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1 | 1fc3d392 | aurel32 | /*
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2 | 1fc3d392 | aurel32 | * QEMU G364 framebuffer Emulator.
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3 | 1fc3d392 | aurel32 | *
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4 | 1fc3d392 | aurel32 | * Copyright (c) 2007-2008 Hervé Poussineau
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5 | 1fc3d392 | aurel32 | *
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6 | 1fc3d392 | aurel32 | * This program is free software; you can redistribute it and/or
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7 | 1fc3d392 | aurel32 | * modify it under the terms of the GNU General Public License as
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8 | 1fc3d392 | aurel32 | * published by the Free Software Foundation; either version 2 of
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9 | 1fc3d392 | aurel32 | * the License, or (at your option) any later version.
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10 | 1fc3d392 | aurel32 | *
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11 | 1fc3d392 | aurel32 | * This program is distributed in the hope that it will be useful,
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12 | 1fc3d392 | aurel32 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 1fc3d392 | aurel32 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | 1fc3d392 | aurel32 | * GNU General Public License for more details.
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15 | 1fc3d392 | aurel32 | *
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16 | 1fc3d392 | aurel32 | * You should have received a copy of the GNU General Public License
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17 | 1fc3d392 | aurel32 | * along with this program; if not, write to the Free Software
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18 | 1fc3d392 | aurel32 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | 1fc3d392 | aurel32 | * MA 02111-1307 USA
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20 | 1fc3d392 | aurel32 | */
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21 | 1fc3d392 | aurel32 | |
22 | 1fc3d392 | aurel32 | #include "hw.h" |
23 | 1fc3d392 | aurel32 | #include "console.h" |
24 | 1fc3d392 | aurel32 | #include "pixel_ops.h" |
25 | 1fc3d392 | aurel32 | |
26 | 1fc3d392 | aurel32 | //#define DEBUG_G364
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27 | 1fc3d392 | aurel32 | |
28 | 1fc3d392 | aurel32 | typedef struct G364State { |
29 | 1fc3d392 | aurel32 | target_phys_addr_t vram_base; |
30 | 1fc3d392 | aurel32 | unsigned int vram_size; |
31 | 1fc3d392 | aurel32 | uint8_t *vram_buffer; |
32 | 1fc3d392 | aurel32 | uint32_t ctla; |
33 | 1fc3d392 | aurel32 | uint8_t palette[256][3]; |
34 | 1fc3d392 | aurel32 | /* display refresh support */
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35 | 1fc3d392 | aurel32 | DisplayState *ds; |
36 | c60e08d9 | pbrook | QEMUConsole *console; |
37 | 1fc3d392 | aurel32 | int graphic_mode;
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38 | 1fc3d392 | aurel32 | uint32_t scr_width, scr_height; /* in pixels */
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39 | 1fc3d392 | aurel32 | } G364State; |
40 | 1fc3d392 | aurel32 | |
41 | 1fc3d392 | aurel32 | /*
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42 | 1fc3d392 | aurel32 | * graphic modes
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43 | 1fc3d392 | aurel32 | */
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44 | 1fc3d392 | aurel32 | #define BPP 8 |
45 | 1fc3d392 | aurel32 | #define PIXEL_WIDTH 8 |
46 | 1fc3d392 | aurel32 | #include "g364fb_template.h" |
47 | 1fc3d392 | aurel32 | #undef BPP
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48 | 1fc3d392 | aurel32 | #undef PIXEL_WIDTH
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49 | 1fc3d392 | aurel32 | |
50 | 1fc3d392 | aurel32 | #define BPP 15 |
51 | 1fc3d392 | aurel32 | #define PIXEL_WIDTH 16 |
52 | 1fc3d392 | aurel32 | #include "g364fb_template.h" |
53 | 1fc3d392 | aurel32 | #undef BPP
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54 | 1fc3d392 | aurel32 | #undef PIXEL_WIDTH
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55 | 1fc3d392 | aurel32 | |
56 | 1fc3d392 | aurel32 | #define BPP 16 |
57 | 1fc3d392 | aurel32 | #define PIXEL_WIDTH 16 |
58 | 1fc3d392 | aurel32 | #include "g364fb_template.h" |
59 | 1fc3d392 | aurel32 | #undef BPP
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60 | 1fc3d392 | aurel32 | #undef PIXEL_WIDTH
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61 | 1fc3d392 | aurel32 | |
62 | 1fc3d392 | aurel32 | #define BPP 32 |
63 | 1fc3d392 | aurel32 | #define PIXEL_WIDTH 32 |
64 | 1fc3d392 | aurel32 | #include "g364fb_template.h" |
65 | 1fc3d392 | aurel32 | #undef BPP
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66 | 1fc3d392 | aurel32 | #undef PIXEL_WIDTH
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67 | 1fc3d392 | aurel32 | |
68 | 1fc3d392 | aurel32 | #define REG_DISPLAYX 0x0918 |
69 | 1fc3d392 | aurel32 | #define REG_DISPLAYY 0x0940 |
70 | 1fc3d392 | aurel32 | |
71 | 1fc3d392 | aurel32 | #define CTLA_FORCE_BLANK 0x400 |
72 | 1fc3d392 | aurel32 | |
73 | 1fc3d392 | aurel32 | static void g364fb_draw_graphic(G364State *s, int full_update) |
74 | 1fc3d392 | aurel32 | { |
75 | 1fc3d392 | aurel32 | switch (s->ds->depth) {
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76 | 1fc3d392 | aurel32 | case 8: |
77 | 1fc3d392 | aurel32 | g364fb_draw_graphic8(s, full_update); |
78 | 1fc3d392 | aurel32 | break;
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79 | 1fc3d392 | aurel32 | case 15: |
80 | 1fc3d392 | aurel32 | g364fb_draw_graphic15(s, full_update); |
81 | 1fc3d392 | aurel32 | break;
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82 | 1fc3d392 | aurel32 | case 16: |
83 | 1fc3d392 | aurel32 | g364fb_draw_graphic16(s, full_update); |
84 | 1fc3d392 | aurel32 | break;
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85 | 1fc3d392 | aurel32 | case 32: |
86 | 1fc3d392 | aurel32 | g364fb_draw_graphic32(s, full_update); |
87 | 1fc3d392 | aurel32 | break;
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88 | 1fc3d392 | aurel32 | default:
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89 | 1fc3d392 | aurel32 | printf("g364fb: unknown depth %d\n", s->ds->depth);
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90 | 1fc3d392 | aurel32 | return;
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91 | 1fc3d392 | aurel32 | } |
92 | 1fc3d392 | aurel32 | |
93 | 221bb2d5 | aurel32 | dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
94 | 1fc3d392 | aurel32 | } |
95 | 1fc3d392 | aurel32 | |
96 | 1fc3d392 | aurel32 | static void g364fb_draw_blank(G364State *s, int full_update) |
97 | 1fc3d392 | aurel32 | { |
98 | 1fc3d392 | aurel32 | int i, w;
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99 | 1fc3d392 | aurel32 | uint8_t *d; |
100 | 1fc3d392 | aurel32 | |
101 | 1fc3d392 | aurel32 | if (!full_update)
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102 | 1fc3d392 | aurel32 | return;
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103 | 1fc3d392 | aurel32 | |
104 | 221bb2d5 | aurel32 | w = s->scr_width * ((s->ds->depth + 7) >> 3); |
105 | 1fc3d392 | aurel32 | d = s->ds->data; |
106 | 221bb2d5 | aurel32 | for(i = 0; i < s->scr_height; i++) { |
107 | 1fc3d392 | aurel32 | memset(d, 0, w);
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108 | 1fc3d392 | aurel32 | d += s->ds->linesize; |
109 | 1fc3d392 | aurel32 | } |
110 | 221bb2d5 | aurel32 | |
111 | 221bb2d5 | aurel32 | dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); |
112 | 1fc3d392 | aurel32 | } |
113 | 1fc3d392 | aurel32 | |
114 | 1fc3d392 | aurel32 | #define GMODE_GRAPH 0 |
115 | 1fc3d392 | aurel32 | #define GMODE_BLANK 1 |
116 | 1fc3d392 | aurel32 | |
117 | 1fc3d392 | aurel32 | static void g364fb_update_display(void *opaque) |
118 | 1fc3d392 | aurel32 | { |
119 | 1fc3d392 | aurel32 | G364State *s = opaque; |
120 | 1fc3d392 | aurel32 | int full_update, graphic_mode;
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121 | 1fc3d392 | aurel32 | |
122 | 221bb2d5 | aurel32 | if (s->scr_width == 0 || s->scr_height == 0) |
123 | 221bb2d5 | aurel32 | return;
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124 | 221bb2d5 | aurel32 | |
125 | 1fc3d392 | aurel32 | if (s->ctla & CTLA_FORCE_BLANK)
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126 | 1fc3d392 | aurel32 | graphic_mode = GMODE_BLANK; |
127 | 1fc3d392 | aurel32 | else
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128 | 1fc3d392 | aurel32 | graphic_mode = GMODE_GRAPH; |
129 | 1fc3d392 | aurel32 | full_update = 0;
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130 | 1fc3d392 | aurel32 | if (graphic_mode != s->graphic_mode) {
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131 | 1fc3d392 | aurel32 | s->graphic_mode = graphic_mode; |
132 | 1fc3d392 | aurel32 | full_update = 1;
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133 | 1fc3d392 | aurel32 | } |
134 | 221bb2d5 | aurel32 | if (s->scr_width != s->ds->width || s->scr_height != s->ds->height) {
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135 | 221bb2d5 | aurel32 | qemu_console_resize(s->console, s->scr_width, s->scr_height); |
136 | 221bb2d5 | aurel32 | full_update = 1;
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137 | 221bb2d5 | aurel32 | } |
138 | 1fc3d392 | aurel32 | switch(graphic_mode) {
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139 | 1fc3d392 | aurel32 | case GMODE_GRAPH:
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140 | 1fc3d392 | aurel32 | g364fb_draw_graphic(s, full_update); |
141 | 1fc3d392 | aurel32 | break;
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142 | 1fc3d392 | aurel32 | case GMODE_BLANK:
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143 | 1fc3d392 | aurel32 | default:
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144 | 1fc3d392 | aurel32 | g364fb_draw_blank(s, full_update); |
145 | 1fc3d392 | aurel32 | break;
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146 | 1fc3d392 | aurel32 | } |
147 | 1fc3d392 | aurel32 | } |
148 | 1fc3d392 | aurel32 | |
149 | 1fc3d392 | aurel32 | /* force a full display refresh */
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150 | 1fc3d392 | aurel32 | static void g364fb_invalidate_display(void *opaque) |
151 | 1fc3d392 | aurel32 | { |
152 | 1fc3d392 | aurel32 | G364State *s = opaque; |
153 | 1fc3d392 | aurel32 | s->graphic_mode = -1; /* force full update */ |
154 | 1fc3d392 | aurel32 | } |
155 | 1fc3d392 | aurel32 | |
156 | 1fc3d392 | aurel32 | static void g364fb_reset(void *opaque) |
157 | 1fc3d392 | aurel32 | { |
158 | 1fc3d392 | aurel32 | G364State *s = opaque; |
159 | 1fc3d392 | aurel32 | |
160 | 1fc3d392 | aurel32 | memset(s->palette, 0, sizeof(s->palette)); |
161 | 1fc3d392 | aurel32 | s->scr_width = s->scr_height = 0;
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162 | 1fc3d392 | aurel32 | memset(s->vram_buffer, 0, s->vram_size);
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163 | 1fc3d392 | aurel32 | s->graphic_mode = -1; /* force full update */ |
164 | 1fc3d392 | aurel32 | } |
165 | 1fc3d392 | aurel32 | |
166 | 1fc3d392 | aurel32 | static void g364fb_screen_dump(void *opaque, const char *filename) |
167 | 1fc3d392 | aurel32 | { |
168 | 1fc3d392 | aurel32 | G364State *s = opaque; |
169 | 1fc3d392 | aurel32 | int y, x;
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170 | 1fc3d392 | aurel32 | uint8_t index; |
171 | 1fc3d392 | aurel32 | uint8_t *data_buffer; |
172 | 1fc3d392 | aurel32 | FILE *f; |
173 | 1fc3d392 | aurel32 | |
174 | 1fc3d392 | aurel32 | f = fopen(filename, "wb");
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175 | 1fc3d392 | aurel32 | if (!f)
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176 | 1fc3d392 | aurel32 | return;
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177 | 1fc3d392 | aurel32 | |
178 | 1fc3d392 | aurel32 | data_buffer = s->vram_buffer; |
179 | 1fc3d392 | aurel32 | fprintf(f, "P6\n%d %d\n%d\n",
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180 | 1fc3d392 | aurel32 | s->scr_width, s->scr_height, 255);
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181 | 1fc3d392 | aurel32 | for(y = 0; y < s->scr_height; y++) |
182 | 1fc3d392 | aurel32 | for(x = 0; x < s->scr_width; x++, data_buffer++) { |
183 | 1fc3d392 | aurel32 | index = *data_buffer; |
184 | 1fc3d392 | aurel32 | fputc(s->palette[index][0], f);
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185 | 1fc3d392 | aurel32 | fputc(s->palette[index][1], f);
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186 | 1fc3d392 | aurel32 | fputc(s->palette[index][2], f);
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187 | 1fc3d392 | aurel32 | } |
188 | 1fc3d392 | aurel32 | fclose(f); |
189 | 1fc3d392 | aurel32 | } |
190 | 1fc3d392 | aurel32 | |
191 | 1fc3d392 | aurel32 | /* called for accesses to io ports */
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192 | 1fc3d392 | aurel32 | static uint32_t g364fb_ctrl_readb(void *opaque, target_phys_addr_t addr) |
193 | 1fc3d392 | aurel32 | { |
194 | 1fc3d392 | aurel32 | //G364State *s = opaque;
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195 | 1fc3d392 | aurel32 | uint32_t val; |
196 | 1fc3d392 | aurel32 | |
197 | 1fc3d392 | aurel32 | addr &= 0xffff;
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198 | 1fc3d392 | aurel32 | |
199 | 1fc3d392 | aurel32 | switch (addr) {
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200 | 1fc3d392 | aurel32 | default:
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201 | 1fc3d392 | aurel32 | #ifdef DEBUG_G364
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202 | 1fc3d392 | aurel32 | printf("g364fb/ctrl: invalid read at [" TARGET_FMT_lx "]\n", addr); |
203 | 1fc3d392 | aurel32 | #endif
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204 | 1fc3d392 | aurel32 | val = 0;
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205 | 1fc3d392 | aurel32 | break;
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206 | 1fc3d392 | aurel32 | } |
207 | 1fc3d392 | aurel32 | |
208 | 1fc3d392 | aurel32 | #ifdef DEBUG_G364
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209 | 1fc3d392 | aurel32 | printf("g364fb/ctrl: read 0x%02x at [" TARGET_FMT_lx "]\n", val, addr); |
210 | 1fc3d392 | aurel32 | #endif
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211 | 1fc3d392 | aurel32 | |
212 | 1fc3d392 | aurel32 | return val;
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213 | 1fc3d392 | aurel32 | } |
214 | 1fc3d392 | aurel32 | |
215 | 1fc3d392 | aurel32 | static uint32_t g364fb_ctrl_readw(void *opaque, target_phys_addr_t addr) |
216 | 1fc3d392 | aurel32 | { |
217 | 1fc3d392 | aurel32 | uint32_t v; |
218 | 1fc3d392 | aurel32 | v = g364fb_ctrl_readb(opaque, addr); |
219 | 1fc3d392 | aurel32 | v |= g364fb_ctrl_readb(opaque, addr + 1) << 8; |
220 | 1fc3d392 | aurel32 | return v;
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221 | 1fc3d392 | aurel32 | } |
222 | 1fc3d392 | aurel32 | |
223 | 1fc3d392 | aurel32 | static uint32_t g364fb_ctrl_readl(void *opaque, target_phys_addr_t addr) |
224 | 1fc3d392 | aurel32 | { |
225 | 1fc3d392 | aurel32 | uint32_t v; |
226 | 1fc3d392 | aurel32 | v = g364fb_ctrl_readb(opaque, addr); |
227 | 1fc3d392 | aurel32 | v |= g364fb_ctrl_readb(opaque, addr + 1) << 8; |
228 | 1fc3d392 | aurel32 | v |= g364fb_ctrl_readb(opaque, addr + 2) << 16; |
229 | 1fc3d392 | aurel32 | v |= g364fb_ctrl_readb(opaque, addr + 3) << 24; |
230 | 1fc3d392 | aurel32 | return v;
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231 | 1fc3d392 | aurel32 | } |
232 | 1fc3d392 | aurel32 | |
233 | 1fc3d392 | aurel32 | static void g364fb_ctrl_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
234 | 1fc3d392 | aurel32 | { |
235 | 1fc3d392 | aurel32 | G364State *s = opaque; |
236 | 1fc3d392 | aurel32 | |
237 | 1fc3d392 | aurel32 | addr &= 0xffff;
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238 | 1fc3d392 | aurel32 | |
239 | 1fc3d392 | aurel32 | #ifdef DEBUG_G364
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240 | 1fc3d392 | aurel32 | printf("g364fb/ctrl: write 0x%02x at [" TARGET_FMT_lx "]\n", val, addr); |
241 | 1fc3d392 | aurel32 | #endif
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242 | 1fc3d392 | aurel32 | |
243 | 1fc3d392 | aurel32 | if (addr < 0x0800) { |
244 | 1fc3d392 | aurel32 | /* color palette */
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245 | 1fc3d392 | aurel32 | int idx = addr >> 3; |
246 | 1fc3d392 | aurel32 | int c = addr & 7; |
247 | 1fc3d392 | aurel32 | if (c < 3) |
248 | 1fc3d392 | aurel32 | s->palette[idx][c] = (uint8_t)val; |
249 | 1fc3d392 | aurel32 | } else {
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250 | 1fc3d392 | aurel32 | switch (addr) {
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251 | 1fc3d392 | aurel32 | case REG_DISPLAYX:
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252 | 1fc3d392 | aurel32 | s->scr_width = (s->scr_width & 0xfffffc03) | (val << 2); |
253 | 1fc3d392 | aurel32 | break;
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254 | 1fc3d392 | aurel32 | case REG_DISPLAYX + 1: |
255 | 1fc3d392 | aurel32 | s->scr_width = (s->scr_width & 0xfffc03ff) | (val << 10); |
256 | 1fc3d392 | aurel32 | break;
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257 | 1fc3d392 | aurel32 | case REG_DISPLAYY:
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258 | 1fc3d392 | aurel32 | s->scr_height = (s->scr_height & 0xffffff80) | (val >> 1); |
259 | 1fc3d392 | aurel32 | break;
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260 | 1fc3d392 | aurel32 | case REG_DISPLAYY + 1: |
261 | 1fc3d392 | aurel32 | s->scr_height = (s->scr_height & 0xffff801f) | (val << 7); |
262 | 1fc3d392 | aurel32 | break;
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263 | 1fc3d392 | aurel32 | default:
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264 | 1fc3d392 | aurel32 | #ifdef DEBUG_G364
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265 | 1fc3d392 | aurel32 | printf("g364fb/ctrl: invalid write of 0x%02x at [" TARGET_FMT_lx "]\n", val, addr); |
266 | 1fc3d392 | aurel32 | #endif
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267 | 1fc3d392 | aurel32 | break;
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268 | 1fc3d392 | aurel32 | } |
269 | 1fc3d392 | aurel32 | } |
270 | c60e08d9 | pbrook | s->graphic_mode = -1; /* force full update */ |
271 | 1fc3d392 | aurel32 | } |
272 | 1fc3d392 | aurel32 | |
273 | 1fc3d392 | aurel32 | static void g364fb_ctrl_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
274 | 1fc3d392 | aurel32 | { |
275 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb(opaque, addr, val & 0xff);
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276 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
277 | 1fc3d392 | aurel32 | } |
278 | 1fc3d392 | aurel32 | |
279 | 1fc3d392 | aurel32 | static void g364fb_ctrl_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
280 | 1fc3d392 | aurel32 | { |
281 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb(opaque, addr, val & 0xff);
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282 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
283 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
284 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
285 | 1fc3d392 | aurel32 | } |
286 | 1fc3d392 | aurel32 | |
287 | 1fc3d392 | aurel32 | static CPUReadMemoryFunc *g364fb_ctrl_read[3] = { |
288 | 1fc3d392 | aurel32 | g364fb_ctrl_readb, |
289 | 1fc3d392 | aurel32 | g364fb_ctrl_readw, |
290 | 1fc3d392 | aurel32 | g364fb_ctrl_readl, |
291 | 1fc3d392 | aurel32 | }; |
292 | 1fc3d392 | aurel32 | |
293 | 1fc3d392 | aurel32 | static CPUWriteMemoryFunc *g364fb_ctrl_write[3] = { |
294 | 1fc3d392 | aurel32 | g364fb_ctrl_writeb, |
295 | 1fc3d392 | aurel32 | g364fb_ctrl_writew, |
296 | 1fc3d392 | aurel32 | g364fb_ctrl_writel, |
297 | 1fc3d392 | aurel32 | }; |
298 | 1fc3d392 | aurel32 | |
299 | 1fc3d392 | aurel32 | /* called for accesses to video ram */
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300 | 1fc3d392 | aurel32 | static uint32_t g364fb_mem_readb(void *opaque, target_phys_addr_t addr) |
301 | 1fc3d392 | aurel32 | { |
302 | 1fc3d392 | aurel32 | G364State *s = opaque; |
303 | 1fc3d392 | aurel32 | target_phys_addr_t relative_addr = addr - s->vram_base; |
304 | 1fc3d392 | aurel32 | |
305 | 1fc3d392 | aurel32 | return s->vram_buffer[relative_addr];
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306 | 1fc3d392 | aurel32 | } |
307 | 1fc3d392 | aurel32 | |
308 | 1fc3d392 | aurel32 | static uint32_t g364fb_mem_readw(void *opaque, target_phys_addr_t addr) |
309 | 1fc3d392 | aurel32 | { |
310 | 1fc3d392 | aurel32 | uint32_t v; |
311 | 1fc3d392 | aurel32 | v = g364fb_mem_readb(opaque, addr); |
312 | 1fc3d392 | aurel32 | v |= g364fb_mem_readb(opaque, addr + 1) << 8; |
313 | 1fc3d392 | aurel32 | return v;
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314 | 1fc3d392 | aurel32 | } |
315 | 1fc3d392 | aurel32 | |
316 | 1fc3d392 | aurel32 | static uint32_t g364fb_mem_readl(void *opaque, target_phys_addr_t addr) |
317 | 1fc3d392 | aurel32 | { |
318 | 1fc3d392 | aurel32 | uint32_t v; |
319 | 1fc3d392 | aurel32 | v = g364fb_mem_readb(opaque, addr); |
320 | 1fc3d392 | aurel32 | v |= g364fb_mem_readb(opaque, addr + 1) << 8; |
321 | 1fc3d392 | aurel32 | v |= g364fb_mem_readb(opaque, addr + 2) << 16; |
322 | 1fc3d392 | aurel32 | v |= g364fb_mem_readb(opaque, addr + 3) << 24; |
323 | 1fc3d392 | aurel32 | return v;
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324 | 1fc3d392 | aurel32 | } |
325 | 1fc3d392 | aurel32 | |
326 | 1fc3d392 | aurel32 | static void g364fb_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
327 | 1fc3d392 | aurel32 | { |
328 | 1fc3d392 | aurel32 | G364State *s = opaque; |
329 | 1fc3d392 | aurel32 | target_phys_addr_t relative_addr = addr - s->vram_base; |
330 | 1fc3d392 | aurel32 | |
331 | 1fc3d392 | aurel32 | s->vram_buffer[relative_addr] = val; |
332 | 1fc3d392 | aurel32 | } |
333 | 1fc3d392 | aurel32 | |
334 | 1fc3d392 | aurel32 | static void g364fb_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
335 | 1fc3d392 | aurel32 | { |
336 | 1fc3d392 | aurel32 | g364fb_mem_writeb(opaque, addr, val & 0xff);
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337 | 1fc3d392 | aurel32 | g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
338 | 1fc3d392 | aurel32 | } |
339 | 1fc3d392 | aurel32 | |
340 | 1fc3d392 | aurel32 | static void g364fb_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
341 | 1fc3d392 | aurel32 | { |
342 | 1fc3d392 | aurel32 | g364fb_mem_writeb(opaque, addr, val & 0xff);
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343 | 1fc3d392 | aurel32 | g364fb_mem_writeb(opaque, addr + 1, (val >> 8) & 0xff); |
344 | 1fc3d392 | aurel32 | g364fb_mem_writeb(opaque, addr + 2, (val >> 16) & 0xff); |
345 | 1fc3d392 | aurel32 | g364fb_mem_writeb(opaque, addr + 3, (val >> 24) & 0xff); |
346 | 1fc3d392 | aurel32 | } |
347 | 1fc3d392 | aurel32 | |
348 | 1fc3d392 | aurel32 | static CPUReadMemoryFunc *g364fb_mem_read[3] = { |
349 | 1fc3d392 | aurel32 | g364fb_mem_readb, |
350 | 1fc3d392 | aurel32 | g364fb_mem_readw, |
351 | 1fc3d392 | aurel32 | g364fb_mem_readl, |
352 | 1fc3d392 | aurel32 | }; |
353 | 1fc3d392 | aurel32 | |
354 | 1fc3d392 | aurel32 | static CPUWriteMemoryFunc *g364fb_mem_write[3] = { |
355 | 1fc3d392 | aurel32 | g364fb_mem_writeb, |
356 | 1fc3d392 | aurel32 | g364fb_mem_writew, |
357 | 1fc3d392 | aurel32 | g364fb_mem_writel, |
358 | 1fc3d392 | aurel32 | }; |
359 | 1fc3d392 | aurel32 | |
360 | 1fc3d392 | aurel32 | int g364fb_mm_init(DisplayState *ds,
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361 | 1fc3d392 | aurel32 | int vram_size, int it_shift, |
362 | 1fc3d392 | aurel32 | target_phys_addr_t vram_base, target_phys_addr_t ctrl_base) |
363 | 1fc3d392 | aurel32 | { |
364 | 1fc3d392 | aurel32 | G364State *s; |
365 | 1fc3d392 | aurel32 | int io_vram, io_ctrl;
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366 | 1fc3d392 | aurel32 | |
367 | 1fc3d392 | aurel32 | s = qemu_mallocz(sizeof(G364State));
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368 | 1fc3d392 | aurel32 | if (!s)
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369 | 1fc3d392 | aurel32 | return -1; |
370 | 1fc3d392 | aurel32 | |
371 | 1fc3d392 | aurel32 | s->vram_size = vram_size; |
372 | 1fc3d392 | aurel32 | s->vram_buffer = qemu_mallocz(s->vram_size); |
373 | 1fc3d392 | aurel32 | |
374 | 1fc3d392 | aurel32 | qemu_register_reset(g364fb_reset, s); |
375 | 1fc3d392 | aurel32 | g364fb_reset(s); |
376 | 1fc3d392 | aurel32 | |
377 | 1fc3d392 | aurel32 | s->ds = ds; |
378 | 1fc3d392 | aurel32 | s->vram_base = vram_base; |
379 | 1fc3d392 | aurel32 | |
380 | c60e08d9 | pbrook | s->console = graphic_console_init(ds, g364fb_update_display, |
381 | c60e08d9 | pbrook | g364fb_invalidate_display, |
382 | c60e08d9 | pbrook | g364fb_screen_dump, NULL, s);
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383 | 1fc3d392 | aurel32 | |
384 | 1fc3d392 | aurel32 | io_vram = cpu_register_io_memory(0, g364fb_mem_read, g364fb_mem_write, s);
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385 | 1fc3d392 | aurel32 | cpu_register_physical_memory(s->vram_base, vram_size, io_vram); |
386 | 1fc3d392 | aurel32 | |
387 | 1fc3d392 | aurel32 | io_ctrl = cpu_register_io_memory(0, g364fb_ctrl_read, g364fb_ctrl_write, s);
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388 | 1fc3d392 | aurel32 | cpu_register_physical_memory(ctrl_base, 0x10000, io_ctrl);
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389 | 1fc3d392 | aurel32 | |
390 | 1fc3d392 | aurel32 | return 0; |
391 | 1fc3d392 | aurel32 | } |