root / hw / omap_mmc.c @ fcdd25ab
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1 | b30bb3a2 | balrog | /*
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2 | b30bb3a2 | balrog | * OMAP on-chip MMC/SD host emulation.
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3 | b30bb3a2 | balrog | *
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4 | b30bb3a2 | balrog | * Copyright (C) 2006-2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | b30bb3a2 | balrog | *
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6 | b30bb3a2 | balrog | * This program is free software; you can redistribute it and/or
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7 | b30bb3a2 | balrog | * modify it under the terms of the GNU General Public License as
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8 | 827df9f3 | balrog | * published by the Free Software Foundation; either version 2 or
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9 | 827df9f3 | balrog | * (at your option) version 3 of the License.
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10 | b30bb3a2 | balrog | *
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11 | b30bb3a2 | balrog | * This program is distributed in the hope that it will be useful,
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12 | b30bb3a2 | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | b30bb3a2 | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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14 | b30bb3a2 | balrog | * GNU General Public License for more details.
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15 | b30bb3a2 | balrog | *
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16 | b30bb3a2 | balrog | * You should have received a copy of the GNU General Public License
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17 | b30bb3a2 | balrog | * along with this program; if not, write to the Free Software
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18 | b30bb3a2 | balrog | * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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19 | b30bb3a2 | balrog | * MA 02111-1307 USA
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20 | b30bb3a2 | balrog | */
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21 | 87ecb68b | pbrook | #include "hw.h" |
22 | 87ecb68b | pbrook | #include "omap.h" |
23 | b30bb3a2 | balrog | #include "sd.h" |
24 | b30bb3a2 | balrog | |
25 | b30bb3a2 | balrog | struct omap_mmc_s {
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26 | b30bb3a2 | balrog | target_phys_addr_t base; |
27 | b30bb3a2 | balrog | qemu_irq irq; |
28 | b30bb3a2 | balrog | qemu_irq *dma; |
29 | 827df9f3 | balrog | qemu_irq coverswitch; |
30 | b30bb3a2 | balrog | omap_clk clk; |
31 | b30bb3a2 | balrog | SDState *card; |
32 | b30bb3a2 | balrog | uint16_t last_cmd; |
33 | b30bb3a2 | balrog | uint16_t sdio; |
34 | b30bb3a2 | balrog | uint16_t rsp[8];
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35 | b30bb3a2 | balrog | uint32_t arg; |
36 | 827df9f3 | balrog | int lines;
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37 | b30bb3a2 | balrog | int dw;
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38 | b30bb3a2 | balrog | int mode;
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39 | b30bb3a2 | balrog | int enable;
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40 | 827df9f3 | balrog | int be;
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41 | 827df9f3 | balrog | int rev;
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42 | b30bb3a2 | balrog | uint16_t status; |
43 | b30bb3a2 | balrog | uint16_t mask; |
44 | b30bb3a2 | balrog | uint8_t cto; |
45 | b30bb3a2 | balrog | uint16_t dto; |
46 | 827df9f3 | balrog | int clkdiv;
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47 | b30bb3a2 | balrog | uint16_t fifo[32];
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48 | b30bb3a2 | balrog | int fifo_start;
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49 | b30bb3a2 | balrog | int fifo_len;
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50 | b30bb3a2 | balrog | uint16_t blen; |
51 | b30bb3a2 | balrog | uint16_t blen_counter; |
52 | b30bb3a2 | balrog | uint16_t nblk; |
53 | b30bb3a2 | balrog | uint16_t nblk_counter; |
54 | b30bb3a2 | balrog | int tx_dma;
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55 | b30bb3a2 | balrog | int rx_dma;
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56 | b30bb3a2 | balrog | int af_level;
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57 | b30bb3a2 | balrog | int ae_level;
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58 | b30bb3a2 | balrog | |
59 | b30bb3a2 | balrog | int ddir;
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60 | b30bb3a2 | balrog | int transfer;
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61 | 827df9f3 | balrog | |
62 | 827df9f3 | balrog | int cdet_wakeup;
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63 | 827df9f3 | balrog | int cdet_enable;
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64 | 827df9f3 | balrog | int cdet_state;
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65 | 827df9f3 | balrog | qemu_irq cdet; |
66 | b30bb3a2 | balrog | }; |
67 | b30bb3a2 | balrog | |
68 | b30bb3a2 | balrog | static void omap_mmc_interrupts_update(struct omap_mmc_s *s) |
69 | b30bb3a2 | balrog | { |
70 | b30bb3a2 | balrog | qemu_set_irq(s->irq, !!(s->status & s->mask)); |
71 | b30bb3a2 | balrog | } |
72 | b30bb3a2 | balrog | |
73 | b30bb3a2 | balrog | static void omap_mmc_fifolevel_update(struct omap_mmc_s *host) |
74 | b30bb3a2 | balrog | { |
75 | b30bb3a2 | balrog | if (!host->transfer && !host->fifo_len) {
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76 | b30bb3a2 | balrog | host->status &= 0xf3ff;
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77 | b30bb3a2 | balrog | return;
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78 | b30bb3a2 | balrog | } |
79 | b30bb3a2 | balrog | |
80 | b30bb3a2 | balrog | if (host->fifo_len > host->af_level && host->ddir) {
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81 | b30bb3a2 | balrog | if (host->rx_dma) {
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82 | b30bb3a2 | balrog | host->status &= 0xfbff;
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83 | b30bb3a2 | balrog | qemu_irq_raise(host->dma[1]);
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84 | b30bb3a2 | balrog | } else
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85 | b30bb3a2 | balrog | host->status |= 0x0400;
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86 | b30bb3a2 | balrog | } else {
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87 | b30bb3a2 | balrog | host->status &= 0xfbff;
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88 | b30bb3a2 | balrog | qemu_irq_lower(host->dma[1]);
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89 | b30bb3a2 | balrog | } |
90 | b30bb3a2 | balrog | |
91 | b30bb3a2 | balrog | if (host->fifo_len < host->ae_level && !host->ddir) {
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92 | b30bb3a2 | balrog | if (host->tx_dma) {
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93 | b30bb3a2 | balrog | host->status &= 0xf7ff;
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94 | b30bb3a2 | balrog | qemu_irq_raise(host->dma[0]);
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95 | b30bb3a2 | balrog | } else
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96 | b30bb3a2 | balrog | host->status |= 0x0800;
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97 | b30bb3a2 | balrog | } else {
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98 | b30bb3a2 | balrog | qemu_irq_lower(host->dma[0]);
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99 | b30bb3a2 | balrog | host->status &= 0xf7ff;
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100 | b30bb3a2 | balrog | } |
101 | b30bb3a2 | balrog | } |
102 | b30bb3a2 | balrog | |
103 | b30bb3a2 | balrog | typedef enum { |
104 | b30bb3a2 | balrog | sd_nore = 0, /* no response */ |
105 | b30bb3a2 | balrog | sd_r1, /* normal response command */
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106 | b30bb3a2 | balrog | sd_r2, /* CID, CSD registers */
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107 | b30bb3a2 | balrog | sd_r3, /* OCR register */
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108 | b30bb3a2 | balrog | sd_r6 = 6, /* Published RCA response */ |
109 | b30bb3a2 | balrog | sd_r1b = -1,
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110 | b30bb3a2 | balrog | } sd_rsp_type_t; |
111 | b30bb3a2 | balrog | |
112 | b30bb3a2 | balrog | static void omap_mmc_command(struct omap_mmc_s *host, int cmd, int dir, |
113 | b30bb3a2 | balrog | sd_cmd_type_t type, int busy, sd_rsp_type_t resptype, int init) |
114 | b30bb3a2 | balrog | { |
115 | b30bb3a2 | balrog | uint32_t rspstatus, mask; |
116 | b30bb3a2 | balrog | int rsplen, timeout;
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117 | b30bb3a2 | balrog | struct sd_request_s request;
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118 | b30bb3a2 | balrog | uint8_t response[16];
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119 | b30bb3a2 | balrog | |
120 | 827df9f3 | balrog | if (init && cmd == 0) { |
121 | 827df9f3 | balrog | host->status |= 0x0001;
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122 | 827df9f3 | balrog | return;
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123 | 827df9f3 | balrog | } |
124 | 827df9f3 | balrog | |
125 | b30bb3a2 | balrog | if (resptype == sd_r1 && busy)
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126 | b30bb3a2 | balrog | resptype = sd_r1b; |
127 | b30bb3a2 | balrog | |
128 | b30bb3a2 | balrog | if (type == sd_adtc) {
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129 | b30bb3a2 | balrog | host->fifo_start = 0;
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130 | b30bb3a2 | balrog | host->fifo_len = 0;
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131 | b30bb3a2 | balrog | host->transfer = 1;
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132 | b30bb3a2 | balrog | host->ddir = dir; |
133 | b30bb3a2 | balrog | } else
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134 | b30bb3a2 | balrog | host->transfer = 0;
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135 | b30bb3a2 | balrog | timeout = 0;
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136 | b30bb3a2 | balrog | mask = 0;
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137 | b30bb3a2 | balrog | rspstatus = 0;
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138 | b30bb3a2 | balrog | |
139 | b30bb3a2 | balrog | request.cmd = cmd; |
140 | b30bb3a2 | balrog | request.arg = host->arg; |
141 | b30bb3a2 | balrog | request.crc = 0; /* FIXME */ |
142 | b30bb3a2 | balrog | |
143 | b30bb3a2 | balrog | rsplen = sd_do_command(host->card, &request, response); |
144 | b30bb3a2 | balrog | |
145 | b30bb3a2 | balrog | /* TODO: validate CRCs */
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146 | b30bb3a2 | balrog | switch (resptype) {
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147 | b30bb3a2 | balrog | case sd_nore:
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148 | b30bb3a2 | balrog | rsplen = 0;
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149 | b30bb3a2 | balrog | break;
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150 | b30bb3a2 | balrog | |
151 | b30bb3a2 | balrog | case sd_r1:
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152 | b30bb3a2 | balrog | case sd_r1b:
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153 | b30bb3a2 | balrog | if (rsplen < 4) { |
154 | b30bb3a2 | balrog | timeout = 1;
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155 | b30bb3a2 | balrog | break;
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156 | b30bb3a2 | balrog | } |
157 | b30bb3a2 | balrog | rsplen = 4;
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158 | b30bb3a2 | balrog | |
159 | b30bb3a2 | balrog | mask = OUT_OF_RANGE | ADDRESS_ERROR | BLOCK_LEN_ERROR | |
160 | b30bb3a2 | balrog | ERASE_SEQ_ERROR | ERASE_PARAM | WP_VIOLATION | |
161 | b30bb3a2 | balrog | LOCK_UNLOCK_FAILED | COM_CRC_ERROR | ILLEGAL_COMMAND | |
162 | b30bb3a2 | balrog | CARD_ECC_FAILED | CC_ERROR | SD_ERROR | |
163 | b30bb3a2 | balrog | CID_CSD_OVERWRITE; |
164 | b30bb3a2 | balrog | if (host->sdio & (1 << 13)) |
165 | b30bb3a2 | balrog | mask |= AKE_SEQ_ERROR; |
166 | b30bb3a2 | balrog | rspstatus = (response[0] << 24) | (response[1] << 16) | |
167 | b30bb3a2 | balrog | (response[2] << 8) | (response[3] << 0); |
168 | b30bb3a2 | balrog | break;
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169 | b30bb3a2 | balrog | |
170 | b30bb3a2 | balrog | case sd_r2:
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171 | b30bb3a2 | balrog | if (rsplen < 16) { |
172 | b30bb3a2 | balrog | timeout = 1;
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173 | b30bb3a2 | balrog | break;
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174 | b30bb3a2 | balrog | } |
175 | b30bb3a2 | balrog | rsplen = 16;
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176 | b30bb3a2 | balrog | break;
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177 | b30bb3a2 | balrog | |
178 | b30bb3a2 | balrog | case sd_r3:
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179 | b30bb3a2 | balrog | if (rsplen < 4) { |
180 | b30bb3a2 | balrog | timeout = 1;
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181 | b30bb3a2 | balrog | break;
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182 | b30bb3a2 | balrog | } |
183 | b30bb3a2 | balrog | rsplen = 4;
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184 | b30bb3a2 | balrog | |
185 | b30bb3a2 | balrog | rspstatus = (response[0] << 24) | (response[1] << 16) | |
186 | b30bb3a2 | balrog | (response[2] << 8) | (response[3] << 0); |
187 | b30bb3a2 | balrog | if (rspstatus & 0x80000000) |
188 | b30bb3a2 | balrog | host->status &= 0xe000;
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189 | b30bb3a2 | balrog | else
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190 | b30bb3a2 | balrog | host->status |= 0x1000;
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191 | b30bb3a2 | balrog | break;
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192 | b30bb3a2 | balrog | |
193 | b30bb3a2 | balrog | case sd_r6:
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194 | b30bb3a2 | balrog | if (rsplen < 4) { |
195 | b30bb3a2 | balrog | timeout = 1;
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196 | b30bb3a2 | balrog | break;
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197 | b30bb3a2 | balrog | } |
198 | b30bb3a2 | balrog | rsplen = 4;
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199 | b30bb3a2 | balrog | |
200 | b30bb3a2 | balrog | mask = 0xe000 | AKE_SEQ_ERROR;
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201 | b30bb3a2 | balrog | rspstatus = (response[2] << 8) | (response[3] << 0); |
202 | b30bb3a2 | balrog | } |
203 | b30bb3a2 | balrog | |
204 | b30bb3a2 | balrog | if (rspstatus & mask)
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205 | b30bb3a2 | balrog | host->status |= 0x4000;
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206 | b30bb3a2 | balrog | else
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207 | b30bb3a2 | balrog | host->status &= 0xb000;
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208 | b30bb3a2 | balrog | |
209 | b30bb3a2 | balrog | if (rsplen)
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210 | b30bb3a2 | balrog | for (rsplen = 0; rsplen < 8; rsplen ++) |
211 | b30bb3a2 | balrog | host->rsp[~rsplen & 7] = response[(rsplen << 1) | 1] | |
212 | b30bb3a2 | balrog | (response[(rsplen << 1) | 0] << 8); |
213 | b30bb3a2 | balrog | |
214 | b30bb3a2 | balrog | if (timeout)
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215 | b30bb3a2 | balrog | host->status |= 0x0080;
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216 | b30bb3a2 | balrog | else if (cmd == 12) |
217 | b30bb3a2 | balrog | host->status |= 0x0005; /* Makes it more real */ |
218 | b30bb3a2 | balrog | else
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219 | b30bb3a2 | balrog | host->status |= 0x0001;
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220 | b30bb3a2 | balrog | } |
221 | b30bb3a2 | balrog | |
222 | b30bb3a2 | balrog | static void omap_mmc_transfer(struct omap_mmc_s *host) |
223 | b30bb3a2 | balrog | { |
224 | b30bb3a2 | balrog | uint8_t value; |
225 | b30bb3a2 | balrog | |
226 | b30bb3a2 | balrog | if (!host->transfer)
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227 | b30bb3a2 | balrog | return;
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228 | b30bb3a2 | balrog | |
229 | b30bb3a2 | balrog | while (1) { |
230 | b30bb3a2 | balrog | if (host->ddir) {
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231 | b30bb3a2 | balrog | if (host->fifo_len > host->af_level)
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232 | b30bb3a2 | balrog | break;
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233 | b30bb3a2 | balrog | |
234 | b30bb3a2 | balrog | value = sd_read_data(host->card); |
235 | b30bb3a2 | balrog | host->fifo[(host->fifo_start + host->fifo_len) & 31] = value;
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236 | b30bb3a2 | balrog | if (-- host->blen_counter) {
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237 | b30bb3a2 | balrog | value = sd_read_data(host->card); |
238 | b30bb3a2 | balrog | host->fifo[(host->fifo_start + host->fifo_len) & 31] |=
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239 | b30bb3a2 | balrog | value << 8;
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240 | b30bb3a2 | balrog | host->blen_counter --; |
241 | b30bb3a2 | balrog | } |
242 | b30bb3a2 | balrog | |
243 | b30bb3a2 | balrog | host->fifo_len ++; |
244 | b30bb3a2 | balrog | } else {
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245 | b30bb3a2 | balrog | if (!host->fifo_len)
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246 | b30bb3a2 | balrog | break;
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247 | b30bb3a2 | balrog | |
248 | b30bb3a2 | balrog | value = host->fifo[host->fifo_start] & 0xff;
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249 | b30bb3a2 | balrog | sd_write_data(host->card, value); |
250 | b30bb3a2 | balrog | if (-- host->blen_counter) {
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251 | b30bb3a2 | balrog | value = host->fifo[host->fifo_start] >> 8;
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252 | b30bb3a2 | balrog | sd_write_data(host->card, value); |
253 | b30bb3a2 | balrog | host->blen_counter --; |
254 | b30bb3a2 | balrog | } |
255 | b30bb3a2 | balrog | |
256 | b30bb3a2 | balrog | host->fifo_start ++; |
257 | b30bb3a2 | balrog | host->fifo_len --; |
258 | b30bb3a2 | balrog | host->fifo_start &= 31;
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259 | b30bb3a2 | balrog | } |
260 | b30bb3a2 | balrog | |
261 | b30bb3a2 | balrog | if (host->blen_counter == 0) { |
262 | b30bb3a2 | balrog | host->nblk_counter --; |
263 | b30bb3a2 | balrog | host->blen_counter = host->blen; |
264 | b30bb3a2 | balrog | |
265 | b30bb3a2 | balrog | if (host->nblk_counter == 0) { |
266 | b30bb3a2 | balrog | host->nblk_counter = host->nblk; |
267 | b30bb3a2 | balrog | host->transfer = 0;
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268 | b30bb3a2 | balrog | host->status |= 0x0008;
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269 | b30bb3a2 | balrog | break;
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270 | b30bb3a2 | balrog | } |
271 | b30bb3a2 | balrog | } |
272 | b30bb3a2 | balrog | } |
273 | b30bb3a2 | balrog | } |
274 | b30bb3a2 | balrog | |
275 | b30bb3a2 | balrog | static void omap_mmc_update(void *opaque) |
276 | b30bb3a2 | balrog | { |
277 | b30bb3a2 | balrog | struct omap_mmc_s *s = opaque;
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278 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
279 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
280 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
281 | b30bb3a2 | balrog | } |
282 | b30bb3a2 | balrog | |
283 | 827df9f3 | balrog | void omap_mmc_reset(struct omap_mmc_s *host) |
284 | 827df9f3 | balrog | { |
285 | 827df9f3 | balrog | host->last_cmd = 0;
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286 | 827df9f3 | balrog | memset(host->rsp, 0, sizeof(host->rsp)); |
287 | 827df9f3 | balrog | host->arg = 0;
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288 | 827df9f3 | balrog | host->dw = 0;
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289 | 827df9f3 | balrog | host->mode = 0;
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290 | 827df9f3 | balrog | host->enable = 0;
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291 | 827df9f3 | balrog | host->status = 0;
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292 | 827df9f3 | balrog | host->mask = 0;
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293 | 827df9f3 | balrog | host->cto = 0;
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294 | 827df9f3 | balrog | host->dto = 0;
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295 | 827df9f3 | balrog | host->fifo_len = 0;
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296 | 827df9f3 | balrog | host->blen = 0;
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297 | 827df9f3 | balrog | host->blen_counter = 0;
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298 | 827df9f3 | balrog | host->nblk = 0;
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299 | 827df9f3 | balrog | host->nblk_counter = 0;
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300 | 827df9f3 | balrog | host->tx_dma = 0;
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301 | 827df9f3 | balrog | host->rx_dma = 0;
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302 | 827df9f3 | balrog | host->ae_level = 0x00;
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303 | 827df9f3 | balrog | host->af_level = 0x1f;
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304 | 827df9f3 | balrog | host->transfer = 0;
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305 | 827df9f3 | balrog | host->cdet_wakeup = 0;
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306 | 827df9f3 | balrog | host->cdet_enable = 0;
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307 | 827df9f3 | balrog | qemu_set_irq(host->coverswitch, host->cdet_state); |
308 | 827df9f3 | balrog | host->clkdiv = 0;
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309 | 827df9f3 | balrog | } |
310 | 827df9f3 | balrog | |
311 | b30bb3a2 | balrog | static uint32_t omap_mmc_read(void *opaque, target_phys_addr_t offset) |
312 | b30bb3a2 | balrog | { |
313 | b30bb3a2 | balrog | uint16_t i; |
314 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
315 | cf965d24 | balrog | offset &= OMAP_MPUI_REG_MASK; |
316 | b30bb3a2 | balrog | |
317 | b30bb3a2 | balrog | switch (offset) {
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318 | b30bb3a2 | balrog | case 0x00: /* MMC_CMD */ |
319 | b30bb3a2 | balrog | return s->last_cmd;
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320 | b30bb3a2 | balrog | |
321 | b30bb3a2 | balrog | case 0x04: /* MMC_ARGL */ |
322 | b30bb3a2 | balrog | return s->arg & 0x0000ffff; |
323 | b30bb3a2 | balrog | |
324 | b30bb3a2 | balrog | case 0x08: /* MMC_ARGH */ |
325 | b30bb3a2 | balrog | return s->arg >> 16; |
326 | b30bb3a2 | balrog | |
327 | b30bb3a2 | balrog | case 0x0c: /* MMC_CON */ |
328 | 827df9f3 | balrog | return (s->dw << 15) | (s->mode << 12) | (s->enable << 11) | |
329 | 827df9f3 | balrog | (s->be << 10) | s->clkdiv;
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330 | b30bb3a2 | balrog | |
331 | b30bb3a2 | balrog | case 0x10: /* MMC_STAT */ |
332 | b30bb3a2 | balrog | return s->status;
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333 | b30bb3a2 | balrog | |
334 | b30bb3a2 | balrog | case 0x14: /* MMC_IE */ |
335 | b30bb3a2 | balrog | return s->mask;
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336 | b30bb3a2 | balrog | |
337 | b30bb3a2 | balrog | case 0x18: /* MMC_CTO */ |
338 | b30bb3a2 | balrog | return s->cto;
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339 | b30bb3a2 | balrog | |
340 | b30bb3a2 | balrog | case 0x1c: /* MMC_DTO */ |
341 | b30bb3a2 | balrog | return s->dto;
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342 | b30bb3a2 | balrog | |
343 | b30bb3a2 | balrog | case 0x20: /* MMC_DATA */ |
344 | b30bb3a2 | balrog | /* TODO: support 8-bit access */
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345 | b30bb3a2 | balrog | i = s->fifo[s->fifo_start]; |
346 | b30bb3a2 | balrog | if (s->fifo_len == 0) { |
347 | b30bb3a2 | balrog | printf("MMC: FIFO underrun\n");
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348 | b30bb3a2 | balrog | return i;
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349 | b30bb3a2 | balrog | } |
350 | b30bb3a2 | balrog | s->fifo_start ++; |
351 | b30bb3a2 | balrog | s->fifo_len --; |
352 | b30bb3a2 | balrog | s->fifo_start &= 31;
|
353 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
354 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
355 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
356 | b30bb3a2 | balrog | return i;
|
357 | b30bb3a2 | balrog | |
358 | b30bb3a2 | balrog | case 0x24: /* MMC_BLEN */ |
359 | b30bb3a2 | balrog | return s->blen_counter;
|
360 | b30bb3a2 | balrog | |
361 | b30bb3a2 | balrog | case 0x28: /* MMC_NBLK */ |
362 | b30bb3a2 | balrog | return s->nblk_counter;
|
363 | b30bb3a2 | balrog | |
364 | b30bb3a2 | balrog | case 0x2c: /* MMC_BUF */ |
365 | b30bb3a2 | balrog | return (s->rx_dma << 15) | (s->af_level << 8) | |
366 | b30bb3a2 | balrog | (s->tx_dma << 7) | s->ae_level;
|
367 | b30bb3a2 | balrog | |
368 | b30bb3a2 | balrog | case 0x30: /* MMC_SPI */ |
369 | b30bb3a2 | balrog | return 0x0000; |
370 | b30bb3a2 | balrog | case 0x34: /* MMC_SDIO */ |
371 | 827df9f3 | balrog | return (s->cdet_wakeup << 2) | (s->cdet_enable) | s->sdio; |
372 | b30bb3a2 | balrog | case 0x38: /* MMC_SYST */ |
373 | b30bb3a2 | balrog | return 0x0000; |
374 | b30bb3a2 | balrog | |
375 | b30bb3a2 | balrog | case 0x3c: /* MMC_REV */ |
376 | 827df9f3 | balrog | return s->rev;
|
377 | b30bb3a2 | balrog | |
378 | b30bb3a2 | balrog | case 0x40: /* MMC_RSP0 */ |
379 | b30bb3a2 | balrog | case 0x44: /* MMC_RSP1 */ |
380 | b30bb3a2 | balrog | case 0x48: /* MMC_RSP2 */ |
381 | b30bb3a2 | balrog | case 0x4c: /* MMC_RSP3 */ |
382 | b30bb3a2 | balrog | case 0x50: /* MMC_RSP4 */ |
383 | b30bb3a2 | balrog | case 0x54: /* MMC_RSP5 */ |
384 | b30bb3a2 | balrog | case 0x58: /* MMC_RSP6 */ |
385 | b30bb3a2 | balrog | case 0x5c: /* MMC_RSP7 */ |
386 | b30bb3a2 | balrog | return s->rsp[(offset - 0x40) >> 2]; |
387 | 827df9f3 | balrog | |
388 | 827df9f3 | balrog | /* OMAP2-specific */
|
389 | 827df9f3 | balrog | case 0x60: /* MMC_IOSR */ |
390 | 827df9f3 | balrog | case 0x64: /* MMC_SYSC */ |
391 | 827df9f3 | balrog | return 0; |
392 | 827df9f3 | balrog | case 0x68: /* MMC_SYSS */ |
393 | 827df9f3 | balrog | return 1; /* RSTD */ |
394 | b30bb3a2 | balrog | } |
395 | b30bb3a2 | balrog | |
396 | b30bb3a2 | balrog | OMAP_BAD_REG(offset); |
397 | b30bb3a2 | balrog | return 0; |
398 | b30bb3a2 | balrog | } |
399 | b30bb3a2 | balrog | |
400 | b30bb3a2 | balrog | static void omap_mmc_write(void *opaque, target_phys_addr_t offset, |
401 | b30bb3a2 | balrog | uint32_t value) |
402 | b30bb3a2 | balrog | { |
403 | b30bb3a2 | balrog | int i;
|
404 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) opaque; |
405 | cf965d24 | balrog | offset &= OMAP_MPUI_REG_MASK; |
406 | b30bb3a2 | balrog | |
407 | b30bb3a2 | balrog | switch (offset) {
|
408 | b30bb3a2 | balrog | case 0x00: /* MMC_CMD */ |
409 | b30bb3a2 | balrog | if (!s->enable)
|
410 | b30bb3a2 | balrog | break;
|
411 | b30bb3a2 | balrog | |
412 | b30bb3a2 | balrog | s->last_cmd = value; |
413 | b30bb3a2 | balrog | for (i = 0; i < 8; i ++) |
414 | b30bb3a2 | balrog | s->rsp[i] = 0x0000;
|
415 | b30bb3a2 | balrog | omap_mmc_command(s, value & 63, (value >> 15) & 1, |
416 | b30bb3a2 | balrog | (sd_cmd_type_t) ((value >> 12) & 3), |
417 | b30bb3a2 | balrog | (value >> 11) & 1, |
418 | b30bb3a2 | balrog | (sd_rsp_type_t) ((value >> 8) & 7), |
419 | b30bb3a2 | balrog | (value >> 7) & 1); |
420 | b30bb3a2 | balrog | omap_mmc_update(s); |
421 | b30bb3a2 | balrog | break;
|
422 | b30bb3a2 | balrog | |
423 | b30bb3a2 | balrog | case 0x04: /* MMC_ARGL */ |
424 | b30bb3a2 | balrog | s->arg &= 0xffff0000;
|
425 | b30bb3a2 | balrog | s->arg |= 0x0000ffff & value;
|
426 | b30bb3a2 | balrog | break;
|
427 | b30bb3a2 | balrog | |
428 | b30bb3a2 | balrog | case 0x08: /* MMC_ARGH */ |
429 | b30bb3a2 | balrog | s->arg &= 0x0000ffff;
|
430 | b30bb3a2 | balrog | s->arg |= value << 16;
|
431 | b30bb3a2 | balrog | break;
|
432 | b30bb3a2 | balrog | |
433 | b30bb3a2 | balrog | case 0x0c: /* MMC_CON */ |
434 | b30bb3a2 | balrog | s->dw = (value >> 15) & 1; |
435 | b30bb3a2 | balrog | s->mode = (value >> 12) & 3; |
436 | b30bb3a2 | balrog | s->enable = (value >> 11) & 1; |
437 | 827df9f3 | balrog | s->be = (value >> 10) & 1; |
438 | 827df9f3 | balrog | s->clkdiv = (value >> 0) & (s->rev >= 2 ? 0x3ff : 0xff); |
439 | b30bb3a2 | balrog | if (s->mode != 0) |
440 | b30bb3a2 | balrog | printf("SD mode %i unimplemented!\n", s->mode);
|
441 | 827df9f3 | balrog | if (s->be != 0) |
442 | 827df9f3 | balrog | printf("SD FIFO byte sex unimplemented!\n");
|
443 | 827df9f3 | balrog | if (s->dw != 0 && s->lines < 4) |
444 | b30bb3a2 | balrog | printf("4-bit SD bus enabled\n");
|
445 | 827df9f3 | balrog | if (!s->enable)
|
446 | 827df9f3 | balrog | omap_mmc_reset(s); |
447 | b30bb3a2 | balrog | break;
|
448 | b30bb3a2 | balrog | |
449 | b30bb3a2 | balrog | case 0x10: /* MMC_STAT */ |
450 | b30bb3a2 | balrog | s->status &= ~value; |
451 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
452 | b30bb3a2 | balrog | break;
|
453 | b30bb3a2 | balrog | |
454 | b30bb3a2 | balrog | case 0x14: /* MMC_IE */ |
455 | 827df9f3 | balrog | s->mask = value & 0x7fff;
|
456 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
457 | b30bb3a2 | balrog | break;
|
458 | b30bb3a2 | balrog | |
459 | b30bb3a2 | balrog | case 0x18: /* MMC_CTO */ |
460 | b30bb3a2 | balrog | s->cto = value & 0xff;
|
461 | 827df9f3 | balrog | if (s->cto > 0xfd && s->rev <= 1) |
462 | b30bb3a2 | balrog | printf("MMC: CTO of 0xff and 0xfe cannot be used!\n");
|
463 | b30bb3a2 | balrog | break;
|
464 | b30bb3a2 | balrog | |
465 | b30bb3a2 | balrog | case 0x1c: /* MMC_DTO */ |
466 | b30bb3a2 | balrog | s->dto = value & 0xffff;
|
467 | b30bb3a2 | balrog | break;
|
468 | b30bb3a2 | balrog | |
469 | b30bb3a2 | balrog | case 0x20: /* MMC_DATA */ |
470 | b30bb3a2 | balrog | /* TODO: support 8-bit access */
|
471 | b30bb3a2 | balrog | if (s->fifo_len == 32) |
472 | b30bb3a2 | balrog | break;
|
473 | b30bb3a2 | balrog | s->fifo[(s->fifo_start + s->fifo_len) & 31] = value;
|
474 | b30bb3a2 | balrog | s->fifo_len ++; |
475 | b30bb3a2 | balrog | omap_mmc_transfer(s); |
476 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
477 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
478 | b30bb3a2 | balrog | break;
|
479 | b30bb3a2 | balrog | |
480 | b30bb3a2 | balrog | case 0x24: /* MMC_BLEN */ |
481 | b30bb3a2 | balrog | s->blen = (value & 0x07ff) + 1; |
482 | b30bb3a2 | balrog | s->blen_counter = s->blen; |
483 | b30bb3a2 | balrog | break;
|
484 | b30bb3a2 | balrog | |
485 | b30bb3a2 | balrog | case 0x28: /* MMC_NBLK */ |
486 | b30bb3a2 | balrog | s->nblk = (value & 0x07ff) + 1; |
487 | b30bb3a2 | balrog | s->nblk_counter = s->nblk; |
488 | b30bb3a2 | balrog | s->blen_counter = s->blen; |
489 | b30bb3a2 | balrog | break;
|
490 | b30bb3a2 | balrog | |
491 | b30bb3a2 | balrog | case 0x2c: /* MMC_BUF */ |
492 | b30bb3a2 | balrog | s->rx_dma = (value >> 15) & 1; |
493 | b30bb3a2 | balrog | s->af_level = (value >> 8) & 0x1f; |
494 | b30bb3a2 | balrog | s->tx_dma = (value >> 7) & 1; |
495 | b30bb3a2 | balrog | s->ae_level = value & 0x1f;
|
496 | b30bb3a2 | balrog | |
497 | b30bb3a2 | balrog | if (s->rx_dma)
|
498 | b30bb3a2 | balrog | s->status &= 0xfbff;
|
499 | b30bb3a2 | balrog | if (s->tx_dma)
|
500 | b30bb3a2 | balrog | s->status &= 0xf7ff;
|
501 | b30bb3a2 | balrog | omap_mmc_fifolevel_update(s); |
502 | b30bb3a2 | balrog | omap_mmc_interrupts_update(s); |
503 | b30bb3a2 | balrog | break;
|
504 | b30bb3a2 | balrog | |
505 | b30bb3a2 | balrog | /* SPI, SDIO and TEST modes unimplemented */
|
506 | 827df9f3 | balrog | case 0x30: /* MMC_SPI (OMAP1 only) */ |
507 | b30bb3a2 | balrog | break;
|
508 | b30bb3a2 | balrog | case 0x34: /* MMC_SDIO */ |
509 | 827df9f3 | balrog | s->sdio = value & (s->rev >= 2 ? 0xfbf3 : 0x2020); |
510 | 827df9f3 | balrog | s->cdet_wakeup = (value >> 9) & 1; |
511 | 827df9f3 | balrog | s->cdet_enable = (value >> 2) & 1; |
512 | b30bb3a2 | balrog | break;
|
513 | b30bb3a2 | balrog | case 0x38: /* MMC_SYST */ |
514 | b30bb3a2 | balrog | break;
|
515 | b30bb3a2 | balrog | |
516 | b30bb3a2 | balrog | case 0x3c: /* MMC_REV */ |
517 | b30bb3a2 | balrog | case 0x40: /* MMC_RSP0 */ |
518 | b30bb3a2 | balrog | case 0x44: /* MMC_RSP1 */ |
519 | b30bb3a2 | balrog | case 0x48: /* MMC_RSP2 */ |
520 | b30bb3a2 | balrog | case 0x4c: /* MMC_RSP3 */ |
521 | b30bb3a2 | balrog | case 0x50: /* MMC_RSP4 */ |
522 | b30bb3a2 | balrog | case 0x54: /* MMC_RSP5 */ |
523 | b30bb3a2 | balrog | case 0x58: /* MMC_RSP6 */ |
524 | b30bb3a2 | balrog | case 0x5c: /* MMC_RSP7 */ |
525 | b30bb3a2 | balrog | OMAP_RO_REG(offset); |
526 | b30bb3a2 | balrog | break;
|
527 | b30bb3a2 | balrog | |
528 | 827df9f3 | balrog | /* OMAP2-specific */
|
529 | 827df9f3 | balrog | case 0x60: /* MMC_IOSR */ |
530 | 827df9f3 | balrog | if (value & 0xf) |
531 | 827df9f3 | balrog | printf("MMC: SDIO bits used!\n");
|
532 | 827df9f3 | balrog | break;
|
533 | 827df9f3 | balrog | case 0x64: /* MMC_SYSC */ |
534 | 827df9f3 | balrog | if (value & (1 << 2)) /* SRTS */ |
535 | 827df9f3 | balrog | omap_mmc_reset(s); |
536 | 827df9f3 | balrog | break;
|
537 | 827df9f3 | balrog | case 0x68: /* MMC_SYSS */ |
538 | 827df9f3 | balrog | OMAP_RO_REG(offset); |
539 | 827df9f3 | balrog | break;
|
540 | 827df9f3 | balrog | |
541 | b30bb3a2 | balrog | default:
|
542 | b30bb3a2 | balrog | OMAP_BAD_REG(offset); |
543 | b30bb3a2 | balrog | } |
544 | b30bb3a2 | balrog | } |
545 | b30bb3a2 | balrog | |
546 | b30bb3a2 | balrog | static CPUReadMemoryFunc *omap_mmc_readfn[] = {
|
547 | b30bb3a2 | balrog | omap_badwidth_read16, |
548 | b30bb3a2 | balrog | omap_mmc_read, |
549 | b30bb3a2 | balrog | omap_badwidth_read16, |
550 | b30bb3a2 | balrog | }; |
551 | b30bb3a2 | balrog | |
552 | b30bb3a2 | balrog | static CPUWriteMemoryFunc *omap_mmc_writefn[] = {
|
553 | b30bb3a2 | balrog | omap_badwidth_write16, |
554 | b30bb3a2 | balrog | omap_mmc_write, |
555 | b30bb3a2 | balrog | omap_badwidth_write16, |
556 | b30bb3a2 | balrog | }; |
557 | b30bb3a2 | balrog | |
558 | 827df9f3 | balrog | static void omap_mmc_cover_cb(void *opaque, int line, int level) |
559 | b30bb3a2 | balrog | { |
560 | 827df9f3 | balrog | struct omap_mmc_s *host = (struct omap_mmc_s *) opaque; |
561 | 827df9f3 | balrog | |
562 | 827df9f3 | balrog | if (!host->cdet_state && level) {
|
563 | 827df9f3 | balrog | host->status |= 0x0002;
|
564 | 827df9f3 | balrog | omap_mmc_interrupts_update(host); |
565 | 827df9f3 | balrog | if (host->cdet_wakeup)
|
566 | 827df9f3 | balrog | /* TODO: Assert wake-up */;
|
567 | 827df9f3 | balrog | } |
568 | 827df9f3 | balrog | |
569 | 827df9f3 | balrog | if (host->cdet_state != level) {
|
570 | 827df9f3 | balrog | qemu_set_irq(host->coverswitch, level); |
571 | 827df9f3 | balrog | host->cdet_state = level; |
572 | 827df9f3 | balrog | } |
573 | b30bb3a2 | balrog | } |
574 | b30bb3a2 | balrog | |
575 | b30bb3a2 | balrog | struct omap_mmc_s *omap_mmc_init(target_phys_addr_t base,
|
576 | 87ecb68b | pbrook | BlockDriverState *bd, |
577 | b30bb3a2 | balrog | qemu_irq irq, qemu_irq dma[], omap_clk clk) |
578 | b30bb3a2 | balrog | { |
579 | b30bb3a2 | balrog | int iomemtype;
|
580 | b30bb3a2 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) |
581 | b30bb3a2 | balrog | qemu_mallocz(sizeof(struct omap_mmc_s)); |
582 | b30bb3a2 | balrog | |
583 | b30bb3a2 | balrog | s->irq = irq; |
584 | b30bb3a2 | balrog | s->base = base; |
585 | b30bb3a2 | balrog | s->dma = dma; |
586 | b30bb3a2 | balrog | s->clk = clk; |
587 | 827df9f3 | balrog | s->lines = 1; /* TODO: needs to be settable per-board */ |
588 | 827df9f3 | balrog | s->rev = 1;
|
589 | 827df9f3 | balrog | |
590 | 827df9f3 | balrog | omap_mmc_reset(s); |
591 | b30bb3a2 | balrog | |
592 | b30bb3a2 | balrog | iomemtype = cpu_register_io_memory(0, omap_mmc_readfn,
|
593 | b30bb3a2 | balrog | omap_mmc_writefn, s); |
594 | b30bb3a2 | balrog | cpu_register_physical_memory(s->base, 0x800, iomemtype);
|
595 | b30bb3a2 | balrog | |
596 | b30bb3a2 | balrog | /* Instantiate the storage */
|
597 | 775616c3 | pbrook | s->card = sd_init(bd, 0);
|
598 | b30bb3a2 | balrog | |
599 | b30bb3a2 | balrog | return s;
|
600 | b30bb3a2 | balrog | } |
601 | b30bb3a2 | balrog | |
602 | 827df9f3 | balrog | struct omap_mmc_s *omap2_mmc_init(struct omap_target_agent_s *ta, |
603 | 827df9f3 | balrog | BlockDriverState *bd, qemu_irq irq, qemu_irq dma[], |
604 | 827df9f3 | balrog | omap_clk fclk, omap_clk iclk) |
605 | 827df9f3 | balrog | { |
606 | 827df9f3 | balrog | int iomemtype;
|
607 | 827df9f3 | balrog | struct omap_mmc_s *s = (struct omap_mmc_s *) |
608 | 827df9f3 | balrog | qemu_mallocz(sizeof(struct omap_mmc_s)); |
609 | 827df9f3 | balrog | |
610 | 827df9f3 | balrog | s->irq = irq; |
611 | 827df9f3 | balrog | s->dma = dma; |
612 | 827df9f3 | balrog | s->clk = fclk; |
613 | 827df9f3 | balrog | s->lines = 4;
|
614 | 827df9f3 | balrog | s->rev = 2;
|
615 | 827df9f3 | balrog | |
616 | 827df9f3 | balrog | omap_mmc_reset(s); |
617 | 827df9f3 | balrog | |
618 | c66fb5bc | balrog | iomemtype = l4_register_io_memory(0, omap_mmc_readfn,
|
619 | 827df9f3 | balrog | omap_mmc_writefn, s); |
620 | 827df9f3 | balrog | s->base = omap_l4_attach(ta, 0, iomemtype);
|
621 | 827df9f3 | balrog | |
622 | 827df9f3 | balrog | /* Instantiate the storage */
|
623 | 827df9f3 | balrog | s->card = sd_init(bd, 0);
|
624 | 827df9f3 | balrog | |
625 | 827df9f3 | balrog | s->cdet = qemu_allocate_irqs(omap_mmc_cover_cb, s, 1)[0]; |
626 | 827df9f3 | balrog | sd_set_cb(s->card, 0, s->cdet);
|
627 | 827df9f3 | balrog | |
628 | 827df9f3 | balrog | return s;
|
629 | 827df9f3 | balrog | } |
630 | 827df9f3 | balrog | |
631 | 8e129e07 | balrog | void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover) |
632 | 8e129e07 | balrog | { |
633 | 827df9f3 | balrog | if (s->cdet) {
|
634 | 827df9f3 | balrog | sd_set_cb(s->card, ro, s->cdet); |
635 | 827df9f3 | balrog | s->coverswitch = cover; |
636 | 827df9f3 | balrog | qemu_set_irq(cover, s->cdet_state); |
637 | 827df9f3 | balrog | } else
|
638 | 827df9f3 | balrog | sd_set_cb(s->card, ro, cover); |
639 | 827df9f3 | balrog | } |
640 | 827df9f3 | balrog | |
641 | 827df9f3 | balrog | void omap_mmc_enable(struct omap_mmc_s *s, int enable) |
642 | 827df9f3 | balrog | { |
643 | 827df9f3 | balrog | sd_enable(s->card, enable); |
644 | 8e129e07 | balrog | } |