Revision fd37d881 hw/piix_pci.c
b/hw/piix_pci.c | ||
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typedef PCIHostState I440FXState; |
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typedef struct PIIX3State { |
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PCIDevice dev; |
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} PIIX3State; |
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struct PCII440FXState { |
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PCIDevice dev; |
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target_phys_addr_t isa_page_descs[384 / 4]; |
... | ... | |
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/* PIIX3 PCI to ISA bridge */ |
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static PCIDevice *piix3_dev;
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static PIIX3State *piix3_dev;
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static void piix3_set_irq(void *opaque, int irq_num, int level) |
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{ |
... | ... | |
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/* now we change the pic irq level according to the piix irq mappings */ |
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/* XXX: optimize */ |
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pic_irq = piix3_dev->config[0x60 + irq_num]; |
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pic_irq = piix3_dev->dev.config[0x60 + irq_num];
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if (pic_irq < 16) { |
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/* The pic level is the logical OR of all the PCI irqs mapped |
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to it */ |
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pic_level = 0; |
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for (i = 0; i < 4; i++) { |
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if (pic_irq == piix3_dev->config[0x60 + i]) |
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if (pic_irq == piix3_dev->dev.config[0x60 + i])
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pic_level |= pci_irq_levels[i]; |
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} |
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qemu_set_irq(pic[pic_irq], pic_level); |
... | ... | |
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static void piix3_reset(void *opaque) |
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{ |
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PCIDevice *d = opaque;
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uint8_t *pci_conf = d->config; |
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PIIX3State *d = opaque;
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uint8_t *pci_conf = d->dev.config;
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pci_conf[0x04] = 0x07; // master, memory and I/O |
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pci_conf[0x05] = 0x00; |
... | ... | |
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return pci_device_load(d, f); |
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} |
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static int piix3_initfn(PCIDevice *d) |
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static int piix3_initfn(PCIDevice *dev)
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{ |
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PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
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uint8_t *pci_conf; |
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isa_bus_new(&d->qdev); |
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isa_bus_new(&d->dev.qdev);
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register_savevm("PIIX3", 0, 2, piix_save, piix_load, d); |
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pci_conf = d->config; |
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pci_conf = d->dev.config;
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pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL); |
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pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371SB_0); // 82371SB PIIX3 PCI-to-ISA bridge (Step A1) |
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_ISA); |
... | ... | |
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},{ |
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.qdev.name = "PIIX3", |
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.qdev.desc = "ISA bridge", |
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.qdev.size = sizeof(PCIDevice),
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.qdev.size = sizeof(PIIX3State),
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.qdev.no_user = 1, |
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.init = piix3_initfn, |
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},{ |
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