Revision fd56059f target-cris/translate.c
| b/target-cris/translate.c | ||
|---|---|---|
| 110 | 110 |
unsigned int mode; |
| 111 | 111 |
unsigned int postinc; |
| 112 | 112 |
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| 113 |
|
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struct |
|
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{
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int op; |
|
| 117 |
int size; |
|
| 118 |
unsigned int mask; |
|
| 119 |
} cc_state[3]; |
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int cc_i; |
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| 121 |
|
|
| 122 | 113 |
int update_cc; |
| 123 | 114 |
int cc_op; |
| 124 | 115 |
int cc_size; |
| ... | ... | |
| 183 | 174 |
gen_op_movl_T0_im(32); |
| 184 | 175 |
} |
| 185 | 176 |
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static void gen_movl_T0_p0(void) {
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gen_op_movl_T0_im(0); |
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} |
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|
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| 186 | 181 |
static void gen_ccs_read(void) {
|
| 187 | 182 |
gen_op_movl_T0_p13(); |
| 188 | 183 |
} |
| ... | ... | |
| 209 | 204 |
}; |
| 210 | 205 |
static GenOpFunc *gen_movl_T0_preg[16] = |
| 211 | 206 |
{
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gen_op_movl_T0_p0,
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gen_movl_T0_p0, |
|
| 213 | 208 |
gen_vr_read, |
| 214 | 209 |
gen_op_movl_T0_p2, gen_op_movl_T0_p3, |
| 215 | 210 |
gen_op_movl_T0_p4, gen_op_movl_T0_p5, |
| ... | ... | |
| 345 | 340 |
{
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| 346 | 341 |
uint32_t ovl; |
| 347 | 342 |
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/* Check if we need to evaluate the condition codes due to |
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CC overlaying. */ |
|
| 348 | 345 |
ovl = (dc->cc_mask ^ mask) & ~mask; |
| 349 | 346 |
if (ovl) {
|
| 350 | 347 |
/* TODO: optimize this case. It trigs all the time. */ |
| ... | ... | |
| 987 | 984 |
{
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| 988 | 985 |
dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); |
| 989 | 986 |
DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2)); |
| 990 |
cris_evaluate_flags(dc); |
|
| 991 | 987 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 992 | 988 |
gen_movl_T0_reg[dc->op2](); |
| 993 | 989 |
gen_op_movl_T1_im(dc->op1); |
| ... | ... | |
| 1333 | 1329 |
{
|
| 1334 | 1330 |
DIS(fprintf (logfile, "btst $r%u, $r%u\n", |
| 1335 | 1331 |
dc->op1, dc->op2)); |
| 1336 |
cris_evaluate_flags(dc); |
|
| 1337 | 1332 |
cris_cc_mask(dc, CC_MASK_NZ); |
| 1338 | 1333 |
dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0); |
| 1339 | 1334 |
crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4); |
| ... | ... | |
| 1518 | 1513 |
{
|
| 1519 | 1514 |
DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2)); |
| 1520 | 1515 |
cris_cc_mask(dc, 0); |
| 1521 |
gen_movl_T0_preg[dc->op2](); |
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gen_op_movl_T1_T0(); |
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/* Support register 0 is hardwired to zero. |
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Treat it specially. */ |
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if (dc->op2 == 0) |
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gen_op_movl_T1_im(0); |
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else {
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gen_movl_T0_preg[dc->op2](); |
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gen_op_movl_T1_T0(); |
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} |
|
| 1523 | 1524 |
crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]); |
| 1524 | 1525 |
return 2; |
| 1525 | 1526 |
} |
| ... | ... | |
| 1846 | 1847 |
|
| 1847 | 1848 |
memsize = preg_sizes[dc->op2]; |
| 1848 | 1849 |
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DIS(fprintf (logfile, "move.%d $p%u, [$r%u%s\n", |
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memsize, dc->op2, dc->op1, dc->postinc ? "+]" : "]")); |
|
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DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n", |
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memsize_char(memsize), |
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dc->op2, dc->op1, dc->postinc ? "+]" : "]")); |
|
| 1851 | 1853 |
|
| 1852 | 1854 |
cris_cc_mask(dc, 0); |
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/* prepare store. */ |
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gen_movl_T0_preg[dc->op2](); |
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gen_op_movl_T1_T0(); |
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/* prepare store. Address in T0, value in T1. */ |
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/* Support register 0 is hardwired to zero. |
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Treat it specially. */ |
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if (dc->op2 == 0) |
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gen_op_movl_T1_im(0); |
|
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else |
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{
|
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gen_movl_T0_preg[dc->op2](); |
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gen_op_movl_T1_T0(); |
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} |
|
| 1856 | 1865 |
gen_movl_T0_reg[dc->op1](); |
| 1857 | 1866 |
gen_store_T0_T1(dc, memsize); |
| 1858 | 1867 |
if (dc->postinc) |
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