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1 80cabfad bellard
/*
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 * QEMU PC System Emulator
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 *
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 * Copyright (c) 2003-2004 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "hw.h"
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#include "pc.h"
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#include "fdc.h"
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#include "pci.h"
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#include "block.h"
29 87ecb68b pbrook
#include "sysemu.h"
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#include "audio/audio.h"
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#include "net.h"
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#include "smbus.h"
33 87ecb68b pbrook
#include "boards.h"
34 376253ec aliguori
#include "monitor.h"
35 3cce6243 blueswir1
#include "fw_cfg.h"
36 16b29ae1 aliguori
#include "hpet_emul.h"
37 9dd986cc Richard W.M. Jones
#include "watchdog.h"
38 b6f6e3d3 aliguori
#include "smbios.h"
39 ec82026c Gerd Hoffmann
#include "ide.h"
40 ca20cf32 Blue Swirl
#include "loader.h"
41 ca20cf32 Blue Swirl
#include "elf.h"
42 80cabfad bellard
43 b41a2cd1 bellard
/* output Bochs bios info messages */
44 b41a2cd1 bellard
//#define DEBUG_BIOS
45 b41a2cd1 bellard
46 f16408df Alexander Graf
/* Show multiboot debug output */
47 f16408df Alexander Graf
//#define DEBUG_MULTIBOOT
48 f16408df Alexander Graf
49 80cabfad bellard
#define BIOS_FILENAME "bios.bin"
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#define VGABIOS_FILENAME "vgabios.bin"
51 de9258a8 bellard
#define VGABIOS_CIRRUS_FILENAME "vgabios-cirrus.bin"
52 80cabfad bellard
53 7fb4fdcf balrog
#define PC_MAX_BIOS_SIZE (4 * 1024 * 1024)
54 7fb4fdcf balrog
55 a80274c3 pbrook
/* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
56 a80274c3 pbrook
#define ACPI_DATA_SIZE       0x10000
57 3cce6243 blueswir1
#define BIOS_CFG_IOPORT 0x510
58 8a92ea2f aliguori
#define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
59 b6f6e3d3 aliguori
#define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
60 6b35e7bf Jes Sorensen
#define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
61 80cabfad bellard
62 e4bcb14c ths
#define MAX_IDE_BUS 2
63 e4bcb14c ths
64 c227f099 Anthony Liguori
static fdctrl_t *floppy_controller;
65 b0a21b53 bellard
static RTCState *rtc_state;
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static PITState *pit;
67 0a3bacf3 Juan Quintela
static PCII440FXState *i440fx_state;
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69 e28f9884 Glauber Costa
typedef struct rom_reset_data {
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    uint8_t *data;
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    target_phys_addr_t addr;
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    unsigned size;
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} RomResetData;
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static void option_rom_reset(void *_rrd)
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{
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    RomResetData *rrd = _rrd;
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    cpu_physical_memory_write_rom(rrd->addr, rrd->data, rrd->size);
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}
81 e28f9884 Glauber Costa
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static void option_rom_setup_reset(target_phys_addr_t addr, unsigned size)
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{
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    RomResetData *rrd = qemu_malloc(sizeof *rrd);
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    rrd->data = qemu_malloc(size);
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    cpu_physical_memory_read(addr, rrd->data, size);
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    rrd->addr = addr;
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    rrd->size = size;
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    qemu_register_reset(option_rom_reset, rrd);
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}
92 e28f9884 Glauber Costa
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typedef struct isa_irq_state {
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    qemu_irq *i8259;
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    qemu_irq *ioapic;
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} IsaIrqState;
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static void isa_irq_handler(void *opaque, int n, int level)
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{
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    IsaIrqState *isa = (IsaIrqState *)opaque;
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    if (n < 16) {
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        qemu_set_irq(isa->i8259[n], level);
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    }
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    if (isa->ioapic)
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        qemu_set_irq(isa->ioapic[n], level);
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};
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static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
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{
111 80cabfad bellard
}
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/* MSDOS compatibility mode FPU exception support */
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static qemu_irq ferr_irq;
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/* XXX: add IGNNE support */
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void cpu_set_ferr(CPUX86State *s)
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{
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    qemu_irq_raise(ferr_irq);
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}
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static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
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{
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    qemu_irq_lower(ferr_irq);
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}
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/* TSC handling */
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uint64_t cpu_get_tsc(CPUX86State *env)
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{
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    return cpu_get_ticks();
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}
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/* SMM support */
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void cpu_smm_update(CPUState *env)
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{
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    if (i440fx_state && env == first_cpu)
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        i440fx_set_smm(i440fx_state, (env->hflags >> HF_SMM_SHIFT) & 1);
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}
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/* IRQ handling */
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int cpu_get_pic_interrupt(CPUState *env)
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{
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    int intno;
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    intno = apic_get_interrupt(env);
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    if (intno >= 0) {
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        /* set irq request if a PIC irq is still pending */
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        /* XXX: improve that */
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        pic_update_irq(isa_pic);
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        return intno;
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    }
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    /* read the irq from the PIC */
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    if (!apic_accept_pic_intr(env))
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        return -1;
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    intno = pic_read_irq(isa_pic);
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    return intno;
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}
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static void pic_irq_request(void *opaque, int irq, int level)
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{
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    CPUState *env = first_cpu;
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    if (env->apic_state) {
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        while (env) {
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            if (apic_accept_pic_intr(env))
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                apic_deliver_pic_intr(env, level);
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            env = env->next_cpu;
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        }
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    } else {
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        if (level)
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            cpu_interrupt(env, CPU_INTERRUPT_HARD);
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        else
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            cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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    }
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}
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/* PC cmos mappings */
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#define REG_EQUIPMENT_BYTE          0x14
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static int cmos_get_fd_drive_type(int fd0)
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{
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    int val;
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    switch (fd0) {
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    case 0:
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        /* 1.44 Mb 3"5 drive */
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        val = 4;
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        break;
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    case 1:
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        /* 2.88 Mb 3"5 drive */
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        val = 5;
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        break;
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    case 2:
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        /* 1.2 Mb 5"5 drive */
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        val = 2;
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        break;
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    default:
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        val = 0;
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        break;
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    }
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    return val;
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}
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static void cmos_init_hd(int type_ofs, int info_ofs, BlockDriverState *hd)
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{
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    RTCState *s = rtc_state;
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    int cylinders, heads, sectors;
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    bdrv_get_geometry_hint(hd, &cylinders, &heads, &sectors);
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    rtc_set_memory(s, type_ofs, 47);
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    rtc_set_memory(s, info_ofs, cylinders);
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    rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 2, heads);
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    rtc_set_memory(s, info_ofs + 3, 0xff);
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    rtc_set_memory(s, info_ofs + 4, 0xff);
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    rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
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    rtc_set_memory(s, info_ofs + 6, cylinders);
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    rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
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    rtc_set_memory(s, info_ofs + 8, sectors);
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}
222 ba6c2377 bellard
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/* convert boot_device letter to something recognizable by the bios */
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static int boot_device2nibble(char boot_device)
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{
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    switch(boot_device) {
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    case 'a':
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    case 'b':
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        return 0x01; /* floppy boot */
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    case 'c':
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        return 0x02; /* hard drive boot */
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    case 'd':
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        return 0x03; /* CD-ROM boot */
234 6ac0e82d balrog
    case 'n':
235 6ac0e82d balrog
        return 0x04; /* Network boot */
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    }
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    return 0;
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}
239 6ac0e82d balrog
240 0ecdffbb aurel32
/* copy/pasted from cmos_init, should be made a general function
241 0ecdffbb aurel32
 and used there as well */
242 3b4366de blueswir1
static int pc_boot_set(void *opaque, const char *boot_device)
243 0ecdffbb aurel32
{
244 376253ec aliguori
    Monitor *mon = cur_mon;
245 0ecdffbb aurel32
#define PC_MAX_BOOT_DEVICES 3
246 3b4366de blueswir1
    RTCState *s = (RTCState *)opaque;
247 0ecdffbb aurel32
    int nbds, bds[3] = { 0, };
248 0ecdffbb aurel32
    int i;
249 0ecdffbb aurel32
250 0ecdffbb aurel32
    nbds = strlen(boot_device);
251 0ecdffbb aurel32
    if (nbds > PC_MAX_BOOT_DEVICES) {
252 376253ec aliguori
        monitor_printf(mon, "Too many boot devices for PC\n");
253 0ecdffbb aurel32
        return(1);
254 0ecdffbb aurel32
    }
255 0ecdffbb aurel32
    for (i = 0; i < nbds; i++) {
256 0ecdffbb aurel32
        bds[i] = boot_device2nibble(boot_device[i]);
257 0ecdffbb aurel32
        if (bds[i] == 0) {
258 376253ec aliguori
            monitor_printf(mon, "Invalid boot device for PC: '%c'\n",
259 376253ec aliguori
                           boot_device[i]);
260 0ecdffbb aurel32
            return(1);
261 0ecdffbb aurel32
        }
262 0ecdffbb aurel32
    }
263 0ecdffbb aurel32
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
264 0ecdffbb aurel32
    rtc_set_memory(s, 0x38, (bds[2] << 4));
265 0ecdffbb aurel32
    return(0);
266 0ecdffbb aurel32
}
267 0ecdffbb aurel32
268 ba6c2377 bellard
/* hd_table must contain 4 block drivers */
269 c227f099 Anthony Liguori
static void cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
270 f455e98c Gerd Hoffmann
                      const char *boot_device, DriveInfo **hd_table)
271 80cabfad bellard
{
272 b0a21b53 bellard
    RTCState *s = rtc_state;
273 28c5af54 j_mayer
    int nbds, bds[3] = { 0, };
274 80cabfad bellard
    int val;
275 b41a2cd1 bellard
    int fd0, fd1, nb;
276 ba6c2377 bellard
    int i;
277 b0a21b53 bellard
278 b0a21b53 bellard
    /* various important CMOS locations needed by PC/Bochs bios */
279 80cabfad bellard
280 80cabfad bellard
    /* memory size */
281 333190eb bellard
    val = 640; /* base memory in K */
282 333190eb bellard
    rtc_set_memory(s, 0x15, val);
283 333190eb bellard
    rtc_set_memory(s, 0x16, val >> 8);
284 333190eb bellard
285 80cabfad bellard
    val = (ram_size / 1024) - 1024;
286 80cabfad bellard
    if (val > 65535)
287 80cabfad bellard
        val = 65535;
288 b0a21b53 bellard
    rtc_set_memory(s, 0x17, val);
289 b0a21b53 bellard
    rtc_set_memory(s, 0x18, val >> 8);
290 b0a21b53 bellard
    rtc_set_memory(s, 0x30, val);
291 b0a21b53 bellard
    rtc_set_memory(s, 0x31, val >> 8);
292 80cabfad bellard
293 00f82b8a aurel32
    if (above_4g_mem_size) {
294 00f82b8a aurel32
        rtc_set_memory(s, 0x5b, (unsigned int)above_4g_mem_size >> 16);
295 00f82b8a aurel32
        rtc_set_memory(s, 0x5c, (unsigned int)above_4g_mem_size >> 24);
296 00f82b8a aurel32
        rtc_set_memory(s, 0x5d, (uint64_t)above_4g_mem_size >> 32);
297 00f82b8a aurel32
    }
298 00f82b8a aurel32
299 9da98861 bellard
    if (ram_size > (16 * 1024 * 1024))
300 9da98861 bellard
        val = (ram_size / 65536) - ((16 * 1024 * 1024) / 65536);
301 9da98861 bellard
    else
302 9da98861 bellard
        val = 0;
303 80cabfad bellard
    if (val > 65535)
304 80cabfad bellard
        val = 65535;
305 b0a21b53 bellard
    rtc_set_memory(s, 0x34, val);
306 b0a21b53 bellard
    rtc_set_memory(s, 0x35, val >> 8);
307 3b46e624 ths
308 298e01b6 aurel32
    /* set the number of CPU */
309 298e01b6 aurel32
    rtc_set_memory(s, 0x5f, smp_cpus - 1);
310 298e01b6 aurel32
311 6ac0e82d balrog
    /* set boot devices, and disable floppy signature check if requested */
312 28c5af54 j_mayer
#define PC_MAX_BOOT_DEVICES 3
313 28c5af54 j_mayer
    nbds = strlen(boot_device);
314 28c5af54 j_mayer
    if (nbds > PC_MAX_BOOT_DEVICES) {
315 28c5af54 j_mayer
        fprintf(stderr, "Too many boot devices for PC\n");
316 28c5af54 j_mayer
        exit(1);
317 28c5af54 j_mayer
    }
318 28c5af54 j_mayer
    for (i = 0; i < nbds; i++) {
319 28c5af54 j_mayer
        bds[i] = boot_device2nibble(boot_device[i]);
320 28c5af54 j_mayer
        if (bds[i] == 0) {
321 28c5af54 j_mayer
            fprintf(stderr, "Invalid boot device for PC: '%c'\n",
322 28c5af54 j_mayer
                    boot_device[i]);
323 28c5af54 j_mayer
            exit(1);
324 28c5af54 j_mayer
        }
325 28c5af54 j_mayer
    }
326 28c5af54 j_mayer
    rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
327 28c5af54 j_mayer
    rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ?  0x0 : 0x1));
328 80cabfad bellard
329 b41a2cd1 bellard
    /* floppy type */
330 b41a2cd1 bellard
331 baca51fa bellard
    fd0 = fdctrl_get_drive_type(floppy_controller, 0);
332 baca51fa bellard
    fd1 = fdctrl_get_drive_type(floppy_controller, 1);
333 80cabfad bellard
334 777428f2 bellard
    val = (cmos_get_fd_drive_type(fd0) << 4) | cmos_get_fd_drive_type(fd1);
335 b0a21b53 bellard
    rtc_set_memory(s, 0x10, val);
336 3b46e624 ths
337 b0a21b53 bellard
    val = 0;
338 b41a2cd1 bellard
    nb = 0;
339 80cabfad bellard
    if (fd0 < 3)
340 80cabfad bellard
        nb++;
341 80cabfad bellard
    if (fd1 < 3)
342 80cabfad bellard
        nb++;
343 80cabfad bellard
    switch (nb) {
344 80cabfad bellard
    case 0:
345 80cabfad bellard
        break;
346 80cabfad bellard
    case 1:
347 b0a21b53 bellard
        val |= 0x01; /* 1 drive, ready for boot */
348 80cabfad bellard
        break;
349 80cabfad bellard
    case 2:
350 b0a21b53 bellard
        val |= 0x41; /* 2 drives, ready for boot */
351 80cabfad bellard
        break;
352 80cabfad bellard
    }
353 b0a21b53 bellard
    val |= 0x02; /* FPU is there */
354 b0a21b53 bellard
    val |= 0x04; /* PS/2 mouse installed */
355 b0a21b53 bellard
    rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
356 b0a21b53 bellard
357 ba6c2377 bellard
    /* hard drives */
358 ba6c2377 bellard
359 ba6c2377 bellard
    rtc_set_memory(s, 0x12, (hd_table[0] ? 0xf0 : 0) | (hd_table[1] ? 0x0f : 0));
360 ba6c2377 bellard
    if (hd_table[0])
361 f455e98c Gerd Hoffmann
        cmos_init_hd(0x19, 0x1b, hd_table[0]->bdrv);
362 5fafdf24 ths
    if (hd_table[1])
363 f455e98c Gerd Hoffmann
        cmos_init_hd(0x1a, 0x24, hd_table[1]->bdrv);
364 ba6c2377 bellard
365 ba6c2377 bellard
    val = 0;
366 40b6ecc6 bellard
    for (i = 0; i < 4; i++) {
367 ba6c2377 bellard
        if (hd_table[i]) {
368 46d4767d bellard
            int cylinders, heads, sectors, translation;
369 46d4767d bellard
            /* NOTE: bdrv_get_geometry_hint() returns the physical
370 46d4767d bellard
                geometry.  It is always such that: 1 <= sects <= 63, 1
371 46d4767d bellard
                <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
372 46d4767d bellard
                geometry can be different if a translation is done. */
373 f455e98c Gerd Hoffmann
            translation = bdrv_get_translation_hint(hd_table[i]->bdrv);
374 46d4767d bellard
            if (translation == BIOS_ATA_TRANSLATION_AUTO) {
375 f455e98c Gerd Hoffmann
                bdrv_get_geometry_hint(hd_table[i]->bdrv, &cylinders, &heads, &sectors);
376 46d4767d bellard
                if (cylinders <= 1024 && heads <= 16 && sectors <= 63) {
377 46d4767d bellard
                    /* No translation. */
378 46d4767d bellard
                    translation = 0;
379 46d4767d bellard
                } else {
380 46d4767d bellard
                    /* LBA translation. */
381 46d4767d bellard
                    translation = 1;
382 46d4767d bellard
                }
383 40b6ecc6 bellard
            } else {
384 46d4767d bellard
                translation--;
385 ba6c2377 bellard
            }
386 ba6c2377 bellard
            val |= translation << (i * 2);
387 ba6c2377 bellard
        }
388 40b6ecc6 bellard
    }
389 ba6c2377 bellard
    rtc_set_memory(s, 0x39, val);
390 80cabfad bellard
}
391 80cabfad bellard
392 59b8ad81 bellard
void ioport_set_a20(int enable)
393 59b8ad81 bellard
{
394 59b8ad81 bellard
    /* XXX: send to all CPUs ? */
395 59b8ad81 bellard
    cpu_x86_set_a20(first_cpu, enable);
396 59b8ad81 bellard
}
397 59b8ad81 bellard
398 59b8ad81 bellard
int ioport_get_a20(void)
399 59b8ad81 bellard
{
400 59b8ad81 bellard
    return ((first_cpu->a20_mask >> 20) & 1);
401 59b8ad81 bellard
}
402 59b8ad81 bellard
403 e1a23744 bellard
static void ioport92_write(void *opaque, uint32_t addr, uint32_t val)
404 e1a23744 bellard
{
405 59b8ad81 bellard
    ioport_set_a20((val >> 1) & 1);
406 e1a23744 bellard
    /* XXX: bit 0 is fast reset */
407 e1a23744 bellard
}
408 e1a23744 bellard
409 e1a23744 bellard
static uint32_t ioport92_read(void *opaque, uint32_t addr)
410 e1a23744 bellard
{
411 59b8ad81 bellard
    return ioport_get_a20() << 1;
412 e1a23744 bellard
}
413 e1a23744 bellard
414 80cabfad bellard
/***********************************************************/
415 80cabfad bellard
/* Bochs BIOS debug ports */
416 80cabfad bellard
417 9596ebb7 pbrook
static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
418 80cabfad bellard
{
419 a2f659ee bellard
    static const char shutdown_str[8] = "Shutdown";
420 a2f659ee bellard
    static int shutdown_index = 0;
421 3b46e624 ths
422 80cabfad bellard
    switch(addr) {
423 80cabfad bellard
        /* Bochs BIOS messages */
424 80cabfad bellard
    case 0x400:
425 80cabfad bellard
    case 0x401:
426 80cabfad bellard
        fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
427 80cabfad bellard
        exit(1);
428 80cabfad bellard
    case 0x402:
429 80cabfad bellard
    case 0x403:
430 80cabfad bellard
#ifdef DEBUG_BIOS
431 80cabfad bellard
        fprintf(stderr, "%c", val);
432 80cabfad bellard
#endif
433 80cabfad bellard
        break;
434 a2f659ee bellard
    case 0x8900:
435 a2f659ee bellard
        /* same as Bochs power off */
436 a2f659ee bellard
        if (val == shutdown_str[shutdown_index]) {
437 a2f659ee bellard
            shutdown_index++;
438 a2f659ee bellard
            if (shutdown_index == 8) {
439 a2f659ee bellard
                shutdown_index = 0;
440 a2f659ee bellard
                qemu_system_shutdown_request();
441 a2f659ee bellard
            }
442 a2f659ee bellard
        } else {
443 a2f659ee bellard
            shutdown_index = 0;
444 a2f659ee bellard
        }
445 a2f659ee bellard
        break;
446 80cabfad bellard
447 80cabfad bellard
        /* LGPL'ed VGA BIOS messages */
448 80cabfad bellard
    case 0x501:
449 80cabfad bellard
    case 0x502:
450 80cabfad bellard
        fprintf(stderr, "VGA BIOS panic, line %d\n", val);
451 80cabfad bellard
        exit(1);
452 80cabfad bellard
    case 0x500:
453 80cabfad bellard
    case 0x503:
454 80cabfad bellard
#ifdef DEBUG_BIOS
455 80cabfad bellard
        fprintf(stderr, "%c", val);
456 80cabfad bellard
#endif
457 80cabfad bellard
        break;
458 80cabfad bellard
    }
459 80cabfad bellard
}
460 80cabfad bellard
461 bf483392 Alexander Graf
static void *bochs_bios_init(void)
462 80cabfad bellard
{
463 3cce6243 blueswir1
    void *fw_cfg;
464 b6f6e3d3 aliguori
    uint8_t *smbios_table;
465 b6f6e3d3 aliguori
    size_t smbios_len;
466 11c2fd3e aliguori
    uint64_t *numa_fw_cfg;
467 11c2fd3e aliguori
    int i, j;
468 3cce6243 blueswir1
469 b41a2cd1 bellard
    register_ioport_write(0x400, 1, 2, bochs_bios_write, NULL);
470 b41a2cd1 bellard
    register_ioport_write(0x401, 1, 2, bochs_bios_write, NULL);
471 b41a2cd1 bellard
    register_ioport_write(0x402, 1, 1, bochs_bios_write, NULL);
472 b41a2cd1 bellard
    register_ioport_write(0x403, 1, 1, bochs_bios_write, NULL);
473 a2f659ee bellard
    register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
474 b41a2cd1 bellard
475 b41a2cd1 bellard
    register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
476 b41a2cd1 bellard
    register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
477 b41a2cd1 bellard
    register_ioport_write(0x500, 1, 1, bochs_bios_write, NULL);
478 b41a2cd1 bellard
    register_ioport_write(0x503, 1, 1, bochs_bios_write, NULL);
479 3cce6243 blueswir1
480 3cce6243 blueswir1
    fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
481 bf483392 Alexander Graf
482 3cce6243 blueswir1
    fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
483 905fdcb5 blueswir1
    fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
484 80deece2 blueswir1
    fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
485 80deece2 blueswir1
                     acpi_tables_len);
486 6b35e7bf Jes Sorensen
    fw_cfg_add_bytes(fw_cfg, FW_CFG_IRQ0_OVERRIDE, &irq0override, 1);
487 b6f6e3d3 aliguori
488 b6f6e3d3 aliguori
    smbios_table = smbios_get_table(&smbios_len);
489 b6f6e3d3 aliguori
    if (smbios_table)
490 b6f6e3d3 aliguori
        fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
491 b6f6e3d3 aliguori
                         smbios_table, smbios_len);
492 11c2fd3e aliguori
493 11c2fd3e aliguori
    /* allocate memory for the NUMA channel: one (64bit) word for the number
494 11c2fd3e aliguori
     * of nodes, one word for each VCPU->node and one word for each node to
495 11c2fd3e aliguori
     * hold the amount of memory.
496 11c2fd3e aliguori
     */
497 11c2fd3e aliguori
    numa_fw_cfg = qemu_mallocz((1 + smp_cpus + nb_numa_nodes) * 8);
498 11c2fd3e aliguori
    numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
499 11c2fd3e aliguori
    for (i = 0; i < smp_cpus; i++) {
500 11c2fd3e aliguori
        for (j = 0; j < nb_numa_nodes; j++) {
501 11c2fd3e aliguori
            if (node_cpumask[j] & (1 << i)) {
502 11c2fd3e aliguori
                numa_fw_cfg[i + 1] = cpu_to_le64(j);
503 11c2fd3e aliguori
                break;
504 11c2fd3e aliguori
            }
505 11c2fd3e aliguori
        }
506 11c2fd3e aliguori
    }
507 11c2fd3e aliguori
    for (i = 0; i < nb_numa_nodes; i++) {
508 11c2fd3e aliguori
        numa_fw_cfg[smp_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
509 11c2fd3e aliguori
    }
510 11c2fd3e aliguori
    fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
511 11c2fd3e aliguori
                     (1 + smp_cpus + nb_numa_nodes) * 8);
512 bf483392 Alexander Graf
513 bf483392 Alexander Graf
    return fw_cfg;
514 80cabfad bellard
}
515 80cabfad bellard
516 642a4f96 ths
/* Generate an initial boot sector which sets state and jump to
517 642a4f96 ths
   a specified vector */
518 c227f099 Anthony Liguori
static void generate_bootsect(target_phys_addr_t option_rom,
519 4fc9af53 aliguori
                              uint32_t gpr[8], uint16_t segs[6], uint16_t ip)
520 642a4f96 ths
{
521 4fc9af53 aliguori
    uint8_t rom[512], *p, *reloc;
522 4fc9af53 aliguori
    uint8_t sum;
523 642a4f96 ths
    int i;
524 642a4f96 ths
525 4fc9af53 aliguori
    memset(rom, 0, sizeof(rom));
526 4fc9af53 aliguori
527 4fc9af53 aliguori
    p = rom;
528 4fc9af53 aliguori
    /* Make sure we have an option rom signature */
529 4fc9af53 aliguori
    *p++ = 0x55;
530 4fc9af53 aliguori
    *p++ = 0xaa;
531 642a4f96 ths
532 4fc9af53 aliguori
    /* ROM size in sectors*/
533 4fc9af53 aliguori
    *p++ = 1;
534 642a4f96 ths
535 4fc9af53 aliguori
    /* Hook int19 */
536 642a4f96 ths
537 4fc9af53 aliguori
    *p++ = 0x50;                /* push ax */
538 4fc9af53 aliguori
    *p++ = 0x1e;                /* push ds */
539 4fc9af53 aliguori
    *p++ = 0x31; *p++ = 0xc0;        /* xor ax, ax */
540 4fc9af53 aliguori
    *p++ = 0x8e; *p++ = 0xd8;        /* mov ax, ds */
541 642a4f96 ths
542 4fc9af53 aliguori
    *p++ = 0xc7; *p++ = 0x06;   /* movvw _start,0x64 */
543 4fc9af53 aliguori
    *p++ = 0x64; *p++ = 0x00;
544 4fc9af53 aliguori
    reloc = p;
545 4fc9af53 aliguori
    *p++ = 0x00; *p++ = 0x00;
546 4fc9af53 aliguori
547 4fc9af53 aliguori
    *p++ = 0x8c; *p++ = 0x0e;   /* mov cs,0x66 */
548 4fc9af53 aliguori
    *p++ = 0x66; *p++ = 0x00;
549 4fc9af53 aliguori
550 4fc9af53 aliguori
    *p++ = 0x1f;                /* pop ds */
551 4fc9af53 aliguori
    *p++ = 0x58;                /* pop ax */
552 4fc9af53 aliguori
    *p++ = 0xcb;                /* lret */
553 82663ee2 Blue Swirl
554 642a4f96 ths
    /* Actual code */
555 4fc9af53 aliguori
    *reloc = (p - rom);
556 4fc9af53 aliguori
557 642a4f96 ths
    *p++ = 0xfa;                /* CLI */
558 642a4f96 ths
    *p++ = 0xfc;                /* CLD */
559 642a4f96 ths
560 642a4f96 ths
    for (i = 0; i < 6; i++) {
561 642a4f96 ths
        if (i == 1)                /* Skip CS */
562 642a4f96 ths
            continue;
563 642a4f96 ths
564 642a4f96 ths
        *p++ = 0xb8;                /* MOV AX,imm16 */
565 642a4f96 ths
        *p++ = segs[i];
566 642a4f96 ths
        *p++ = segs[i] >> 8;
567 642a4f96 ths
        *p++ = 0x8e;                /* MOV <seg>,AX */
568 642a4f96 ths
        *p++ = 0xc0 + (i << 3);
569 642a4f96 ths
    }
570 642a4f96 ths
571 642a4f96 ths
    for (i = 0; i < 8; i++) {
572 642a4f96 ths
        *p++ = 0x66;                /* 32-bit operand size */
573 642a4f96 ths
        *p++ = 0xb8 + i;        /* MOV <reg>,imm32 */
574 642a4f96 ths
        *p++ = gpr[i];
575 642a4f96 ths
        *p++ = gpr[i] >> 8;
576 642a4f96 ths
        *p++ = gpr[i] >> 16;
577 642a4f96 ths
        *p++ = gpr[i] >> 24;
578 642a4f96 ths
    }
579 642a4f96 ths
580 642a4f96 ths
    *p++ = 0xea;                /* JMP FAR */
581 642a4f96 ths
    *p++ = ip;                        /* IP */
582 642a4f96 ths
    *p++ = ip >> 8;
583 642a4f96 ths
    *p++ = segs[1];                /* CS */
584 642a4f96 ths
    *p++ = segs[1] >> 8;
585 642a4f96 ths
586 4fc9af53 aliguori
    /* sign rom */
587 4fc9af53 aliguori
    sum = 0;
588 4fc9af53 aliguori
    for (i = 0; i < (sizeof(rom) - 1); i++)
589 4fc9af53 aliguori
        sum += rom[i];
590 4fc9af53 aliguori
    rom[sizeof(rom) - 1] = -sum;
591 4fc9af53 aliguori
592 7ffa4767 pbrook
    cpu_physical_memory_write_rom(option_rom, rom, sizeof(rom));
593 d6ecb036 Glauber Costa
    option_rom_setup_reset(option_rom, sizeof (rom));
594 642a4f96 ths
}
595 80cabfad bellard
596 642a4f96 ths
static long get_file_size(FILE *f)
597 642a4f96 ths
{
598 642a4f96 ths
    long where, size;
599 642a4f96 ths
600 642a4f96 ths
    /* XXX: on Unix systems, using fstat() probably makes more sense */
601 642a4f96 ths
602 642a4f96 ths
    where = ftell(f);
603 642a4f96 ths
    fseek(f, 0, SEEK_END);
604 642a4f96 ths
    size = ftell(f);
605 642a4f96 ths
    fseek(f, where, SEEK_SET);
606 642a4f96 ths
607 642a4f96 ths
    return size;
608 642a4f96 ths
}
609 642a4f96 ths
610 f16408df Alexander Graf
#define MULTIBOOT_STRUCT_ADDR 0x9000
611 f16408df Alexander Graf
612 f16408df Alexander Graf
#if MULTIBOOT_STRUCT_ADDR > 0xf0000
613 f16408df Alexander Graf
#error multiboot struct needs to fit in 16 bit real mode
614 f16408df Alexander Graf
#endif
615 f16408df Alexander Graf
616 f16408df Alexander Graf
static int load_multiboot(void *fw_cfg,
617 f16408df Alexander Graf
                          FILE *f,
618 f16408df Alexander Graf
                          const char *kernel_filename,
619 f16408df Alexander Graf
                          const char *initrd_filename,
620 f16408df Alexander Graf
                          const char *kernel_cmdline,
621 f16408df Alexander Graf
                          uint8_t *header)
622 f16408df Alexander Graf
{
623 f16408df Alexander Graf
    int i, t, is_multiboot = 0;
624 f16408df Alexander Graf
    uint32_t flags = 0;
625 f16408df Alexander Graf
    uint32_t mh_entry_addr;
626 f16408df Alexander Graf
    uint32_t mh_load_addr;
627 f16408df Alexander Graf
    uint32_t mb_kernel_size;
628 f16408df Alexander Graf
    uint32_t mmap_addr = MULTIBOOT_STRUCT_ADDR;
629 f16408df Alexander Graf
    uint32_t mb_bootinfo = MULTIBOOT_STRUCT_ADDR + 0x500;
630 f16408df Alexander Graf
    uint32_t mb_cmdline = mb_bootinfo + 0x200;
631 f16408df Alexander Graf
    uint32_t mb_mod_end;
632 f16408df Alexander Graf
633 f16408df Alexander Graf
    /* Ok, let's see if it is a multiboot image.
634 f16408df Alexander Graf
       The header is 12x32bit long, so the latest entry may be 8192 - 48. */
635 f16408df Alexander Graf
    for (i = 0; i < (8192 - 48); i += 4) {
636 f16408df Alexander Graf
        if (ldl_p(header+i) == 0x1BADB002) {
637 f16408df Alexander Graf
            uint32_t checksum = ldl_p(header+i+8);
638 f16408df Alexander Graf
            flags = ldl_p(header+i+4);
639 f16408df Alexander Graf
            checksum += flags;
640 f16408df Alexander Graf
            checksum += (uint32_t)0x1BADB002;
641 f16408df Alexander Graf
            if (!checksum) {
642 f16408df Alexander Graf
                is_multiboot = 1;
643 f16408df Alexander Graf
                break;
644 f16408df Alexander Graf
            }
645 f16408df Alexander Graf
        }
646 f16408df Alexander Graf
    }
647 f16408df Alexander Graf
648 f16408df Alexander Graf
    if (!is_multiboot)
649 f16408df Alexander Graf
        return 0; /* no multiboot */
650 f16408df Alexander Graf
651 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
652 f16408df Alexander Graf
    fprintf(stderr, "qemu: I believe we found a multiboot image!\n");
653 f16408df Alexander Graf
#endif
654 f16408df Alexander Graf
655 f16408df Alexander Graf
    if (flags & 0x00000004) { /* MULTIBOOT_HEADER_HAS_VBE */
656 f16408df Alexander Graf
        fprintf(stderr, "qemu: multiboot knows VBE. we don't.\n");
657 f16408df Alexander Graf
    }
658 f16408df Alexander Graf
    if (!(flags & 0x00010000)) { /* MULTIBOOT_HEADER_HAS_ADDR */
659 f16408df Alexander Graf
        uint64_t elf_entry;
660 f16408df Alexander Graf
        int kernel_size;
661 f16408df Alexander Graf
        fclose(f);
662 ca20cf32 Blue Swirl
        kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL,
663 ca20cf32 Blue Swirl
                               0, ELF_MACHINE, 0);
664 f16408df Alexander Graf
        if (kernel_size < 0) {
665 f16408df Alexander Graf
            fprintf(stderr, "Error while loading elf kernel\n");
666 f16408df Alexander Graf
            exit(1);
667 f16408df Alexander Graf
        }
668 f16408df Alexander Graf
        mh_load_addr = mh_entry_addr = elf_entry;
669 f16408df Alexander Graf
        mb_kernel_size = kernel_size;
670 f16408df Alexander Graf
671 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
672 f16408df Alexander Graf
        fprintf(stderr, "qemu: loading multiboot-elf kernel (%#x bytes) with entry %#zx\n",
673 f16408df Alexander Graf
                mb_kernel_size, (size_t)mh_entry_addr);
674 f16408df Alexander Graf
#endif
675 f16408df Alexander Graf
    } else {
676 f16408df Alexander Graf
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_ADDR. */
677 f16408df Alexander Graf
        uint32_t mh_header_addr = ldl_p(header+i+12);
678 f16408df Alexander Graf
        mh_load_addr = ldl_p(header+i+16);
679 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
680 f16408df Alexander Graf
        uint32_t mh_load_end_addr = ldl_p(header+i+20);
681 f16408df Alexander Graf
        uint32_t mh_bss_end_addr = ldl_p(header+i+24);
682 f16408df Alexander Graf
#endif
683 f16408df Alexander Graf
        uint32_t mb_kernel_text_offset = i - (mh_header_addr - mh_load_addr);
684 f16408df Alexander Graf
685 f16408df Alexander Graf
        mh_entry_addr = ldl_p(header+i+28);
686 f16408df Alexander Graf
        mb_kernel_size = get_file_size(f) - mb_kernel_text_offset;
687 f16408df Alexander Graf
688 f16408df Alexander Graf
        /* Valid if mh_flags sets MULTIBOOT_HEADER_HAS_VBE.
689 f16408df Alexander Graf
        uint32_t mh_mode_type = ldl_p(header+i+32);
690 f16408df Alexander Graf
        uint32_t mh_width = ldl_p(header+i+36);
691 f16408df Alexander Graf
        uint32_t mh_height = ldl_p(header+i+40);
692 f16408df Alexander Graf
        uint32_t mh_depth = ldl_p(header+i+44); */
693 f16408df Alexander Graf
694 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
695 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_header_addr = %#x\n", mh_header_addr);
696 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_load_addr = %#x\n", mh_load_addr);
697 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_load_end_addr = %#x\n", mh_load_end_addr);
698 f16408df Alexander Graf
        fprintf(stderr, "multiboot: mh_bss_end_addr = %#x\n", mh_bss_end_addr);
699 f16408df Alexander Graf
#endif
700 f16408df Alexander Graf
701 f16408df Alexander Graf
        fseek(f, mb_kernel_text_offset, SEEK_SET);
702 f16408df Alexander Graf
703 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
704 f16408df Alexander Graf
        fprintf(stderr, "qemu: loading multiboot kernel (%#x bytes) at %#x\n",
705 f16408df Alexander Graf
                mb_kernel_size, mh_load_addr);
706 f16408df Alexander Graf
#endif
707 f16408df Alexander Graf
708 f16408df Alexander Graf
        if (!fread_targphys_ok(mh_load_addr, mb_kernel_size, f)) {
709 f16408df Alexander Graf
            fprintf(stderr, "qemu: read error on multiboot kernel '%s' (%#x)\n",
710 f16408df Alexander Graf
                    kernel_filename, mb_kernel_size);
711 f16408df Alexander Graf
            exit(1);
712 f16408df Alexander Graf
        }
713 f16408df Alexander Graf
        fclose(f);
714 f16408df Alexander Graf
    }
715 f16408df Alexander Graf
716 f16408df Alexander Graf
    /* blob size is only the kernel for now */
717 f16408df Alexander Graf
    mb_mod_end = mh_load_addr + mb_kernel_size;
718 f16408df Alexander Graf
719 f16408df Alexander Graf
    /* load modules */
720 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 20, 0x0); /* mods_count */
721 f16408df Alexander Graf
    if (initrd_filename) {
722 f16408df Alexander Graf
        uint32_t mb_mod_info = mb_bootinfo + 0x100;
723 f16408df Alexander Graf
        uint32_t mb_mod_cmdline = mb_bootinfo + 0x300;
724 f16408df Alexander Graf
        uint32_t mb_mod_start = mh_load_addr;
725 f16408df Alexander Graf
        uint32_t mb_mod_length = mb_kernel_size;
726 f16408df Alexander Graf
        char *next_initrd;
727 f16408df Alexander Graf
        char *next_space;
728 f16408df Alexander Graf
        int mb_mod_count = 0;
729 f16408df Alexander Graf
730 f16408df Alexander Graf
        do {
731 f16408df Alexander Graf
            next_initrd = strchr(initrd_filename, ',');
732 f16408df Alexander Graf
            if (next_initrd)
733 f16408df Alexander Graf
                *next_initrd = '\0';
734 f16408df Alexander Graf
            /* if a space comes after the module filename, treat everything
735 f16408df Alexander Graf
               after that as parameters */
736 f16408df Alexander Graf
            cpu_physical_memory_write(mb_mod_cmdline, (uint8_t*)initrd_filename,
737 f16408df Alexander Graf
                                      strlen(initrd_filename) + 1);
738 f16408df Alexander Graf
            stl_phys(mb_mod_info + 8, mb_mod_cmdline); /* string */
739 f16408df Alexander Graf
            mb_mod_cmdline += strlen(initrd_filename) + 1;
740 f16408df Alexander Graf
            if ((next_space = strchr(initrd_filename, ' ')))
741 f16408df Alexander Graf
                *next_space = '\0';
742 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
743 82663ee2 Blue Swirl
            printf("multiboot loading module: %s\n", initrd_filename);
744 f16408df Alexander Graf
#endif
745 f16408df Alexander Graf
            f = fopen(initrd_filename, "rb");
746 f16408df Alexander Graf
            if (f) {
747 f16408df Alexander Graf
                mb_mod_start = (mb_mod_start + mb_mod_length + (TARGET_PAGE_SIZE - 1))
748 f16408df Alexander Graf
                             & (TARGET_PAGE_MASK);
749 f16408df Alexander Graf
                mb_mod_length = get_file_size(f);
750 f16408df Alexander Graf
                mb_mod_end = mb_mod_start + mb_mod_length;
751 f16408df Alexander Graf
752 f16408df Alexander Graf
                if (!fread_targphys_ok(mb_mod_start, mb_mod_length, f)) {
753 f16408df Alexander Graf
                    fprintf(stderr, "qemu: read error on multiboot module '%s' (%#x)\n",
754 f16408df Alexander Graf
                            initrd_filename, mb_mod_length);
755 f16408df Alexander Graf
                    exit(1);
756 f16408df Alexander Graf
                }
757 f16408df Alexander Graf
758 f16408df Alexander Graf
                mb_mod_count++;
759 f16408df Alexander Graf
                stl_phys(mb_mod_info + 0, mb_mod_start);
760 f16408df Alexander Graf
                stl_phys(mb_mod_info + 4, mb_mod_start + mb_mod_length);
761 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
762 f16408df Alexander Graf
                printf("mod_start: %#x\nmod_end:   %#x\n", mb_mod_start,
763 f16408df Alexander Graf
                       mb_mod_start + mb_mod_length);
764 f16408df Alexander Graf
#endif
765 f16408df Alexander Graf
                stl_phys(mb_mod_info + 12, 0x0); /* reserved */
766 f16408df Alexander Graf
            }
767 f16408df Alexander Graf
            initrd_filename = next_initrd+1;
768 f16408df Alexander Graf
            mb_mod_info += 16;
769 f16408df Alexander Graf
        } while (next_initrd);
770 f16408df Alexander Graf
        stl_phys(mb_bootinfo + 20, mb_mod_count); /* mods_count */
771 f16408df Alexander Graf
        stl_phys(mb_bootinfo + 24, mb_bootinfo + 0x100); /* mods_addr */
772 f16408df Alexander Graf
    }
773 f16408df Alexander Graf
774 f16408df Alexander Graf
    /* Make sure we're getting kernel + modules back after reset */
775 f16408df Alexander Graf
    option_rom_setup_reset(mh_load_addr, mb_mod_end - mh_load_addr);
776 f16408df Alexander Graf
777 f16408df Alexander Graf
    /* Commandline support */
778 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 16, mb_cmdline);
779 f16408df Alexander Graf
    t = strlen(kernel_filename);
780 f16408df Alexander Graf
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_filename, t);
781 f16408df Alexander Graf
    mb_cmdline += t;
782 f16408df Alexander Graf
    stb_phys(mb_cmdline++, ' ');
783 f16408df Alexander Graf
    t = strlen(kernel_cmdline) + 1;
784 f16408df Alexander Graf
    cpu_physical_memory_write(mb_cmdline, (uint8_t*)kernel_cmdline, t);
785 f16408df Alexander Graf
786 f16408df Alexander Graf
    /* the kernel is where we want it to be now */
787 f16408df Alexander Graf
788 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_MEMORY (1 << 0)
789 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_BOOT_DEVICE (1 << 1)
790 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_CMDLINE (1 << 2)
791 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_MODULES (1 << 3)
792 f16408df Alexander Graf
#define MULTIBOOT_FLAGS_MMAP (1 << 6)
793 f16408df Alexander Graf
    stl_phys(mb_bootinfo, MULTIBOOT_FLAGS_MEMORY
794 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_BOOT_DEVICE
795 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_CMDLINE
796 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_MODULES
797 f16408df Alexander Graf
                        | MULTIBOOT_FLAGS_MMAP);
798 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 4, 640); /* mem_lower */
799 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 8, ram_size / 1024); /* mem_upper */
800 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 12, 0x8001ffff); /* XXX: use the -boot switch? */
801 f16408df Alexander Graf
    stl_phys(mb_bootinfo + 48, mmap_addr); /* mmap_addr */
802 f16408df Alexander Graf
803 f16408df Alexander Graf
#ifdef DEBUG_MULTIBOOT
804 f16408df Alexander Graf
    fprintf(stderr, "multiboot: mh_entry_addr = %#x\n", mh_entry_addr);
805 f16408df Alexander Graf
#endif
806 f16408df Alexander Graf
807 f16408df Alexander Graf
    /* Pass variables to option rom */
808 f16408df Alexander Graf
    fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, mh_entry_addr);
809 f16408df Alexander Graf
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, mb_bootinfo);
810 f16408df Alexander Graf
    fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, mmap_addr);
811 f16408df Alexander Graf
812 f16408df Alexander Graf
    /* Make sure we're getting the config space back after reset */
813 f16408df Alexander Graf
    option_rom_setup_reset(mb_bootinfo, 0x500);
814 f16408df Alexander Graf
815 f16408df Alexander Graf
    option_rom[nb_option_roms] = "multiboot.bin";
816 f16408df Alexander Graf
    nb_option_roms++;
817 f16408df Alexander Graf
818 f16408df Alexander Graf
    return 1; /* yes, we are multiboot */
819 f16408df Alexander Graf
}
820 f16408df Alexander Graf
821 f16408df Alexander Graf
static void load_linux(void *fw_cfg,
822 c227f099 Anthony Liguori
                       target_phys_addr_t option_rom,
823 4fc9af53 aliguori
                       const char *kernel_filename,
824 642a4f96 ths
                       const char *initrd_filename,
825 e6ade764 Glauber Costa
                       const char *kernel_cmdline,
826 c227f099 Anthony Liguori
               target_phys_addr_t max_ram_size)
827 642a4f96 ths
{
828 642a4f96 ths
    uint16_t protocol;
829 642a4f96 ths
    uint32_t gpr[8];
830 642a4f96 ths
    uint16_t seg[6];
831 642a4f96 ths
    uint16_t real_seg;
832 5cea8590 Paul Brook
    int setup_size, kernel_size, initrd_size = 0, cmdline_size;
833 642a4f96 ths
    uint32_t initrd_max;
834 f16408df Alexander Graf
    uint8_t header[8192];
835 c227f099 Anthony Liguori
    target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
836 642a4f96 ths
    FILE *f, *fi;
837 bf4e5d92 Pascal Terjan
    char *vmode;
838 642a4f96 ths
839 642a4f96 ths
    /* Align to 16 bytes as a paranoia measure */
840 642a4f96 ths
    cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
841 642a4f96 ths
842 642a4f96 ths
    /* load the kernel header */
843 642a4f96 ths
    f = fopen(kernel_filename, "rb");
844 642a4f96 ths
    if (!f || !(kernel_size = get_file_size(f)) ||
845 f16408df Alexander Graf
        fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
846 f16408df Alexander Graf
        MIN(ARRAY_SIZE(header), kernel_size)) {
847 642a4f96 ths
        fprintf(stderr, "qemu: could not load kernel '%s'\n",
848 642a4f96 ths
                kernel_filename);
849 642a4f96 ths
        exit(1);
850 642a4f96 ths
    }
851 642a4f96 ths
852 642a4f96 ths
    /* kernel protocol version */
853 bc4edd79 bellard
#if 0
854 642a4f96 ths
    fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
855 bc4edd79 bellard
#endif
856 642a4f96 ths
    if (ldl_p(header+0x202) == 0x53726448)
857 642a4f96 ths
        protocol = lduw_p(header+0x206);
858 f16408df Alexander Graf
    else {
859 f16408df Alexander Graf
        /* This looks like a multiboot kernel. If it is, let's stop
860 f16408df Alexander Graf
           treating it like a Linux kernel. */
861 f16408df Alexander Graf
        if (load_multiboot(fw_cfg, f, kernel_filename,
862 f16408df Alexander Graf
                           initrd_filename, kernel_cmdline, header))
863 82663ee2 Blue Swirl
            return;
864 642a4f96 ths
        protocol = 0;
865 f16408df Alexander Graf
    }
866 642a4f96 ths
867 642a4f96 ths
    if (protocol < 0x200 || !(header[0x211] & 0x01)) {
868 642a4f96 ths
        /* Low kernel */
869 a37af289 blueswir1
        real_addr    = 0x90000;
870 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
871 a37af289 blueswir1
        prot_addr    = 0x10000;
872 642a4f96 ths
    } else if (protocol < 0x202) {
873 642a4f96 ths
        /* High but ancient kernel */
874 a37af289 blueswir1
        real_addr    = 0x90000;
875 a37af289 blueswir1
        cmdline_addr = 0x9a000 - cmdline_size;
876 a37af289 blueswir1
        prot_addr    = 0x100000;
877 642a4f96 ths
    } else {
878 642a4f96 ths
        /* High and recent kernel */
879 a37af289 blueswir1
        real_addr    = 0x10000;
880 a37af289 blueswir1
        cmdline_addr = 0x20000;
881 a37af289 blueswir1
        prot_addr    = 0x100000;
882 642a4f96 ths
    }
883 642a4f96 ths
884 bc4edd79 bellard
#if 0
885 642a4f96 ths
    fprintf(stderr,
886 526ccb7a balrog
            "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
887 526ccb7a balrog
            "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
888 526ccb7a balrog
            "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
889 a37af289 blueswir1
            real_addr,
890 a37af289 blueswir1
            cmdline_addr,
891 a37af289 blueswir1
            prot_addr);
892 bc4edd79 bellard
#endif
893 642a4f96 ths
894 642a4f96 ths
    /* highest address for loading the initrd */
895 642a4f96 ths
    if (protocol >= 0x203)
896 642a4f96 ths
        initrd_max = ldl_p(header+0x22c);
897 642a4f96 ths
    else
898 642a4f96 ths
        initrd_max = 0x37ffffff;
899 642a4f96 ths
900 e6ade764 Glauber Costa
    if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
901 e6ade764 Glauber Costa
            initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
902 642a4f96 ths
903 642a4f96 ths
    /* kernel command line */
904 a37af289 blueswir1
    pstrcpy_targphys(cmdline_addr, 4096, kernel_cmdline);
905 642a4f96 ths
906 642a4f96 ths
    if (protocol >= 0x202) {
907 a37af289 blueswir1
        stl_p(header+0x228, cmdline_addr);
908 642a4f96 ths
    } else {
909 642a4f96 ths
        stw_p(header+0x20, 0xA33F);
910 642a4f96 ths
        stw_p(header+0x22, cmdline_addr-real_addr);
911 642a4f96 ths
    }
912 642a4f96 ths
913 bf4e5d92 Pascal Terjan
    /* handle vga= parameter */
914 bf4e5d92 Pascal Terjan
    vmode = strstr(kernel_cmdline, "vga=");
915 bf4e5d92 Pascal Terjan
    if (vmode) {
916 bf4e5d92 Pascal Terjan
        unsigned int video_mode;
917 bf4e5d92 Pascal Terjan
        /* skip "vga=" */
918 bf4e5d92 Pascal Terjan
        vmode += 4;
919 bf4e5d92 Pascal Terjan
        if (!strncmp(vmode, "normal", 6)) {
920 bf4e5d92 Pascal Terjan
            video_mode = 0xffff;
921 bf4e5d92 Pascal Terjan
        } else if (!strncmp(vmode, "ext", 3)) {
922 bf4e5d92 Pascal Terjan
            video_mode = 0xfffe;
923 bf4e5d92 Pascal Terjan
        } else if (!strncmp(vmode, "ask", 3)) {
924 bf4e5d92 Pascal Terjan
            video_mode = 0xfffd;
925 bf4e5d92 Pascal Terjan
        } else {
926 bf4e5d92 Pascal Terjan
            video_mode = strtol(vmode, NULL, 0);
927 bf4e5d92 Pascal Terjan
        }
928 bf4e5d92 Pascal Terjan
        stw_p(header+0x1fa, video_mode);
929 bf4e5d92 Pascal Terjan
    }
930 bf4e5d92 Pascal Terjan
931 642a4f96 ths
    /* loader type */
932 642a4f96 ths
    /* High nybble = B reserved for Qemu; low nybble is revision number.
933 642a4f96 ths
       If this code is substantially changed, you may want to consider
934 642a4f96 ths
       incrementing the revision. */
935 642a4f96 ths
    if (protocol >= 0x200)
936 642a4f96 ths
        header[0x210] = 0xB0;
937 642a4f96 ths
938 642a4f96 ths
    /* heap */
939 642a4f96 ths
    if (protocol >= 0x201) {
940 642a4f96 ths
        header[0x211] |= 0x80;        /* CAN_USE_HEAP */
941 642a4f96 ths
        stw_p(header+0x224, cmdline_addr-real_addr-0x200);
942 642a4f96 ths
    }
943 642a4f96 ths
944 642a4f96 ths
    /* load initrd */
945 642a4f96 ths
    if (initrd_filename) {
946 642a4f96 ths
        if (protocol < 0x200) {
947 642a4f96 ths
            fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
948 642a4f96 ths
            exit(1);
949 642a4f96 ths
        }
950 642a4f96 ths
951 642a4f96 ths
        fi = fopen(initrd_filename, "rb");
952 642a4f96 ths
        if (!fi) {
953 642a4f96 ths
            fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
954 642a4f96 ths
                    initrd_filename);
955 642a4f96 ths
            exit(1);
956 642a4f96 ths
        }
957 642a4f96 ths
958 642a4f96 ths
        initrd_size = get_file_size(fi);
959 a37af289 blueswir1
        initrd_addr = (initrd_max-initrd_size) & ~4095;
960 642a4f96 ths
961 a37af289 blueswir1
        if (!fread_targphys_ok(initrd_addr, initrd_size, fi)) {
962 642a4f96 ths
            fprintf(stderr, "qemu: read error on initial ram disk '%s'\n",
963 642a4f96 ths
                    initrd_filename);
964 642a4f96 ths
            exit(1);
965 642a4f96 ths
        }
966 642a4f96 ths
        fclose(fi);
967 642a4f96 ths
968 a37af289 blueswir1
        stl_p(header+0x218, initrd_addr);
969 642a4f96 ths
        stl_p(header+0x21c, initrd_size);
970 642a4f96 ths
    }
971 642a4f96 ths
972 642a4f96 ths
    /* store the finalized header and load the rest of the kernel */
973 f16408df Alexander Graf
    cpu_physical_memory_write(real_addr, header, ARRAY_SIZE(header));
974 642a4f96 ths
975 642a4f96 ths
    setup_size = header[0x1f1];
976 642a4f96 ths
    if (setup_size == 0)
977 642a4f96 ths
        setup_size = 4;
978 642a4f96 ths
979 642a4f96 ths
    setup_size = (setup_size+1)*512;
980 f16408df Alexander Graf
    /* Size of protected-mode code */
981 f16408df Alexander Graf
    kernel_size -= (setup_size > ARRAY_SIZE(header)) ? setup_size : ARRAY_SIZE(header);
982 f16408df Alexander Graf
983 f16408df Alexander Graf
    /* In case we have read too much already, copy that over */
984 f16408df Alexander Graf
    if (setup_size < ARRAY_SIZE(header)) {
985 f16408df Alexander Graf
        cpu_physical_memory_write(prot_addr, header + setup_size, ARRAY_SIZE(header) - setup_size);
986 f16408df Alexander Graf
        prot_addr += (ARRAY_SIZE(header) - setup_size);
987 f16408df Alexander Graf
        setup_size = ARRAY_SIZE(header);
988 f16408df Alexander Graf
    }
989 642a4f96 ths
990 f16408df Alexander Graf
    if (!fread_targphys_ok(real_addr + ARRAY_SIZE(header),
991 f16408df Alexander Graf
                           setup_size - ARRAY_SIZE(header), f) ||
992 a37af289 blueswir1
        !fread_targphys_ok(prot_addr, kernel_size, f)) {
993 642a4f96 ths
        fprintf(stderr, "qemu: read error on kernel '%s'\n",
994 642a4f96 ths
                kernel_filename);
995 642a4f96 ths
        exit(1);
996 642a4f96 ths
    }
997 642a4f96 ths
    fclose(f);
998 642a4f96 ths
999 642a4f96 ths
    /* generate bootsector to set up the initial register state */
1000 a37af289 blueswir1
    real_seg = real_addr >> 4;
1001 642a4f96 ths
    seg[0] = seg[2] = seg[3] = seg[4] = seg[4] = real_seg;
1002 642a4f96 ths
    seg[1] = real_seg+0x20;        /* CS */
1003 642a4f96 ths
    memset(gpr, 0, sizeof gpr);
1004 642a4f96 ths
    gpr[4] = cmdline_addr-real_addr-16;        /* SP (-16 is paranoia) */
1005 642a4f96 ths
1006 d6ecb036 Glauber Costa
    option_rom_setup_reset(real_addr, setup_size);
1007 d6ecb036 Glauber Costa
    option_rom_setup_reset(prot_addr, kernel_size);
1008 d6ecb036 Glauber Costa
    option_rom_setup_reset(cmdline_addr, cmdline_size);
1009 d6ecb036 Glauber Costa
    if (initrd_filename)
1010 d6ecb036 Glauber Costa
        option_rom_setup_reset(initrd_addr, initrd_size);
1011 d6ecb036 Glauber Costa
1012 4fc9af53 aliguori
    generate_bootsect(option_rom, gpr, seg, 0);
1013 642a4f96 ths
}
1014 642a4f96 ths
1015 b41a2cd1 bellard
static const int ide_iobase[2] = { 0x1f0, 0x170 };
1016 b41a2cd1 bellard
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
1017 b41a2cd1 bellard
static const int ide_irq[2] = { 14, 15 };
1018 b41a2cd1 bellard
1019 b41a2cd1 bellard
#define NE2000_NB_MAX 6
1020 b41a2cd1 bellard
1021 675d6f82 Blue Swirl
static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
1022 675d6f82 Blue Swirl
                                              0x280, 0x380 };
1023 675d6f82 Blue Swirl
static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
1024 b41a2cd1 bellard
1025 675d6f82 Blue Swirl
static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
1026 675d6f82 Blue Swirl
static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
1027 8d11df9e bellard
1028 675d6f82 Blue Swirl
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
1029 675d6f82 Blue Swirl
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
1030 6508fe59 bellard
1031 6a36d84e bellard
#ifdef HAS_AUDIO
1032 d537cf6c pbrook
static void audio_init (PCIBus *pci_bus, qemu_irq *pic)
1033 6a36d84e bellard
{
1034 6a36d84e bellard
    struct soundhw *c;
1035 6a36d84e bellard
1036 3a8bae3e malc
    for (c = soundhw; c->name; ++c) {
1037 3a8bae3e malc
        if (c->enabled) {
1038 3a8bae3e malc
            if (c->isa) {
1039 3a8bae3e malc
                c->init.init_isa(pic);
1040 3a8bae3e malc
            } else {
1041 3a8bae3e malc
                if (pci_bus) {
1042 3a8bae3e malc
                    c->init.init_pci(pci_bus);
1043 6a36d84e bellard
                }
1044 6a36d84e bellard
            }
1045 6a36d84e bellard
        }
1046 6a36d84e bellard
    }
1047 6a36d84e bellard
}
1048 6a36d84e bellard
#endif
1049 6a36d84e bellard
1050 3a38d437 Jes Sorensen
static void pc_init_ne2k_isa(NICInfo *nd)
1051 a41b2ff2 pbrook
{
1052 a41b2ff2 pbrook
    static int nb_ne2k = 0;
1053 a41b2ff2 pbrook
1054 a41b2ff2 pbrook
    if (nb_ne2k == NE2000_NB_MAX)
1055 a41b2ff2 pbrook
        return;
1056 3a38d437 Jes Sorensen
    isa_ne2000_init(ne2000_io[nb_ne2k],
1057 9453c5bc Gerd Hoffmann
                    ne2000_irq[nb_ne2k], nd);
1058 a41b2ff2 pbrook
    nb_ne2k++;
1059 a41b2ff2 pbrook
}
1060 a41b2ff2 pbrook
1061 c227f099 Anthony Liguori
static int load_option_rom(const char *oprom, target_phys_addr_t start,
1062 c227f099 Anthony Liguori
                           target_phys_addr_t end)
1063 f753ff16 pbrook
{
1064 82663ee2 Blue Swirl
    int size;
1065 82663ee2 Blue Swirl
    char *filename;
1066 82663ee2 Blue Swirl
1067 82663ee2 Blue Swirl
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, oprom);
1068 82663ee2 Blue Swirl
    if (filename) {
1069 82663ee2 Blue Swirl
        size = get_image_size(filename);
1070 82663ee2 Blue Swirl
        if (size > 0 && start + size > end) {
1071 82663ee2 Blue Swirl
            fprintf(stderr, "Not enough space to load option rom '%s'\n",
1072 82663ee2 Blue Swirl
                    oprom);
1073 f753ff16 pbrook
            exit(1);
1074 f753ff16 pbrook
        }
1075 82663ee2 Blue Swirl
        size = load_image_targphys(filename, start, end - start);
1076 82663ee2 Blue Swirl
        qemu_free(filename);
1077 82663ee2 Blue Swirl
    } else {
1078 82663ee2 Blue Swirl
        size = -1;
1079 82663ee2 Blue Swirl
    }
1080 82663ee2 Blue Swirl
    if (size < 0) {
1081 82663ee2 Blue Swirl
        fprintf(stderr, "Could not load option rom '%s'\n", oprom);
1082 82663ee2 Blue Swirl
        exit(1);
1083 82663ee2 Blue Swirl
    }
1084 82663ee2 Blue Swirl
    /* Round up optiom rom size to the next 2k boundary */
1085 82663ee2 Blue Swirl
    size = (size + 2047) & ~2047;
1086 82663ee2 Blue Swirl
    option_rom_setup_reset(start, size);
1087 82663ee2 Blue Swirl
    return size;
1088 f753ff16 pbrook
}
1089 f753ff16 pbrook
1090 678e12cc Gleb Natapov
int cpu_is_bsp(CPUState *env)
1091 678e12cc Gleb Natapov
{
1092 82663ee2 Blue Swirl
    return env->cpuid_apic_id == 0;
1093 678e12cc Gleb Natapov
}
1094 678e12cc Gleb Natapov
1095 3a31f36a Jan Kiszka
static CPUState *pc_new_cpu(const char *cpu_model)
1096 3a31f36a Jan Kiszka
{
1097 3a31f36a Jan Kiszka
    CPUState *env;
1098 3a31f36a Jan Kiszka
1099 3a31f36a Jan Kiszka
    env = cpu_init(cpu_model);
1100 3a31f36a Jan Kiszka
    if (!env) {
1101 3a31f36a Jan Kiszka
        fprintf(stderr, "Unable to find x86 CPU definition\n");
1102 3a31f36a Jan Kiszka
        exit(1);
1103 3a31f36a Jan Kiszka
    }
1104 3a31f36a Jan Kiszka
    if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
1105 3a31f36a Jan Kiszka
        env->cpuid_apic_id = env->cpu_index;
1106 3a31f36a Jan Kiszka
        /* APIC reset callback resets cpu */
1107 3a31f36a Jan Kiszka
        apic_init(env);
1108 3a31f36a Jan Kiszka
    } else {
1109 3a31f36a Jan Kiszka
        qemu_register_reset((QEMUResetHandler*)cpu_reset, env);
1110 3a31f36a Jan Kiszka
    }
1111 3a31f36a Jan Kiszka
    return env;
1112 3a31f36a Jan Kiszka
}
1113 3a31f36a Jan Kiszka
1114 80cabfad bellard
/* PC hardware initialisation */
1115 c227f099 Anthony Liguori
static void pc_init1(ram_addr_t ram_size,
1116 3023f332 aliguori
                     const char *boot_device,
1117 e8b2a1c6 Mark McLoughlin
                     const char *kernel_filename,
1118 e8b2a1c6 Mark McLoughlin
                     const char *kernel_cmdline,
1119 3dbbdc25 bellard
                     const char *initrd_filename,
1120 e8b2a1c6 Mark McLoughlin
                     const char *cpu_model,
1121 caea79a9 Mark McLoughlin
                     int pci_enabled)
1122 80cabfad bellard
{
1123 5cea8590 Paul Brook
    char *filename;
1124 642a4f96 ths
    int ret, linux_boot, i;
1125 c227f099 Anthony Liguori
    ram_addr_t ram_addr, bios_offset, option_rom_offset;
1126 c227f099 Anthony Liguori
    ram_addr_t below_4g_mem_size, above_4g_mem_size = 0;
1127 f753ff16 pbrook
    int bios_size, isa_bios_size, oprom_area_size;
1128 46e50e9d bellard
    PCIBus *pci_bus;
1129 b3999638 Gerd Hoffmann
    ISADevice *isa_dev;
1130 5c3ff3a7 pbrook
    int piix3_devfn = -1;
1131 59b8ad81 bellard
    CPUState *env;
1132 d537cf6c pbrook
    qemu_irq *cpu_irq;
1133 1452411b Avi Kivity
    qemu_irq *isa_irq;
1134 d537cf6c pbrook
    qemu_irq *i8259;
1135 1452411b Avi Kivity
    IsaIrqState *isa_irq_state;
1136 f455e98c Gerd Hoffmann
    DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
1137 fd8014e1 Gerd Hoffmann
    DriveInfo *fd[MAX_FD];
1138 34b39c2b aliguori
    int using_vga = cirrus_vga_enabled || std_vga_enabled || vmsvga_enabled;
1139 bf483392 Alexander Graf
    void *fw_cfg;
1140 d592d303 bellard
1141 00f82b8a aurel32
    if (ram_size >= 0xe0000000 ) {
1142 00f82b8a aurel32
        above_4g_mem_size = ram_size - 0xe0000000;
1143 00f82b8a aurel32
        below_4g_mem_size = 0xe0000000;
1144 00f82b8a aurel32
    } else {
1145 00f82b8a aurel32
        below_4g_mem_size = ram_size;
1146 00f82b8a aurel32
    }
1147 00f82b8a aurel32
1148 80cabfad bellard
    linux_boot = (kernel_filename != NULL);
1149 80cabfad bellard
1150 59b8ad81 bellard
    /* init CPUs */
1151 a049de61 bellard
    if (cpu_model == NULL) {
1152 a049de61 bellard
#ifdef TARGET_X86_64
1153 a049de61 bellard
        cpu_model = "qemu64";
1154 a049de61 bellard
#else
1155 a049de61 bellard
        cpu_model = "qemu32";
1156 a049de61 bellard
#endif
1157 a049de61 bellard
    }
1158 3a31f36a Jan Kiszka
1159 3a31f36a Jan Kiszka
    for (i = 0; i < smp_cpus; i++) {
1160 3a31f36a Jan Kiszka
        env = pc_new_cpu(cpu_model);
1161 59b8ad81 bellard
    }
1162 59b8ad81 bellard
1163 26fb5e48 aurel32
    vmport_init();
1164 26fb5e48 aurel32
1165 80cabfad bellard
    /* allocate RAM */
1166 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(0xa0000);
1167 82b36dc3 aliguori
    cpu_register_physical_memory(0, 0xa0000, ram_addr);
1168 82b36dc3 aliguori
1169 82b36dc3 aliguori
    /* Allocate, even though we won't register, so we don't break the
1170 82b36dc3 aliguori
     * phys_ram_base + PA assumption. This range includes vga (0xa0000 - 0xc0000),
1171 82b36dc3 aliguori
     * and some bios areas, which will be registered later
1172 82b36dc3 aliguori
     */
1173 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(0x100000 - 0xa0000);
1174 82b36dc3 aliguori
    ram_addr = qemu_ram_alloc(below_4g_mem_size - 0x100000);
1175 82b36dc3 aliguori
    cpu_register_physical_memory(0x100000,
1176 82b36dc3 aliguori
                 below_4g_mem_size - 0x100000,
1177 82b36dc3 aliguori
                 ram_addr);
1178 00f82b8a aurel32
1179 00f82b8a aurel32
    /* above 4giga memory allocation */
1180 00f82b8a aurel32
    if (above_4g_mem_size > 0) {
1181 8a637d44 Paul Brook
#if TARGET_PHYS_ADDR_BITS == 32
1182 8a637d44 Paul Brook
        hw_error("To much RAM for 32-bit physical address");
1183 8a637d44 Paul Brook
#else
1184 82b36dc3 aliguori
        ram_addr = qemu_ram_alloc(above_4g_mem_size);
1185 82b36dc3 aliguori
        cpu_register_physical_memory(0x100000000ULL,
1186 526ccb7a balrog
                                     above_4g_mem_size,
1187 82b36dc3 aliguori
                                     ram_addr);
1188 8a637d44 Paul Brook
#endif
1189 00f82b8a aurel32
    }
1190 80cabfad bellard
1191 82b36dc3 aliguori
1192 970ac5a3 bellard
    /* BIOS load */
1193 1192dad8 j_mayer
    if (bios_name == NULL)
1194 1192dad8 j_mayer
        bios_name = BIOS_FILENAME;
1195 5cea8590 Paul Brook
    filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
1196 5cea8590 Paul Brook
    if (filename) {
1197 5cea8590 Paul Brook
        bios_size = get_image_size(filename);
1198 5cea8590 Paul Brook
    } else {
1199 5cea8590 Paul Brook
        bios_size = -1;
1200 5cea8590 Paul Brook
    }
1201 5fafdf24 ths
    if (bios_size <= 0 ||
1202 970ac5a3 bellard
        (bios_size % 65536) != 0) {
1203 7587cf44 bellard
        goto bios_error;
1204 7587cf44 bellard
    }
1205 970ac5a3 bellard
    bios_offset = qemu_ram_alloc(bios_size);
1206 5cea8590 Paul Brook
    ret = load_image(filename, qemu_get_ram_ptr(bios_offset));
1207 7587cf44 bellard
    if (ret != bios_size) {
1208 7587cf44 bellard
    bios_error:
1209 5cea8590 Paul Brook
        fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
1210 80cabfad bellard
        exit(1);
1211 80cabfad bellard
    }
1212 5cea8590 Paul Brook
    if (filename) {
1213 5cea8590 Paul Brook
        qemu_free(filename);
1214 5cea8590 Paul Brook
    }
1215 7587cf44 bellard
    /* map the last 128KB of the BIOS in ISA space */
1216 7587cf44 bellard
    isa_bios_size = bios_size;
1217 7587cf44 bellard
    if (isa_bios_size > (128 * 1024))
1218 7587cf44 bellard
        isa_bios_size = 128 * 1024;
1219 5fafdf24 ths
    cpu_register_physical_memory(0x100000 - isa_bios_size,
1220 5fafdf24 ths
                                 isa_bios_size,
1221 7587cf44 bellard
                                 (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
1222 9ae02555 ths
1223 4fc9af53 aliguori
1224 f753ff16 pbrook
1225 f753ff16 pbrook
    option_rom_offset = qemu_ram_alloc(0x20000);
1226 f753ff16 pbrook
    oprom_area_size = 0;
1227 49669fc5 Glauber Costa
    cpu_register_physical_memory(0xc0000, 0x20000, option_rom_offset);
1228 f753ff16 pbrook
1229 f753ff16 pbrook
    if (using_vga) {
1230 5cea8590 Paul Brook
        const char *vgabios_filename;
1231 f753ff16 pbrook
        /* VGA BIOS load */
1232 f753ff16 pbrook
        if (cirrus_vga_enabled) {
1233 5cea8590 Paul Brook
            vgabios_filename = VGABIOS_CIRRUS_FILENAME;
1234 f753ff16 pbrook
        } else {
1235 5cea8590 Paul Brook
            vgabios_filename = VGABIOS_FILENAME;
1236 970ac5a3 bellard
        }
1237 5cea8590 Paul Brook
        oprom_area_size = load_option_rom(vgabios_filename, 0xc0000, 0xe0000);
1238 f753ff16 pbrook
    }
1239 f753ff16 pbrook
    /* Although video roms can grow larger than 0x8000, the area between
1240 f753ff16 pbrook
     * 0xc0000 - 0xc8000 is reserved for them. It means we won't be looking
1241 f753ff16 pbrook
     * for any other kind of option rom inside this area */
1242 f753ff16 pbrook
    if (oprom_area_size < 0x8000)
1243 f753ff16 pbrook
        oprom_area_size = 0x8000;
1244 f753ff16 pbrook
1245 1d108d97 Alexander Graf
    /* map all the bios at the top of memory */
1246 1d108d97 Alexander Graf
    cpu_register_physical_memory((uint32_t)(-bios_size),
1247 1d108d97 Alexander Graf
                                 bios_size, bios_offset | IO_MEM_ROM);
1248 1d108d97 Alexander Graf
1249 bf483392 Alexander Graf
    fw_cfg = bochs_bios_init();
1250 1d108d97 Alexander Graf
1251 f753ff16 pbrook
    if (linux_boot) {
1252 f16408df Alexander Graf
        load_linux(fw_cfg, 0xc0000 + oprom_area_size,
1253 e6ade764 Glauber Costa
                   kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
1254 f753ff16 pbrook
        oprom_area_size += 2048;
1255 f753ff16 pbrook
    }
1256 f753ff16 pbrook
1257 f753ff16 pbrook
    for (i = 0; i < nb_option_roms; i++) {
1258 406c8df3 Glauber Costa
        oprom_area_size += load_option_rom(option_rom[i], 0xc0000 + oprom_area_size,
1259 406c8df3 Glauber Costa
                                           0xe0000);
1260 406c8df3 Glauber Costa
    }
1261 406c8df3 Glauber Costa
1262 406c8df3 Glauber Costa
    for (i = 0; i < nb_nics; i++) {
1263 406c8df3 Glauber Costa
        char nic_oprom[1024];
1264 406c8df3 Glauber Costa
        const char *model = nd_table[i].model;
1265 406c8df3 Glauber Costa
1266 406c8df3 Glauber Costa
        if (!nd_table[i].bootable)
1267 406c8df3 Glauber Costa
            continue;
1268 406c8df3 Glauber Costa
1269 406c8df3 Glauber Costa
        if (model == NULL)
1270 0d6b0b1d Anthony Liguori
            model = "e1000";
1271 406c8df3 Glauber Costa
        snprintf(nic_oprom, sizeof(nic_oprom), "pxe-%s.bin", model);
1272 406c8df3 Glauber Costa
1273 406c8df3 Glauber Costa
        oprom_area_size += load_option_rom(nic_oprom, 0xc0000 + oprom_area_size,
1274 406c8df3 Glauber Costa
                                           0xe0000);
1275 9ae02555 ths
    }
1276 9ae02555 ths
1277 a5b38b51 aurel32
    cpu_irq = qemu_allocate_irqs(pic_irq_request, NULL, 1);
1278 d537cf6c pbrook
    i8259 = i8259_init(cpu_irq[0]);
1279 1452411b Avi Kivity
    isa_irq_state = qemu_mallocz(sizeof(*isa_irq_state));
1280 1452411b Avi Kivity
    isa_irq_state->i8259 = i8259;
1281 1632dc6a Avi Kivity
    isa_irq = qemu_allocate_irqs(isa_irq_handler, isa_irq_state, 24);
1282 d537cf6c pbrook
1283 69b91039 bellard
    if (pci_enabled) {
1284 85a750ca Juan Quintela
        pci_bus = i440fx_init(&i440fx_state, &piix3_devfn, isa_irq);
1285 46e50e9d bellard
    } else {
1286 46e50e9d bellard
        pci_bus = NULL;
1287 2091ba23 Gerd Hoffmann
        isa_bus_new(NULL);
1288 69b91039 bellard
    }
1289 2091ba23 Gerd Hoffmann
    isa_bus_irqs(isa_irq);
1290 69b91039 bellard
1291 3a38d437 Jes Sorensen
    ferr_irq = isa_reserve_irq(13);
1292 3a38d437 Jes Sorensen
1293 80cabfad bellard
    /* init basic PC hardware */
1294 b41a2cd1 bellard
    register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1295 80cabfad bellard
1296 f929aad6 bellard
    register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1297 f929aad6 bellard
1298 1f04275e bellard
    if (cirrus_vga_enabled) {
1299 1f04275e bellard
        if (pci_enabled) {
1300 fbe1b595 Paul Brook
            pci_cirrus_vga_init(pci_bus);
1301 1f04275e bellard
        } else {
1302 fbe1b595 Paul Brook
            isa_cirrus_vga_init();
1303 1f04275e bellard
        }
1304 d34cab9f ths
    } else if (vmsvga_enabled) {
1305 d34cab9f ths
        if (pci_enabled)
1306 fbe1b595 Paul Brook
            pci_vmsvga_init(pci_bus);
1307 d34cab9f ths
        else
1308 d34cab9f ths
            fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
1309 c2b3b41a aliguori
    } else if (std_vga_enabled) {
1310 89b6b508 bellard
        if (pci_enabled) {
1311 fbe1b595 Paul Brook
            pci_vga_init(pci_bus, 0, 0);
1312 89b6b508 bellard
        } else {
1313 fbe1b595 Paul Brook
            isa_vga_init();
1314 89b6b508 bellard
        }
1315 1f04275e bellard
    }
1316 80cabfad bellard
1317 32e0c826 Gerd Hoffmann
    rtc_state = rtc_init(2000);
1318 80cabfad bellard
1319 3b4366de blueswir1
    qemu_register_boot_set(pc_boot_set, rtc_state);
1320 3b4366de blueswir1
1321 e1a23744 bellard
    register_ioport_read(0x92, 1, 1, ioport92_read, NULL);
1322 e1a23744 bellard
    register_ioport_write(0x92, 1, 1, ioport92_write, NULL);
1323 e1a23744 bellard
1324 d592d303 bellard
    if (pci_enabled) {
1325 1632dc6a Avi Kivity
        isa_irq_state->ioapic = ioapic_init();
1326 d592d303 bellard
    }
1327 3a38d437 Jes Sorensen
    pit = pit_init(0x40, isa_reserve_irq(0));
1328 fd06c375 bellard
    pcspk_init(pit);
1329 16b29ae1 aliguori
    if (!no_hpet) {
1330 1452411b Avi Kivity
        hpet_init(isa_irq);
1331 16b29ae1 aliguori
    }
1332 b41a2cd1 bellard
1333 8d11df9e bellard
    for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1334 8d11df9e bellard
        if (serial_hds[i]) {
1335 3a38d437 Jes Sorensen
            serial_init(serial_io[i], isa_reserve_irq(serial_irq[i]), 115200,
1336 b6cd0ea1 aurel32
                        serial_hds[i]);
1337 8d11df9e bellard
        }
1338 8d11df9e bellard
    }
1339 b41a2cd1 bellard
1340 6508fe59 bellard
    for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1341 6508fe59 bellard
        if (parallel_hds[i]) {
1342 021f0674 Gerd Hoffmann
            parallel_init(i, parallel_hds[i]);
1343 6508fe59 bellard
        }
1344 6508fe59 bellard
    }
1345 6508fe59 bellard
1346 a41b2ff2 pbrook
    for(i = 0; i < nb_nics; i++) {
1347 cb457d76 aliguori
        NICInfo *nd = &nd_table[i];
1348 cb457d76 aliguori
1349 cb457d76 aliguori
        if (!pci_enabled || (nd->model && strcmp(nd->model, "ne2k_isa") == 0))
1350 3a38d437 Jes Sorensen
            pc_init_ne2k_isa(nd);
1351 cb457d76 aliguori
        else
1352 0d6b0b1d Anthony Liguori
            pci_nic_init(nd, "e1000", NULL);
1353 a41b2ff2 pbrook
    }
1354 b41a2cd1 bellard
1355 e4bcb14c ths
    if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
1356 e4bcb14c ths
        fprintf(stderr, "qemu: too many IDE bus\n");
1357 e4bcb14c ths
        exit(1);
1358 e4bcb14c ths
    }
1359 e4bcb14c ths
1360 e4bcb14c ths
    for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
1361 f455e98c Gerd Hoffmann
        hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
1362 e4bcb14c ths
    }
1363 e4bcb14c ths
1364 a41b2ff2 pbrook
    if (pci_enabled) {
1365 ae027ad3 Stefan Weil
        pci_piix3_ide_init(pci_bus, hd, piix3_devfn + 1);
1366 a41b2ff2 pbrook
    } else {
1367 e4bcb14c ths
        for(i = 0; i < MAX_IDE_BUS; i++) {
1368 dea21e97 Gerd Hoffmann
            isa_ide_init(ide_iobase[i], ide_iobase2[i], ide_irq[i],
1369 e4bcb14c ths
                         hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]);
1370 69b91039 bellard
        }
1371 b41a2cd1 bellard
    }
1372 69b91039 bellard
1373 2e15e23b Gerd Hoffmann
    isa_dev = isa_create_simple("i8042");
1374 7c29d0c0 bellard
    DMA_init(0);
1375 6a36d84e bellard
#ifdef HAS_AUDIO
1376 1452411b Avi Kivity
    audio_init(pci_enabled ? pci_bus : NULL, isa_irq);
1377 fb065187 bellard
#endif
1378 80cabfad bellard
1379 e4bcb14c ths
    for(i = 0; i < MAX_FD; i++) {
1380 fd8014e1 Gerd Hoffmann
        fd[i] = drive_get(IF_FLOPPY, 0, i);
1381 e4bcb14c ths
    }
1382 86c86157 Gerd Hoffmann
    floppy_controller = fdctrl_init_isa(fd);
1383 b41a2cd1 bellard
1384 00f82b8a aurel32
    cmos_init(below_4g_mem_size, above_4g_mem_size, boot_device, hd);
1385 69b91039 bellard
1386 bb36d470 bellard
    if (pci_enabled && usb_enabled) {
1387 afcc3cdf ths
        usb_uhci_piix3_init(pci_bus, piix3_devfn + 2);
1388 bb36d470 bellard
    }
1389 bb36d470 bellard
1390 6515b203 bellard
    if (pci_enabled && acpi_enabled) {
1391 3fffc223 ths
        uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */
1392 0ff596d0 pbrook
        i2c_bus *smbus;
1393 0ff596d0 pbrook
1394 0ff596d0 pbrook
        /* TODO: Populate SPD eeprom data.  */
1395 3a38d437 Jes Sorensen
        smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
1396 3a38d437 Jes Sorensen
                              isa_reserve_irq(9));
1397 3fffc223 ths
        for (i = 0; i < 8; i++) {
1398 1ea96673 Paul Brook
            DeviceState *eeprom;
1399 02e2da45 Paul Brook
            eeprom = qdev_create((BusState *)smbus, "smbus-eeprom");
1400 5b7f5327 Juan Quintela
            qdev_prop_set_uint8(eeprom, "address", 0x50 + i);
1401 ee6847d1 Gerd Hoffmann
            qdev_prop_set_ptr(eeprom, "data", eeprom_buf + (i * 256));
1402 1ea96673 Paul Brook
            qdev_init(eeprom);
1403 3fffc223 ths
        }
1404 3f84865a Gerd Hoffmann
        piix4_acpi_system_hot_add_init(pci_bus);
1405 6515b203 bellard
    }
1406 3b46e624 ths
1407 a5954d5c bellard
    if (i440fx_state) {
1408 a5954d5c bellard
        i440fx_init_memory_mappings(i440fx_state);
1409 a5954d5c bellard
    }
1410 e4bcb14c ths
1411 7d8406be pbrook
    if (pci_enabled) {
1412 e4bcb14c ths
        int max_bus;
1413 9be5dafe Paul Brook
        int bus;
1414 96d30e48 ths
1415 e4bcb14c ths
        max_bus = drive_get_max_bus(IF_SCSI);
1416 e4bcb14c ths
        for (bus = 0; bus <= max_bus; bus++) {
1417 9be5dafe Paul Brook
            pci_create_simple(pci_bus, -1, "lsi53c895a");
1418 e4bcb14c ths
        }
1419 7d8406be pbrook
    }
1420 6e02c38d aliguori
1421 a2fa19f9 aliguori
    /* Add virtio console devices */
1422 a2fa19f9 aliguori
    if (pci_enabled) {
1423 a2fa19f9 aliguori
        for(i = 0; i < MAX_VIRTIO_CONSOLES; i++) {
1424 0e058a8a Paul Brook
            if (virtcon_hds[i]) {
1425 caea79a9 Mark McLoughlin
                pci_create_simple(pci_bus, -1, "virtio-console-pci");
1426 0e058a8a Paul Brook
            }
1427 a2fa19f9 aliguori
        }
1428 a2fa19f9 aliguori
    }
1429 80cabfad bellard
}
1430 b5ff2d6e bellard
1431 c227f099 Anthony Liguori
static void pc_init_pci(ram_addr_t ram_size,
1432 3023f332 aliguori
                        const char *boot_device,
1433 5fafdf24 ths
                        const char *kernel_filename,
1434 3dbbdc25 bellard
                        const char *kernel_cmdline,
1435 94fc95cd j_mayer
                        const char *initrd_filename,
1436 94fc95cd j_mayer
                        const char *cpu_model)
1437 3dbbdc25 bellard
{
1438 fbe1b595 Paul Brook
    pc_init1(ram_size, boot_device,
1439 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1440 caea79a9 Mark McLoughlin
             initrd_filename, cpu_model, 1);
1441 3dbbdc25 bellard
}
1442 3dbbdc25 bellard
1443 c227f099 Anthony Liguori
static void pc_init_isa(ram_addr_t ram_size,
1444 3023f332 aliguori
                        const char *boot_device,
1445 5fafdf24 ths
                        const char *kernel_filename,
1446 3dbbdc25 bellard
                        const char *kernel_cmdline,
1447 94fc95cd j_mayer
                        const char *initrd_filename,
1448 94fc95cd j_mayer
                        const char *cpu_model)
1449 3dbbdc25 bellard
{
1450 679a37af Gerd Hoffmann
    if (cpu_model == NULL)
1451 679a37af Gerd Hoffmann
        cpu_model = "486";
1452 fbe1b595 Paul Brook
    pc_init1(ram_size, boot_device,
1453 3dbbdc25 bellard
             kernel_filename, kernel_cmdline,
1454 caea79a9 Mark McLoughlin
             initrd_filename, cpu_model, 0);
1455 3dbbdc25 bellard
}
1456 3dbbdc25 bellard
1457 0bacd130 aliguori
/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE)
1458 0bacd130 aliguori
   BIOS will read it and start S3 resume at POST Entry */
1459 0bacd130 aliguori
void cmos_set_s3_resume(void)
1460 0bacd130 aliguori
{
1461 0bacd130 aliguori
    if (rtc_state)
1462 0bacd130 aliguori
        rtc_set_memory(rtc_state, 0xF, 0xFE);
1463 0bacd130 aliguori
}
1464 0bacd130 aliguori
1465 f80f9ec9 Anthony Liguori
static QEMUMachine pc_machine = {
1466 95747581 Mark McLoughlin
    .name = "pc-0.11",
1467 95747581 Mark McLoughlin
    .alias = "pc",
1468 a245f2e7 aurel32
    .desc = "Standard PC",
1469 a245f2e7 aurel32
    .init = pc_init_pci,
1470 b2097003 aliguori
    .max_cpus = 255,
1471 0c257437 Anthony Liguori
    .is_default = 1,
1472 3dbbdc25 bellard
};
1473 3dbbdc25 bellard
1474 96cc1810 Gerd Hoffmann
static QEMUMachine pc_machine_v0_10 = {
1475 96cc1810 Gerd Hoffmann
    .name = "pc-0.10",
1476 96cc1810 Gerd Hoffmann
    .desc = "Standard PC, qemu 0.10",
1477 96cc1810 Gerd Hoffmann
    .init = pc_init_pci,
1478 96cc1810 Gerd Hoffmann
    .max_cpus = 255,
1479 96cc1810 Gerd Hoffmann
    .compat_props = (CompatProperty[]) {
1480 ab73ff29 Gerd Hoffmann
        {
1481 ab73ff29 Gerd Hoffmann
            .driver   = "virtio-blk-pci",
1482 ab73ff29 Gerd Hoffmann
            .property = "class",
1483 ab73ff29 Gerd Hoffmann
            .value    = stringify(PCI_CLASS_STORAGE_OTHER),
1484 d6beee99 Gerd Hoffmann
        },{
1485 d6beee99 Gerd Hoffmann
            .driver   = "virtio-console-pci",
1486 d6beee99 Gerd Hoffmann
            .property = "class",
1487 d6beee99 Gerd Hoffmann
            .value    = stringify(PCI_CLASS_DISPLAY_OTHER),
1488 a1e0fea5 Gerd Hoffmann
        },{
1489 a1e0fea5 Gerd Hoffmann
            .driver   = "virtio-net-pci",
1490 a1e0fea5 Gerd Hoffmann
            .property = "vectors",
1491 a1e0fea5 Gerd Hoffmann
            .value    = stringify(0),
1492 177539e0 Gerd Hoffmann
        },{
1493 177539e0 Gerd Hoffmann
            .driver   = "virtio-blk-pci",
1494 177539e0 Gerd Hoffmann
            .property = "vectors",
1495 177539e0 Gerd Hoffmann
            .value    = stringify(0),
1496 ab73ff29 Gerd Hoffmann
        },
1497 96cc1810 Gerd Hoffmann
        { /* end of list */ }
1498 96cc1810 Gerd Hoffmann
    },
1499 96cc1810 Gerd Hoffmann
};
1500 96cc1810 Gerd Hoffmann
1501 f80f9ec9 Anthony Liguori
static QEMUMachine isapc_machine = {
1502 a245f2e7 aurel32
    .name = "isapc",
1503 a245f2e7 aurel32
    .desc = "ISA-only PC",
1504 a245f2e7 aurel32
    .init = pc_init_isa,
1505 b2097003 aliguori
    .max_cpus = 1,
1506 b5ff2d6e bellard
};
1507 f80f9ec9 Anthony Liguori
1508 f80f9ec9 Anthony Liguori
static void pc_machine_init(void)
1509 f80f9ec9 Anthony Liguori
{
1510 f80f9ec9 Anthony Liguori
    qemu_register_machine(&pc_machine);
1511 96cc1810 Gerd Hoffmann
    qemu_register_machine(&pc_machine_v0_10);
1512 f80f9ec9 Anthony Liguori
    qemu_register_machine(&isapc_machine);
1513 f80f9ec9 Anthony Liguori
}
1514 f80f9ec9 Anthony Liguori
1515 f80f9ec9 Anthony Liguori
machine_init(pc_machine_init);