Revision fdfba1a2 target-i386/helper.c
| b/target-i386/helper.c | ||
|---|---|---|
| 515 | 515 |
int cpu_x86_handle_mmu_fault(CPUX86State *env, target_ulong addr, |
| 516 | 516 |
int is_write1, int mmu_idx) |
| 517 | 517 |
{
|
| 518 |
CPUState *cs = ENV_GET_CPU(env); |
|
| 518 | 519 |
uint64_t ptep, pte; |
| 519 | 520 |
target_ulong pde_addr, pte_addr; |
| 520 | 521 |
int error_code, is_dirty, prot, page_size, is_write, is_user; |
| ... | ... | |
| 734 | 735 |
/* page directory entry */ |
| 735 | 736 |
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & |
| 736 | 737 |
env->a20_mask; |
| 737 |
pde = ldl_phys(pde_addr); |
|
| 738 |
pde = ldl_phys(cs->as, pde_addr);
|
|
| 738 | 739 |
if (!(pde & PG_PRESENT_MASK)) {
|
| 739 | 740 |
error_code = 0; |
| 740 | 741 |
goto do_fault; |
| ... | ... | |
| 792 | 793 |
/* page directory entry */ |
| 793 | 794 |
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & |
| 794 | 795 |
env->a20_mask; |
| 795 |
pte = ldl_phys(pte_addr); |
|
| 796 |
pte = ldl_phys(cs->as, pte_addr);
|
|
| 796 | 797 |
if (!(pte & PG_PRESENT_MASK)) {
|
| 797 | 798 |
error_code = 0; |
| 798 | 799 |
goto do_fault; |
| ... | ... | |
| 963 | 964 |
|
| 964 | 965 |
/* page directory entry */ |
| 965 | 966 |
pde_addr = ((env->cr[3] & ~0xfff) + ((addr >> 20) & 0xffc)) & env->a20_mask; |
| 966 |
pde = ldl_phys(pde_addr); |
|
| 967 |
pde = ldl_phys(cs->as, pde_addr);
|
|
| 967 | 968 |
if (!(pde & PG_PRESENT_MASK)) |
| 968 | 969 |
return -1; |
| 969 | 970 |
if ((pde & PG_PSE_MASK) && (env->cr[4] & CR4_PSE_MASK)) {
|
| ... | ... | |
| 972 | 973 |
} else {
|
| 973 | 974 |
/* page directory entry */ |
| 974 | 975 |
pte_addr = ((pde & ~0xfff) + ((addr >> 10) & 0xffc)) & env->a20_mask; |
| 975 |
pte = ldl_phys(pte_addr); |
|
| 976 |
pte = ldl_phys(cs->as, pte_addr);
|
|
| 976 | 977 |
if (!(pte & PG_PRESENT_MASK)) |
| 977 | 978 |
return -1; |
| 978 | 979 |
page_size = 4096; |
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