root / target-i386 / seg_helper.c @ fdfba1a2
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/*
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* x86 segmentation related helpers:
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* TSS, interrupts, system calls, jumps and call/task gates, descriptors
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h" |
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#include "qemu/log.h" |
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#include "helper.h" |
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//#define DEBUG_PCALL
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#if !defined(CONFIG_USER_ONLY)
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#include "exec/softmmu_exec.h" |
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#endif /* !defined(CONFIG_USER_ONLY) */ |
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#ifdef DEBUG_PCALL
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# define LOG_PCALL(...) qemu_log_mask(CPU_LOG_PCALL, ## __VA_ARGS__) |
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# define LOG_PCALL_STATE(cpu) \
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log_cpu_state_mask(CPU_LOG_PCALL, (cpu), CPU_DUMP_CCOP) |
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#else
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# define LOG_PCALL(...) do { } while (0) |
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# define LOG_PCALL_STATE(cpu) do { } while (0) |
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#endif
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/* return non zero if error */
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static inline int load_segment(CPUX86State *env, uint32_t *e1_ptr, |
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uint32_t *e2_ptr, int selector)
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{ |
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SegmentCache *dt; |
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int index;
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target_ulong ptr; |
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if (selector & 0x4) { |
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dt = &env->ldt; |
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} else {
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dt = &env->gdt; |
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} |
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index = selector & ~7;
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if ((index + 7) > dt->limit) { |
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return -1; |
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} |
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ptr = dt->base + index; |
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*e1_ptr = cpu_ldl_kernel(env, ptr); |
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*e2_ptr = cpu_ldl_kernel(env, ptr + 4);
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return 0; |
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} |
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static inline unsigned int get_seg_limit(uint32_t e1, uint32_t e2) |
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{ |
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unsigned int limit; |
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limit = (e1 & 0xffff) | (e2 & 0x000f0000); |
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if (e2 & DESC_G_MASK) {
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limit = (limit << 12) | 0xfff; |
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} |
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return limit;
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} |
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static inline uint32_t get_seg_base(uint32_t e1, uint32_t e2) |
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{ |
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return (e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000); |
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} |
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static inline void load_seg_cache_raw_dt(SegmentCache *sc, uint32_t e1, |
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uint32_t e2) |
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{ |
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sc->base = get_seg_base(e1, e2); |
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sc->limit = get_seg_limit(e1, e2); |
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sc->flags = e2; |
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} |
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/* init the segment cache in vm86 mode. */
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static inline void load_seg_vm(CPUX86State *env, int seg, int selector) |
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{ |
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selector &= 0xffff;
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cpu_x86_load_seg_cache(env, seg, selector, |
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(selector << 4), 0xffff, 0); |
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} |
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static inline void get_ss_esp_from_tss(CPUX86State *env, uint32_t *ss_ptr, |
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uint32_t *esp_ptr, int dpl)
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{ |
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int type, index, shift;
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#if 0
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{
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int i;
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printf("TR: base=%p limit=%x\n", env->tr.base, env->tr.limit);
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for (i = 0; i < env->tr.limit; i++) {
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printf("%02x ", env->tr.base[i]);
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if ((i & 7) == 7) {
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printf("\n");
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}
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}
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printf("\n");
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}
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#endif
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if (!(env->tr.flags & DESC_P_MASK)) {
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cpu_abort(env, "invalid tss");
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} |
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type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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if ((type & 7) != 1) { |
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cpu_abort(env, "invalid tss type");
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} |
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shift = type >> 3;
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index = (dpl * 4 + 2) << shift; |
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if (index + (4 << shift) - 1 > env->tr.limit) { |
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raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
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} |
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if (shift == 0) { |
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*esp_ptr = cpu_lduw_kernel(env, env->tr.base + index); |
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*ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 2);
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} else {
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*esp_ptr = cpu_ldl_kernel(env, env->tr.base + index); |
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*ss_ptr = cpu_lduw_kernel(env, env->tr.base + index + 4);
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} |
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} |
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/* XXX: merge with load_seg() */
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static void tss_load_seg(CPUX86State *env, int seg_reg, int selector) |
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{ |
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uint32_t e1, e2; |
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int rpl, dpl, cpl;
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if ((selector & 0xfffc) != 0) { |
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if (load_segment(env, &e1, &e2, selector) != 0) { |
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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if (!(e2 & DESC_S_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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rpl = selector & 3;
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dpl = (e2 >> DESC_DPL_SHIFT) & 3;
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cpl = env->hflags & HF_CPL_MASK; |
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if (seg_reg == R_CS) {
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if (!(e2 & DESC_CS_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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/* XXX: is it correct? */
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if (dpl != rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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if ((e2 & DESC_C_MASK) && dpl > rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} else if (seg_reg == R_SS) { |
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/* SS must be writable data */
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if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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if (dpl != cpl || dpl != rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} else {
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/* not readable code */
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if ((e2 & DESC_CS_MASK) && !(e2 & DESC_R_MASK)) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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/* if data or non conforming code, checks the rights */
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if (((e2 >> DESC_TYPE_SHIFT) & 0xf) < 12) { |
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if (dpl < cpl || dpl < rpl) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} |
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} |
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
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} |
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cpu_x86_load_seg_cache(env, seg_reg, selector, |
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get_seg_base(e1, e2), |
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get_seg_limit(e1, e2), |
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e2); |
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} else {
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if (seg_reg == R_SS || seg_reg == R_CS) {
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raise_exception_err(env, EXCP0A_TSS, selector & 0xfffc);
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} |
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} |
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} |
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#define SWITCH_TSS_JMP 0 |
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#define SWITCH_TSS_IRET 1 |
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#define SWITCH_TSS_CALL 2 |
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/* XXX: restore CPU state in registers (PowerPC case) */
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static void switch_tss(CPUX86State *env, int tss_selector, |
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uint32_t e1, uint32_t e2, int source,
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uint32_t next_eip) |
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{ |
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int tss_limit, tss_limit_max, type, old_tss_limit_max, old_type, v1, v2, i;
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target_ulong tss_base; |
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uint32_t new_regs[8], new_segs[6]; |
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uint32_t new_eflags, new_eip, new_cr3, new_ldt, new_trap; |
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uint32_t old_eflags, eflags_mask; |
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SegmentCache *dt; |
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int index;
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target_ulong ptr; |
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type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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LOG_PCALL("switch_tss: sel=0x%04x type=%d src=%d\n", tss_selector, type,
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source); |
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/* if task gate, we read the TSS segment and we load it */
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if (type == 5) { |
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
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} |
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tss_selector = e1 >> 16;
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if (tss_selector & 4) { |
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raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
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} |
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if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
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raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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} |
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if (e2 & DESC_S_MASK) {
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raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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} |
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type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
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if ((type & 7) != 1) { |
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raise_exception_err(env, EXCP0D_GPF, tss_selector & 0xfffc);
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} |
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} |
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if (!(e2 & DESC_P_MASK)) {
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raise_exception_err(env, EXCP0B_NOSEG, tss_selector & 0xfffc);
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} |
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if (type & 8) { |
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tss_limit_max = 103;
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} else {
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tss_limit_max = 43;
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} |
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tss_limit = get_seg_limit(e1, e2); |
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tss_base = get_seg_base(e1, e2); |
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if ((tss_selector & 4) != 0 || |
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tss_limit < tss_limit_max) { |
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raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
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} |
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old_type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
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if (old_type & 8) { |
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old_tss_limit_max = 103;
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} else {
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old_tss_limit_max = 43;
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} |
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/* read all the registers from the new TSS */
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if (type & 8) { |
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/* 32 bit */
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new_cr3 = cpu_ldl_kernel(env, tss_base + 0x1c);
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new_eip = cpu_ldl_kernel(env, tss_base + 0x20);
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new_eflags = cpu_ldl_kernel(env, tss_base + 0x24);
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for (i = 0; i < 8; i++) { |
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new_regs[i] = cpu_ldl_kernel(env, tss_base + (0x28 + i * 4)); |
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} |
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for (i = 0; i < 6; i++) { |
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new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x48 + i * 4)); |
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} |
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new_ldt = cpu_lduw_kernel(env, tss_base + 0x60);
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new_trap = cpu_ldl_kernel(env, tss_base + 0x64);
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} else {
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/* 16 bit */
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new_cr3 = 0;
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new_eip = cpu_lduw_kernel(env, tss_base + 0x0e);
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new_eflags = cpu_lduw_kernel(env, tss_base + 0x10);
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for (i = 0; i < 8; i++) { |
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new_regs[i] = cpu_lduw_kernel(env, tss_base + (0x12 + i * 2)) | |
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0xffff0000;
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} |
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for (i = 0; i < 4; i++) { |
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new_segs[i] = cpu_lduw_kernel(env, tss_base + (0x22 + i * 4)); |
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} |
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new_ldt = cpu_lduw_kernel(env, tss_base + 0x2a);
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new_segs[R_FS] = 0;
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new_segs[R_GS] = 0;
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new_trap = 0;
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} |
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/* XXX: avoid a compiler warning, see
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http://support.amd.com/us/Processor_TechDocs/24593.pdf
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chapters 12.2.5 and 13.2.4 on how to implement TSS Trap bit */
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(void)new_trap;
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/* NOTE: we must avoid memory exceptions during the task switch,
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so we make dummy accesses before */
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/* XXX: it can still fail in some cases, so a bigger hack is
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necessary to valid the TLB after having done the accesses */
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v1 = cpu_ldub_kernel(env, env->tr.base); |
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v2 = cpu_ldub_kernel(env, env->tr.base + old_tss_limit_max); |
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cpu_stb_kernel(env, env->tr.base, v1); |
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cpu_stb_kernel(env, env->tr.base + old_tss_limit_max, v2); |
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/* clear busy bit (it is restartable) */
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if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_IRET) {
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target_ulong ptr; |
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uint32_t e2; |
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ptr = env->gdt.base + (env->tr.selector & ~7);
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e2 = cpu_ldl_kernel(env, ptr + 4);
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e2 &= ~DESC_TSS_BUSY_MASK; |
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cpu_stl_kernel(env, ptr + 4, e2);
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} |
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old_eflags = cpu_compute_eflags(env); |
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if (source == SWITCH_TSS_IRET) {
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old_eflags &= ~NT_MASK; |
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} |
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/* save the current state in the old TSS */
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if (type & 8) { |
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/* 32 bit */
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cpu_stl_kernel(env, env->tr.base + 0x20, next_eip);
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cpu_stl_kernel(env, env->tr.base + 0x24, old_eflags);
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cpu_stl_kernel(env, env->tr.base + (0x28 + 0 * 4), env->regs[R_EAX]); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 1 * 4), env->regs[R_ECX]); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 2 * 4), env->regs[R_EDX]); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 3 * 4), env->regs[R_EBX]); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 4 * 4), env->regs[R_ESP]); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 5 * 4), env->regs[R_EBP]); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 6 * 4), env->regs[R_ESI]); |
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cpu_stl_kernel(env, env->tr.base + (0x28 + 7 * 4), env->regs[R_EDI]); |
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for (i = 0; i < 6; i++) { |
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cpu_stw_kernel(env, env->tr.base + (0x48 + i * 4), |
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env->segs[i].selector); |
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} |
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} else {
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/* 16 bit */
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cpu_stw_kernel(env, env->tr.base + 0x0e, next_eip);
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cpu_stw_kernel(env, env->tr.base + 0x10, old_eflags);
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cpu_stw_kernel(env, env->tr.base + (0x12 + 0 * 2), env->regs[R_EAX]); |
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cpu_stw_kernel(env, env->tr.base + (0x12 + 1 * 2), env->regs[R_ECX]); |
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cpu_stw_kernel(env, env->tr.base + (0x12 + 2 * 2), env->regs[R_EDX]); |
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cpu_stw_kernel(env, env->tr.base + (0x12 + 3 * 2), env->regs[R_EBX]); |
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cpu_stw_kernel(env, env->tr.base + (0x12 + 4 * 2), env->regs[R_ESP]); |
348 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 5 * 2), env->regs[R_EBP]); |
349 |
cpu_stw_kernel(env, env->tr.base + (0x12 + 6 * 2), env->regs[R_ESI]); |
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cpu_stw_kernel(env, env->tr.base + (0x12 + 7 * 2), env->regs[R_EDI]); |
351 |
for (i = 0; i < 4; i++) { |
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cpu_stw_kernel(env, env->tr.base + (0x22 + i * 4), |
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env->segs[i].selector); |
354 |
} |
355 |
} |
356 |
|
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/* now if an exception occurs, it will occurs in the next task
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context */
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359 |
|
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if (source == SWITCH_TSS_CALL) {
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cpu_stw_kernel(env, tss_base, env->tr.selector); |
362 |
new_eflags |= NT_MASK; |
363 |
} |
364 |
|
365 |
/* set busy bit */
|
366 |
if (source == SWITCH_TSS_JMP || source == SWITCH_TSS_CALL) {
|
367 |
target_ulong ptr; |
368 |
uint32_t e2; |
369 |
|
370 |
ptr = env->gdt.base + (tss_selector & ~7);
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e2 = cpu_ldl_kernel(env, ptr + 4);
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e2 |= DESC_TSS_BUSY_MASK; |
373 |
cpu_stl_kernel(env, ptr + 4, e2);
|
374 |
} |
375 |
|
376 |
/* set the new CPU state */
|
377 |
/* from this point, any exception which occurs can give problems */
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env->cr[0] |= CR0_TS_MASK;
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env->hflags |= HF_TS_MASK; |
380 |
env->tr.selector = tss_selector; |
381 |
env->tr.base = tss_base; |
382 |
env->tr.limit = tss_limit; |
383 |
env->tr.flags = e2 & ~DESC_TSS_BUSY_MASK; |
384 |
|
385 |
if ((type & 8) && (env->cr[0] & CR0_PG_MASK)) { |
386 |
cpu_x86_update_cr3(env, new_cr3); |
387 |
} |
388 |
|
389 |
/* load all registers without an exception, then reload them with
|
390 |
possible exception */
|
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env->eip = new_eip; |
392 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | |
393 |
IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | NT_MASK; |
394 |
if (!(type & 8)) { |
395 |
eflags_mask &= 0xffff;
|
396 |
} |
397 |
cpu_load_eflags(env, new_eflags, eflags_mask); |
398 |
/* XXX: what to do in 16 bit case? */
|
399 |
env->regs[R_EAX] = new_regs[0];
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400 |
env->regs[R_ECX] = new_regs[1];
|
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env->regs[R_EDX] = new_regs[2];
|
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env->regs[R_EBX] = new_regs[3];
|
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env->regs[R_ESP] = new_regs[4];
|
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env->regs[R_EBP] = new_regs[5];
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env->regs[R_ESI] = new_regs[6];
|
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env->regs[R_EDI] = new_regs[7];
|
407 |
if (new_eflags & VM_MASK) {
|
408 |
for (i = 0; i < 6; i++) { |
409 |
load_seg_vm(env, i, new_segs[i]); |
410 |
} |
411 |
/* in vm86, CPL is always 3 */
|
412 |
cpu_x86_set_cpl(env, 3);
|
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} else {
|
414 |
/* CPL is set the RPL of CS */
|
415 |
cpu_x86_set_cpl(env, new_segs[R_CS] & 3);
|
416 |
/* first just selectors as the rest may trigger exceptions */
|
417 |
for (i = 0; i < 6; i++) { |
418 |
cpu_x86_load_seg_cache(env, i, new_segs[i], 0, 0, 0); |
419 |
} |
420 |
} |
421 |
|
422 |
env->ldt.selector = new_ldt & ~4;
|
423 |
env->ldt.base = 0;
|
424 |
env->ldt.limit = 0;
|
425 |
env->ldt.flags = 0;
|
426 |
|
427 |
/* load the LDT */
|
428 |
if (new_ldt & 4) { |
429 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
430 |
} |
431 |
|
432 |
if ((new_ldt & 0xfffc) != 0) { |
433 |
dt = &env->gdt; |
434 |
index = new_ldt & ~7;
|
435 |
if ((index + 7) > dt->limit) { |
436 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
437 |
} |
438 |
ptr = dt->base + index; |
439 |
e1 = cpu_ldl_kernel(env, ptr); |
440 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
441 |
if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
442 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
443 |
} |
444 |
if (!(e2 & DESC_P_MASK)) {
|
445 |
raise_exception_err(env, EXCP0A_TSS, new_ldt & 0xfffc);
|
446 |
} |
447 |
load_seg_cache_raw_dt(&env->ldt, e1, e2); |
448 |
} |
449 |
|
450 |
/* load the segments */
|
451 |
if (!(new_eflags & VM_MASK)) {
|
452 |
tss_load_seg(env, R_CS, new_segs[R_CS]); |
453 |
tss_load_seg(env, R_SS, new_segs[R_SS]); |
454 |
tss_load_seg(env, R_ES, new_segs[R_ES]); |
455 |
tss_load_seg(env, R_DS, new_segs[R_DS]); |
456 |
tss_load_seg(env, R_FS, new_segs[R_FS]); |
457 |
tss_load_seg(env, R_GS, new_segs[R_GS]); |
458 |
} |
459 |
|
460 |
/* check that env->eip is in the CS segment limits */
|
461 |
if (new_eip > env->segs[R_CS].limit) {
|
462 |
/* XXX: different exception if CALL? */
|
463 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
464 |
} |
465 |
|
466 |
#ifndef CONFIG_USER_ONLY
|
467 |
/* reset local breakpoints */
|
468 |
if (env->dr[7] & DR7_LOCAL_BP_MASK) { |
469 |
for (i = 0; i < DR7_MAX_BP; i++) { |
470 |
if (hw_local_breakpoint_enabled(env->dr[7], i) && |
471 |
!hw_global_breakpoint_enabled(env->dr[7], i)) {
|
472 |
hw_breakpoint_remove(env, i); |
473 |
} |
474 |
} |
475 |
env->dr[7] &= ~DR7_LOCAL_BP_MASK;
|
476 |
} |
477 |
#endif
|
478 |
} |
479 |
|
480 |
static inline unsigned int get_sp_mask(unsigned int e2) |
481 |
{ |
482 |
if (e2 & DESC_B_MASK) {
|
483 |
return 0xffffffff; |
484 |
} else {
|
485 |
return 0xffff; |
486 |
} |
487 |
} |
488 |
|
489 |
static int exception_has_error_code(int intno) |
490 |
{ |
491 |
switch (intno) {
|
492 |
case 8: |
493 |
case 10: |
494 |
case 11: |
495 |
case 12: |
496 |
case 13: |
497 |
case 14: |
498 |
case 17: |
499 |
return 1; |
500 |
} |
501 |
return 0; |
502 |
} |
503 |
|
504 |
#ifdef TARGET_X86_64
|
505 |
#define SET_ESP(val, sp_mask) \
|
506 |
do { \
|
507 |
if ((sp_mask) == 0xffff) { \ |
508 |
env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | \
|
509 |
((val) & 0xffff); \
|
510 |
} else if ((sp_mask) == 0xffffffffLL) { \ |
511 |
env->regs[R_ESP] = (uint32_t)(val); \ |
512 |
} else { \
|
513 |
env->regs[R_ESP] = (val); \ |
514 |
} \ |
515 |
} while (0) |
516 |
#else
|
517 |
#define SET_ESP(val, sp_mask) \
|
518 |
do { \
|
519 |
env->regs[R_ESP] = (env->regs[R_ESP] & ~(sp_mask)) | \ |
520 |
((val) & (sp_mask)); \ |
521 |
} while (0) |
522 |
#endif
|
523 |
|
524 |
/* in 64-bit machines, this can overflow. So this segment addition macro
|
525 |
* can be used to trim the value to 32-bit whenever needed */
|
526 |
#define SEG_ADDL(ssp, sp, sp_mask) ((uint32_t)((ssp) + (sp & (sp_mask))))
|
527 |
|
528 |
/* XXX: add a is_user flag to have proper security support */
|
529 |
#define PUSHW(ssp, sp, sp_mask, val) \
|
530 |
{ \ |
531 |
sp -= 2; \
|
532 |
cpu_stw_kernel(env, (ssp) + (sp & (sp_mask)), (val)); \ |
533 |
} |
534 |
|
535 |
#define PUSHL(ssp, sp, sp_mask, val) \
|
536 |
{ \ |
537 |
sp -= 4; \
|
538 |
cpu_stl_kernel(env, SEG_ADDL(ssp, sp, sp_mask), (uint32_t)(val)); \ |
539 |
} |
540 |
|
541 |
#define POPW(ssp, sp, sp_mask, val) \
|
542 |
{ \ |
543 |
val = cpu_lduw_kernel(env, (ssp) + (sp & (sp_mask))); \ |
544 |
sp += 2; \
|
545 |
} |
546 |
|
547 |
#define POPL(ssp, sp, sp_mask, val) \
|
548 |
{ \ |
549 |
val = (uint32_t)cpu_ldl_kernel(env, SEG_ADDL(ssp, sp, sp_mask)); \ |
550 |
sp += 4; \
|
551 |
} |
552 |
|
553 |
/* protected mode interrupt */
|
554 |
static void do_interrupt_protected(CPUX86State *env, int intno, int is_int, |
555 |
int error_code, unsigned int next_eip, |
556 |
int is_hw)
|
557 |
{ |
558 |
SegmentCache *dt; |
559 |
target_ulong ptr, ssp; |
560 |
int type, dpl, selector, ss_dpl, cpl;
|
561 |
int has_error_code, new_stack, shift;
|
562 |
uint32_t e1, e2, offset, ss = 0, esp, ss_e1 = 0, ss_e2 = 0; |
563 |
uint32_t old_eip, sp_mask; |
564 |
|
565 |
has_error_code = 0;
|
566 |
if (!is_int && !is_hw) {
|
567 |
has_error_code = exception_has_error_code(intno); |
568 |
} |
569 |
if (is_int) {
|
570 |
old_eip = next_eip; |
571 |
} else {
|
572 |
old_eip = env->eip; |
573 |
} |
574 |
|
575 |
dt = &env->idt; |
576 |
if (intno * 8 + 7 > dt->limit) { |
577 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
578 |
} |
579 |
ptr = dt->base + intno * 8;
|
580 |
e1 = cpu_ldl_kernel(env, ptr); |
581 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
582 |
/* check gate type */
|
583 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
584 |
switch (type) {
|
585 |
case 5: /* task gate */ |
586 |
/* must do that check here to return the correct error code */
|
587 |
if (!(e2 & DESC_P_MASK)) {
|
588 |
raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
589 |
} |
590 |
switch_tss(env, intno * 8, e1, e2, SWITCH_TSS_CALL, old_eip);
|
591 |
if (has_error_code) {
|
592 |
int type;
|
593 |
uint32_t mask; |
594 |
|
595 |
/* push the error code */
|
596 |
type = (env->tr.flags >> DESC_TYPE_SHIFT) & 0xf;
|
597 |
shift = type >> 3;
|
598 |
if (env->segs[R_SS].flags & DESC_B_MASK) {
|
599 |
mask = 0xffffffff;
|
600 |
} else {
|
601 |
mask = 0xffff;
|
602 |
} |
603 |
esp = (env->regs[R_ESP] - (2 << shift)) & mask;
|
604 |
ssp = env->segs[R_SS].base + esp; |
605 |
if (shift) {
|
606 |
cpu_stl_kernel(env, ssp, error_code); |
607 |
} else {
|
608 |
cpu_stw_kernel(env, ssp, error_code); |
609 |
} |
610 |
SET_ESP(esp, mask); |
611 |
} |
612 |
return;
|
613 |
case 6: /* 286 interrupt gate */ |
614 |
case 7: /* 286 trap gate */ |
615 |
case 14: /* 386 interrupt gate */ |
616 |
case 15: /* 386 trap gate */ |
617 |
break;
|
618 |
default:
|
619 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
620 |
break;
|
621 |
} |
622 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
623 |
cpl = env->hflags & HF_CPL_MASK; |
624 |
/* check privilege if software int */
|
625 |
if (is_int && dpl < cpl) {
|
626 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
627 |
} |
628 |
/* check valid bit */
|
629 |
if (!(e2 & DESC_P_MASK)) {
|
630 |
raise_exception_err(env, EXCP0B_NOSEG, intno * 8 + 2); |
631 |
} |
632 |
selector = e1 >> 16;
|
633 |
offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
634 |
if ((selector & 0xfffc) == 0) { |
635 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
636 |
} |
637 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
638 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
639 |
} |
640 |
if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
641 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
642 |
} |
643 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
644 |
if (dpl > cpl) {
|
645 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
646 |
} |
647 |
if (!(e2 & DESC_P_MASK)) {
|
648 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
649 |
} |
650 |
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
|
651 |
/* to inner privilege */
|
652 |
get_ss_esp_from_tss(env, &ss, &esp, dpl); |
653 |
if ((ss & 0xfffc) == 0) { |
654 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
655 |
} |
656 |
if ((ss & 3) != dpl) { |
657 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
658 |
} |
659 |
if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
660 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
661 |
} |
662 |
ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
663 |
if (ss_dpl != dpl) {
|
664 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
665 |
} |
666 |
if (!(ss_e2 & DESC_S_MASK) ||
|
667 |
(ss_e2 & DESC_CS_MASK) || |
668 |
!(ss_e2 & DESC_W_MASK)) { |
669 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
670 |
} |
671 |
if (!(ss_e2 & DESC_P_MASK)) {
|
672 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
673 |
} |
674 |
new_stack = 1;
|
675 |
sp_mask = get_sp_mask(ss_e2); |
676 |
ssp = get_seg_base(ss_e1, ss_e2); |
677 |
} else if ((e2 & DESC_C_MASK) || dpl == cpl) { |
678 |
/* to same privilege */
|
679 |
if (env->eflags & VM_MASK) {
|
680 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
681 |
} |
682 |
new_stack = 0;
|
683 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
684 |
ssp = env->segs[R_SS].base; |
685 |
esp = env->regs[R_ESP]; |
686 |
dpl = cpl; |
687 |
} else {
|
688 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
689 |
new_stack = 0; /* avoid warning */ |
690 |
sp_mask = 0; /* avoid warning */ |
691 |
ssp = 0; /* avoid warning */ |
692 |
esp = 0; /* avoid warning */ |
693 |
} |
694 |
|
695 |
shift = type >> 3;
|
696 |
|
697 |
#if 0
|
698 |
/* XXX: check that enough room is available */
|
699 |
push_size = 6 + (new_stack << 2) + (has_error_code << 1);
|
700 |
if (env->eflags & VM_MASK) {
|
701 |
push_size += 8;
|
702 |
}
|
703 |
push_size <<= shift;
|
704 |
#endif
|
705 |
if (shift == 1) { |
706 |
if (new_stack) {
|
707 |
if (env->eflags & VM_MASK) {
|
708 |
PUSHL(ssp, esp, sp_mask, env->segs[R_GS].selector); |
709 |
PUSHL(ssp, esp, sp_mask, env->segs[R_FS].selector); |
710 |
PUSHL(ssp, esp, sp_mask, env->segs[R_DS].selector); |
711 |
PUSHL(ssp, esp, sp_mask, env->segs[R_ES].selector); |
712 |
} |
713 |
PUSHL(ssp, esp, sp_mask, env->segs[R_SS].selector); |
714 |
PUSHL(ssp, esp, sp_mask, env->regs[R_ESP]); |
715 |
} |
716 |
PUSHL(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
717 |
PUSHL(ssp, esp, sp_mask, env->segs[R_CS].selector); |
718 |
PUSHL(ssp, esp, sp_mask, old_eip); |
719 |
if (has_error_code) {
|
720 |
PUSHL(ssp, esp, sp_mask, error_code); |
721 |
} |
722 |
} else {
|
723 |
if (new_stack) {
|
724 |
if (env->eflags & VM_MASK) {
|
725 |
PUSHW(ssp, esp, sp_mask, env->segs[R_GS].selector); |
726 |
PUSHW(ssp, esp, sp_mask, env->segs[R_FS].selector); |
727 |
PUSHW(ssp, esp, sp_mask, env->segs[R_DS].selector); |
728 |
PUSHW(ssp, esp, sp_mask, env->segs[R_ES].selector); |
729 |
} |
730 |
PUSHW(ssp, esp, sp_mask, env->segs[R_SS].selector); |
731 |
PUSHW(ssp, esp, sp_mask, env->regs[R_ESP]); |
732 |
} |
733 |
PUSHW(ssp, esp, sp_mask, cpu_compute_eflags(env)); |
734 |
PUSHW(ssp, esp, sp_mask, env->segs[R_CS].selector); |
735 |
PUSHW(ssp, esp, sp_mask, old_eip); |
736 |
if (has_error_code) {
|
737 |
PUSHW(ssp, esp, sp_mask, error_code); |
738 |
} |
739 |
} |
740 |
|
741 |
if (new_stack) {
|
742 |
if (env->eflags & VM_MASK) {
|
743 |
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0, 0); |
744 |
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0, 0); |
745 |
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0, 0); |
746 |
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0, 0); |
747 |
} |
748 |
ss = (ss & ~3) | dpl;
|
749 |
cpu_x86_load_seg_cache(env, R_SS, ss, |
750 |
ssp, get_seg_limit(ss_e1, ss_e2), ss_e2); |
751 |
} |
752 |
SET_ESP(esp, sp_mask); |
753 |
|
754 |
selector = (selector & ~3) | dpl;
|
755 |
cpu_x86_load_seg_cache(env, R_CS, selector, |
756 |
get_seg_base(e1, e2), |
757 |
get_seg_limit(e1, e2), |
758 |
e2); |
759 |
cpu_x86_set_cpl(env, dpl); |
760 |
env->eip = offset; |
761 |
|
762 |
/* interrupt gate clear IF mask */
|
763 |
if ((type & 1) == 0) { |
764 |
env->eflags &= ~IF_MASK; |
765 |
} |
766 |
env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); |
767 |
} |
768 |
|
769 |
#ifdef TARGET_X86_64
|
770 |
|
771 |
#define PUSHQ(sp, val) \
|
772 |
{ \ |
773 |
sp -= 8; \
|
774 |
cpu_stq_kernel(env, sp, (val)); \ |
775 |
} |
776 |
|
777 |
#define POPQ(sp, val) \
|
778 |
{ \ |
779 |
val = cpu_ldq_kernel(env, sp); \ |
780 |
sp += 8; \
|
781 |
} |
782 |
|
783 |
static inline target_ulong get_rsp_from_tss(CPUX86State *env, int level) |
784 |
{ |
785 |
int index;
|
786 |
|
787 |
#if 0
|
788 |
printf("TR: base=" TARGET_FMT_lx " limit=%x\n",
|
789 |
env->tr.base, env->tr.limit);
|
790 |
#endif
|
791 |
|
792 |
if (!(env->tr.flags & DESC_P_MASK)) {
|
793 |
cpu_abort(env, "invalid tss");
|
794 |
} |
795 |
index = 8 * level + 4; |
796 |
if ((index + 7) > env->tr.limit) { |
797 |
raise_exception_err(env, EXCP0A_TSS, env->tr.selector & 0xfffc);
|
798 |
} |
799 |
return cpu_ldq_kernel(env, env->tr.base + index);
|
800 |
} |
801 |
|
802 |
/* 64 bit interrupt */
|
803 |
static void do_interrupt64(CPUX86State *env, int intno, int is_int, |
804 |
int error_code, target_ulong next_eip, int is_hw) |
805 |
{ |
806 |
SegmentCache *dt; |
807 |
target_ulong ptr; |
808 |
int type, dpl, selector, cpl, ist;
|
809 |
int has_error_code, new_stack;
|
810 |
uint32_t e1, e2, e3, ss; |
811 |
target_ulong old_eip, esp, offset; |
812 |
|
813 |
has_error_code = 0;
|
814 |
if (!is_int && !is_hw) {
|
815 |
has_error_code = exception_has_error_code(intno); |
816 |
} |
817 |
if (is_int) {
|
818 |
old_eip = next_eip; |
819 |
} else {
|
820 |
old_eip = env->eip; |
821 |
} |
822 |
|
823 |
dt = &env->idt; |
824 |
if (intno * 16 + 15 > dt->limit) { |
825 |
raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
826 |
} |
827 |
ptr = dt->base + intno * 16;
|
828 |
e1 = cpu_ldl_kernel(env, ptr); |
829 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
830 |
e3 = cpu_ldl_kernel(env, ptr + 8);
|
831 |
/* check gate type */
|
832 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
833 |
switch (type) {
|
834 |
case 14: /* 386 interrupt gate */ |
835 |
case 15: /* 386 trap gate */ |
836 |
break;
|
837 |
default:
|
838 |
raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
839 |
break;
|
840 |
} |
841 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
842 |
cpl = env->hflags & HF_CPL_MASK; |
843 |
/* check privilege if software int */
|
844 |
if (is_int && dpl < cpl) {
|
845 |
raise_exception_err(env, EXCP0D_GPF, intno * 16 + 2); |
846 |
} |
847 |
/* check valid bit */
|
848 |
if (!(e2 & DESC_P_MASK)) {
|
849 |
raise_exception_err(env, EXCP0B_NOSEG, intno * 16 + 2); |
850 |
} |
851 |
selector = e1 >> 16;
|
852 |
offset = ((target_ulong)e3 << 32) | (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
853 |
ist = e2 & 7;
|
854 |
if ((selector & 0xfffc) == 0) { |
855 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
856 |
} |
857 |
|
858 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
859 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
860 |
} |
861 |
if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
862 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
863 |
} |
864 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
865 |
if (dpl > cpl) {
|
866 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
867 |
} |
868 |
if (!(e2 & DESC_P_MASK)) {
|
869 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
870 |
} |
871 |
if (!(e2 & DESC_L_MASK) || (e2 & DESC_B_MASK)) {
|
872 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
873 |
} |
874 |
if ((!(e2 & DESC_C_MASK) && dpl < cpl) || ist != 0) { |
875 |
/* to inner privilege */
|
876 |
if (ist != 0) { |
877 |
esp = get_rsp_from_tss(env, ist + 3);
|
878 |
} else {
|
879 |
esp = get_rsp_from_tss(env, dpl); |
880 |
} |
881 |
esp &= ~0xfLL; /* align stack */ |
882 |
ss = 0;
|
883 |
new_stack = 1;
|
884 |
} else if ((e2 & DESC_C_MASK) || dpl == cpl) { |
885 |
/* to same privilege */
|
886 |
if (env->eflags & VM_MASK) {
|
887 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
888 |
} |
889 |
new_stack = 0;
|
890 |
if (ist != 0) { |
891 |
esp = get_rsp_from_tss(env, ist + 3);
|
892 |
} else {
|
893 |
esp = env->regs[R_ESP]; |
894 |
} |
895 |
esp &= ~0xfLL; /* align stack */ |
896 |
dpl = cpl; |
897 |
} else {
|
898 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
899 |
new_stack = 0; /* avoid warning */ |
900 |
esp = 0; /* avoid warning */ |
901 |
} |
902 |
|
903 |
PUSHQ(esp, env->segs[R_SS].selector); |
904 |
PUSHQ(esp, env->regs[R_ESP]); |
905 |
PUSHQ(esp, cpu_compute_eflags(env)); |
906 |
PUSHQ(esp, env->segs[R_CS].selector); |
907 |
PUSHQ(esp, old_eip); |
908 |
if (has_error_code) {
|
909 |
PUSHQ(esp, error_code); |
910 |
} |
911 |
|
912 |
if (new_stack) {
|
913 |
ss = 0 | dpl;
|
914 |
cpu_x86_load_seg_cache(env, R_SS, ss, 0, 0, 0); |
915 |
} |
916 |
env->regs[R_ESP] = esp; |
917 |
|
918 |
selector = (selector & ~3) | dpl;
|
919 |
cpu_x86_load_seg_cache(env, R_CS, selector, |
920 |
get_seg_base(e1, e2), |
921 |
get_seg_limit(e1, e2), |
922 |
e2); |
923 |
cpu_x86_set_cpl(env, dpl); |
924 |
env->eip = offset; |
925 |
|
926 |
/* interrupt gate clear IF mask */
|
927 |
if ((type & 1) == 0) { |
928 |
env->eflags &= ~IF_MASK; |
929 |
} |
930 |
env->eflags &= ~(TF_MASK | VM_MASK | RF_MASK | NT_MASK); |
931 |
} |
932 |
#endif
|
933 |
|
934 |
#ifdef TARGET_X86_64
|
935 |
#if defined(CONFIG_USER_ONLY)
|
936 |
void helper_syscall(CPUX86State *env, int next_eip_addend) |
937 |
{ |
938 |
env->exception_index = EXCP_SYSCALL; |
939 |
env->exception_next_eip = env->eip + next_eip_addend; |
940 |
cpu_loop_exit(env); |
941 |
} |
942 |
#else
|
943 |
void helper_syscall(CPUX86State *env, int next_eip_addend) |
944 |
{ |
945 |
int selector;
|
946 |
|
947 |
if (!(env->efer & MSR_EFER_SCE)) {
|
948 |
raise_exception_err(env, EXCP06_ILLOP, 0);
|
949 |
} |
950 |
selector = (env->star >> 32) & 0xffff; |
951 |
if (env->hflags & HF_LMA_MASK) {
|
952 |
int code64;
|
953 |
|
954 |
env->regs[R_ECX] = env->eip + next_eip_addend; |
955 |
env->regs[11] = cpu_compute_eflags(env);
|
956 |
|
957 |
code64 = env->hflags & HF_CS64_MASK; |
958 |
|
959 |
cpu_x86_set_cpl(env, 0);
|
960 |
cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
961 |
0, 0xffffffff, |
962 |
DESC_G_MASK | DESC_P_MASK | |
963 |
DESC_S_MASK | |
964 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
965 |
DESC_L_MASK); |
966 |
cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
967 |
0, 0xffffffff, |
968 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
969 |
DESC_S_MASK | |
970 |
DESC_W_MASK | DESC_A_MASK); |
971 |
env->eflags &= ~env->fmask; |
972 |
cpu_load_eflags(env, env->eflags, 0);
|
973 |
if (code64) {
|
974 |
env->eip = env->lstar; |
975 |
} else {
|
976 |
env->eip = env->cstar; |
977 |
} |
978 |
} else {
|
979 |
env->regs[R_ECX] = (uint32_t)(env->eip + next_eip_addend); |
980 |
|
981 |
cpu_x86_set_cpl(env, 0);
|
982 |
cpu_x86_load_seg_cache(env, R_CS, selector & 0xfffc,
|
983 |
0, 0xffffffff, |
984 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
985 |
DESC_S_MASK | |
986 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
987 |
cpu_x86_load_seg_cache(env, R_SS, (selector + 8) & 0xfffc, |
988 |
0, 0xffffffff, |
989 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
990 |
DESC_S_MASK | |
991 |
DESC_W_MASK | DESC_A_MASK); |
992 |
env->eflags &= ~(IF_MASK | RF_MASK | VM_MASK); |
993 |
env->eip = (uint32_t)env->star; |
994 |
} |
995 |
} |
996 |
#endif
|
997 |
#endif
|
998 |
|
999 |
#ifdef TARGET_X86_64
|
1000 |
void helper_sysret(CPUX86State *env, int dflag) |
1001 |
{ |
1002 |
int cpl, selector;
|
1003 |
|
1004 |
if (!(env->efer & MSR_EFER_SCE)) {
|
1005 |
raise_exception_err(env, EXCP06_ILLOP, 0);
|
1006 |
} |
1007 |
cpl = env->hflags & HF_CPL_MASK; |
1008 |
if (!(env->cr[0] & CR0_PE_MASK) || cpl != 0) { |
1009 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1010 |
} |
1011 |
selector = (env->star >> 48) & 0xffff; |
1012 |
if (env->hflags & HF_LMA_MASK) {
|
1013 |
if (dflag == 2) { |
1014 |
cpu_x86_load_seg_cache(env, R_CS, (selector + 16) | 3, |
1015 |
0, 0xffffffff, |
1016 |
DESC_G_MASK | DESC_P_MASK | |
1017 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1018 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
1019 |
DESC_L_MASK); |
1020 |
env->eip = env->regs[R_ECX]; |
1021 |
} else {
|
1022 |
cpu_x86_load_seg_cache(env, R_CS, selector | 3,
|
1023 |
0, 0xffffffff, |
1024 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1025 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1026 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
1027 |
env->eip = (uint32_t)env->regs[R_ECX]; |
1028 |
} |
1029 |
cpu_x86_load_seg_cache(env, R_SS, selector + 8,
|
1030 |
0, 0xffffffff, |
1031 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1032 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1033 |
DESC_W_MASK | DESC_A_MASK); |
1034 |
cpu_load_eflags(env, (uint32_t)(env->regs[11]), TF_MASK | AC_MASK
|
1035 |
| ID_MASK | IF_MASK | IOPL_MASK | VM_MASK | RF_MASK | |
1036 |
NT_MASK); |
1037 |
cpu_x86_set_cpl(env, 3);
|
1038 |
} else {
|
1039 |
cpu_x86_load_seg_cache(env, R_CS, selector | 3,
|
1040 |
0, 0xffffffff, |
1041 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1042 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1043 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
1044 |
env->eip = (uint32_t)env->regs[R_ECX]; |
1045 |
cpu_x86_load_seg_cache(env, R_SS, selector + 8,
|
1046 |
0, 0xffffffff, |
1047 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
1048 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
1049 |
DESC_W_MASK | DESC_A_MASK); |
1050 |
env->eflags |= IF_MASK; |
1051 |
cpu_x86_set_cpl(env, 3);
|
1052 |
} |
1053 |
} |
1054 |
#endif
|
1055 |
|
1056 |
/* real mode interrupt */
|
1057 |
static void do_interrupt_real(CPUX86State *env, int intno, int is_int, |
1058 |
int error_code, unsigned int next_eip) |
1059 |
{ |
1060 |
SegmentCache *dt; |
1061 |
target_ulong ptr, ssp; |
1062 |
int selector;
|
1063 |
uint32_t offset, esp; |
1064 |
uint32_t old_cs, old_eip; |
1065 |
|
1066 |
/* real mode (simpler!) */
|
1067 |
dt = &env->idt; |
1068 |
if (intno * 4 + 3 > dt->limit) { |
1069 |
raise_exception_err(env, EXCP0D_GPF, intno * 8 + 2); |
1070 |
} |
1071 |
ptr = dt->base + intno * 4;
|
1072 |
offset = cpu_lduw_kernel(env, ptr); |
1073 |
selector = cpu_lduw_kernel(env, ptr + 2);
|
1074 |
esp = env->regs[R_ESP]; |
1075 |
ssp = env->segs[R_SS].base; |
1076 |
if (is_int) {
|
1077 |
old_eip = next_eip; |
1078 |
} else {
|
1079 |
old_eip = env->eip; |
1080 |
} |
1081 |
old_cs = env->segs[R_CS].selector; |
1082 |
/* XXX: use SS segment size? */
|
1083 |
PUSHW(ssp, esp, 0xffff, cpu_compute_eflags(env));
|
1084 |
PUSHW(ssp, esp, 0xffff, old_cs);
|
1085 |
PUSHW(ssp, esp, 0xffff, old_eip);
|
1086 |
|
1087 |
/* update processor state */
|
1088 |
env->regs[R_ESP] = (env->regs[R_ESP] & ~0xffff) | (esp & 0xffff); |
1089 |
env->eip = offset; |
1090 |
env->segs[R_CS].selector = selector; |
1091 |
env->segs[R_CS].base = (selector << 4);
|
1092 |
env->eflags &= ~(IF_MASK | TF_MASK | AC_MASK | RF_MASK); |
1093 |
} |
1094 |
|
1095 |
#if defined(CONFIG_USER_ONLY)
|
1096 |
/* fake user mode interrupt */
|
1097 |
static void do_interrupt_user(CPUX86State *env, int intno, int is_int, |
1098 |
int error_code, target_ulong next_eip)
|
1099 |
{ |
1100 |
SegmentCache *dt; |
1101 |
target_ulong ptr; |
1102 |
int dpl, cpl, shift;
|
1103 |
uint32_t e2; |
1104 |
|
1105 |
dt = &env->idt; |
1106 |
if (env->hflags & HF_LMA_MASK) {
|
1107 |
shift = 4;
|
1108 |
} else {
|
1109 |
shift = 3;
|
1110 |
} |
1111 |
ptr = dt->base + (intno << shift); |
1112 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1113 |
|
1114 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1115 |
cpl = env->hflags & HF_CPL_MASK; |
1116 |
/* check privilege if software int */
|
1117 |
if (is_int && dpl < cpl) {
|
1118 |
raise_exception_err(env, EXCP0D_GPF, (intno << shift) + 2);
|
1119 |
} |
1120 |
|
1121 |
/* Since we emulate only user space, we cannot do more than
|
1122 |
exiting the emulation with the suitable exception and error
|
1123 |
code */
|
1124 |
if (is_int) {
|
1125 |
env->eip = next_eip; |
1126 |
} |
1127 |
} |
1128 |
|
1129 |
#else
|
1130 |
|
1131 |
static void handle_even_inj(CPUX86State *env, int intno, int is_int, |
1132 |
int error_code, int is_hw, int rm) |
1133 |
{ |
1134 |
CPUState *cs = ENV_GET_CPU(env); |
1135 |
uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + offsetof(struct vmcb,
|
1136 |
control.event_inj)); |
1137 |
|
1138 |
if (!(event_inj & SVM_EVTINJ_VALID)) {
|
1139 |
int type;
|
1140 |
|
1141 |
if (is_int) {
|
1142 |
type = SVM_EVTINJ_TYPE_SOFT; |
1143 |
} else {
|
1144 |
type = SVM_EVTINJ_TYPE_EXEPT; |
1145 |
} |
1146 |
event_inj = intno | type | SVM_EVTINJ_VALID; |
1147 |
if (!rm && exception_has_error_code(intno)) {
|
1148 |
event_inj |= SVM_EVTINJ_VALID_ERR; |
1149 |
stl_phys(env->vm_vmcb + offsetof(struct vmcb,
|
1150 |
control.event_inj_err), |
1151 |
error_code); |
1152 |
} |
1153 |
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
|
1154 |
event_inj); |
1155 |
} |
1156 |
} |
1157 |
#endif
|
1158 |
|
1159 |
/*
|
1160 |
* Begin execution of an interruption. is_int is TRUE if coming from
|
1161 |
* the int instruction. next_eip is the env->eip value AFTER the interrupt
|
1162 |
* instruction. It is only relevant if is_int is TRUE.
|
1163 |
*/
|
1164 |
static void do_interrupt_all(X86CPU *cpu, int intno, int is_int, |
1165 |
int error_code, target_ulong next_eip, int is_hw) |
1166 |
{ |
1167 |
CPUX86State *env = &cpu->env; |
1168 |
|
1169 |
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
1170 |
if ((env->cr[0] & CR0_PE_MASK)) { |
1171 |
static int count; |
1172 |
|
1173 |
qemu_log("%6d: v=%02x e=%04x i=%d cpl=%d IP=%04x:" TARGET_FMT_lx
|
1174 |
" pc=" TARGET_FMT_lx " SP=%04x:" TARGET_FMT_lx, |
1175 |
count, intno, error_code, is_int, |
1176 |
env->hflags & HF_CPL_MASK, |
1177 |
env->segs[R_CS].selector, env->eip, |
1178 |
(int)env->segs[R_CS].base + env->eip,
|
1179 |
env->segs[R_SS].selector, env->regs[R_ESP]); |
1180 |
if (intno == 0x0e) { |
1181 |
qemu_log(" CR2=" TARGET_FMT_lx, env->cr[2]); |
1182 |
} else {
|
1183 |
qemu_log(" env->regs[R_EAX]=" TARGET_FMT_lx, env->regs[R_EAX]);
|
1184 |
} |
1185 |
qemu_log("\n");
|
1186 |
log_cpu_state(CPU(cpu), CPU_DUMP_CCOP); |
1187 |
#if 0
|
1188 |
{
|
1189 |
int i;
|
1190 |
target_ulong ptr;
|
1191 |
|
1192 |
qemu_log(" code=");
|
1193 |
ptr = env->segs[R_CS].base + env->eip;
|
1194 |
for (i = 0; i < 16; i++) {
|
1195 |
qemu_log(" %02x", ldub(ptr + i));
|
1196 |
}
|
1197 |
qemu_log("\n");
|
1198 |
}
|
1199 |
#endif
|
1200 |
count++; |
1201 |
} |
1202 |
} |
1203 |
if (env->cr[0] & CR0_PE_MASK) { |
1204 |
#if !defined(CONFIG_USER_ONLY)
|
1205 |
if (env->hflags & HF_SVMI_MASK) {
|
1206 |
handle_even_inj(env, intno, is_int, error_code, is_hw, 0);
|
1207 |
} |
1208 |
#endif
|
1209 |
#ifdef TARGET_X86_64
|
1210 |
if (env->hflags & HF_LMA_MASK) {
|
1211 |
do_interrupt64(env, intno, is_int, error_code, next_eip, is_hw); |
1212 |
} else
|
1213 |
#endif
|
1214 |
{ |
1215 |
do_interrupt_protected(env, intno, is_int, error_code, next_eip, |
1216 |
is_hw); |
1217 |
} |
1218 |
} else {
|
1219 |
#if !defined(CONFIG_USER_ONLY)
|
1220 |
if (env->hflags & HF_SVMI_MASK) {
|
1221 |
handle_even_inj(env, intno, is_int, error_code, is_hw, 1);
|
1222 |
} |
1223 |
#endif
|
1224 |
do_interrupt_real(env, intno, is_int, error_code, next_eip); |
1225 |
} |
1226 |
|
1227 |
#if !defined(CONFIG_USER_ONLY)
|
1228 |
if (env->hflags & HF_SVMI_MASK) {
|
1229 |
CPUState *cs = CPU(cpu); |
1230 |
uint32_t event_inj = ldl_phys(cs->as, env->vm_vmcb + |
1231 |
offsetof(struct vmcb,
|
1232 |
control.event_inj)); |
1233 |
|
1234 |
stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.event_inj),
|
1235 |
event_inj & ~SVM_EVTINJ_VALID); |
1236 |
} |
1237 |
#endif
|
1238 |
} |
1239 |
|
1240 |
void x86_cpu_do_interrupt(CPUState *cs)
|
1241 |
{ |
1242 |
X86CPU *cpu = X86_CPU(cs); |
1243 |
CPUX86State *env = &cpu->env; |
1244 |
|
1245 |
#if defined(CONFIG_USER_ONLY)
|
1246 |
/* if user mode only, we simulate a fake exception
|
1247 |
which will be handled outside the cpu execution
|
1248 |
loop */
|
1249 |
do_interrupt_user(env, env->exception_index, |
1250 |
env->exception_is_int, |
1251 |
env->error_code, |
1252 |
env->exception_next_eip); |
1253 |
/* successfully delivered */
|
1254 |
env->old_exception = -1;
|
1255 |
#else
|
1256 |
/* simulate a real cpu exception. On i386, it can
|
1257 |
trigger new exceptions, but we do not handle
|
1258 |
double or triple faults yet. */
|
1259 |
do_interrupt_all(cpu, env->exception_index, |
1260 |
env->exception_is_int, |
1261 |
env->error_code, |
1262 |
env->exception_next_eip, 0);
|
1263 |
/* successfully delivered */
|
1264 |
env->old_exception = -1;
|
1265 |
#endif
|
1266 |
} |
1267 |
|
1268 |
void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) |
1269 |
{ |
1270 |
do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw); |
1271 |
} |
1272 |
|
1273 |
void helper_enter_level(CPUX86State *env, int level, int data32, |
1274 |
target_ulong t1) |
1275 |
{ |
1276 |
target_ulong ssp; |
1277 |
uint32_t esp_mask, esp, ebp; |
1278 |
|
1279 |
esp_mask = get_sp_mask(env->segs[R_SS].flags); |
1280 |
ssp = env->segs[R_SS].base; |
1281 |
ebp = env->regs[R_EBP]; |
1282 |
esp = env->regs[R_ESP]; |
1283 |
if (data32) {
|
1284 |
/* 32 bit */
|
1285 |
esp -= 4;
|
1286 |
while (--level) {
|
1287 |
esp -= 4;
|
1288 |
ebp -= 4;
|
1289 |
cpu_stl_data(env, ssp + (esp & esp_mask), |
1290 |
cpu_ldl_data(env, ssp + (ebp & esp_mask))); |
1291 |
} |
1292 |
esp -= 4;
|
1293 |
cpu_stl_data(env, ssp + (esp & esp_mask), t1); |
1294 |
} else {
|
1295 |
/* 16 bit */
|
1296 |
esp -= 2;
|
1297 |
while (--level) {
|
1298 |
esp -= 2;
|
1299 |
ebp -= 2;
|
1300 |
cpu_stw_data(env, ssp + (esp & esp_mask), |
1301 |
cpu_lduw_data(env, ssp + (ebp & esp_mask))); |
1302 |
} |
1303 |
esp -= 2;
|
1304 |
cpu_stw_data(env, ssp + (esp & esp_mask), t1); |
1305 |
} |
1306 |
} |
1307 |
|
1308 |
#ifdef TARGET_X86_64
|
1309 |
void helper_enter64_level(CPUX86State *env, int level, int data64, |
1310 |
target_ulong t1) |
1311 |
{ |
1312 |
target_ulong esp, ebp; |
1313 |
|
1314 |
ebp = env->regs[R_EBP]; |
1315 |
esp = env->regs[R_ESP]; |
1316 |
|
1317 |
if (data64) {
|
1318 |
/* 64 bit */
|
1319 |
esp -= 8;
|
1320 |
while (--level) {
|
1321 |
esp -= 8;
|
1322 |
ebp -= 8;
|
1323 |
cpu_stq_data(env, esp, cpu_ldq_data(env, ebp)); |
1324 |
} |
1325 |
esp -= 8;
|
1326 |
cpu_stq_data(env, esp, t1); |
1327 |
} else {
|
1328 |
/* 16 bit */
|
1329 |
esp -= 2;
|
1330 |
while (--level) {
|
1331 |
esp -= 2;
|
1332 |
ebp -= 2;
|
1333 |
cpu_stw_data(env, esp, cpu_lduw_data(env, ebp)); |
1334 |
} |
1335 |
esp -= 2;
|
1336 |
cpu_stw_data(env, esp, t1); |
1337 |
} |
1338 |
} |
1339 |
#endif
|
1340 |
|
1341 |
void helper_lldt(CPUX86State *env, int selector) |
1342 |
{ |
1343 |
SegmentCache *dt; |
1344 |
uint32_t e1, e2; |
1345 |
int index, entry_limit;
|
1346 |
target_ulong ptr; |
1347 |
|
1348 |
selector &= 0xffff;
|
1349 |
if ((selector & 0xfffc) == 0) { |
1350 |
/* XXX: NULL selector case: invalid LDT */
|
1351 |
env->ldt.base = 0;
|
1352 |
env->ldt.limit = 0;
|
1353 |
} else {
|
1354 |
if (selector & 0x4) { |
1355 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1356 |
} |
1357 |
dt = &env->gdt; |
1358 |
index = selector & ~7;
|
1359 |
#ifdef TARGET_X86_64
|
1360 |
if (env->hflags & HF_LMA_MASK) {
|
1361 |
entry_limit = 15;
|
1362 |
} else
|
1363 |
#endif
|
1364 |
{ |
1365 |
entry_limit = 7;
|
1366 |
} |
1367 |
if ((index + entry_limit) > dt->limit) {
|
1368 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1369 |
} |
1370 |
ptr = dt->base + index; |
1371 |
e1 = cpu_ldl_kernel(env, ptr); |
1372 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1373 |
if ((e2 & DESC_S_MASK) || ((e2 >> DESC_TYPE_SHIFT) & 0xf) != 2) { |
1374 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1375 |
} |
1376 |
if (!(e2 & DESC_P_MASK)) {
|
1377 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1378 |
} |
1379 |
#ifdef TARGET_X86_64
|
1380 |
if (env->hflags & HF_LMA_MASK) {
|
1381 |
uint32_t e3; |
1382 |
|
1383 |
e3 = cpu_ldl_kernel(env, ptr + 8);
|
1384 |
load_seg_cache_raw_dt(&env->ldt, e1, e2); |
1385 |
env->ldt.base |= (target_ulong)e3 << 32;
|
1386 |
} else
|
1387 |
#endif
|
1388 |
{ |
1389 |
load_seg_cache_raw_dt(&env->ldt, e1, e2); |
1390 |
} |
1391 |
} |
1392 |
env->ldt.selector = selector; |
1393 |
} |
1394 |
|
1395 |
void helper_ltr(CPUX86State *env, int selector) |
1396 |
{ |
1397 |
SegmentCache *dt; |
1398 |
uint32_t e1, e2; |
1399 |
int index, type, entry_limit;
|
1400 |
target_ulong ptr; |
1401 |
|
1402 |
selector &= 0xffff;
|
1403 |
if ((selector & 0xfffc) == 0) { |
1404 |
/* NULL selector case: invalid TR */
|
1405 |
env->tr.base = 0;
|
1406 |
env->tr.limit = 0;
|
1407 |
env->tr.flags = 0;
|
1408 |
} else {
|
1409 |
if (selector & 0x4) { |
1410 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1411 |
} |
1412 |
dt = &env->gdt; |
1413 |
index = selector & ~7;
|
1414 |
#ifdef TARGET_X86_64
|
1415 |
if (env->hflags & HF_LMA_MASK) {
|
1416 |
entry_limit = 15;
|
1417 |
} else
|
1418 |
#endif
|
1419 |
{ |
1420 |
entry_limit = 7;
|
1421 |
} |
1422 |
if ((index + entry_limit) > dt->limit) {
|
1423 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1424 |
} |
1425 |
ptr = dt->base + index; |
1426 |
e1 = cpu_ldl_kernel(env, ptr); |
1427 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1428 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
1429 |
if ((e2 & DESC_S_MASK) ||
|
1430 |
(type != 1 && type != 9)) { |
1431 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1432 |
} |
1433 |
if (!(e2 & DESC_P_MASK)) {
|
1434 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1435 |
} |
1436 |
#ifdef TARGET_X86_64
|
1437 |
if (env->hflags & HF_LMA_MASK) {
|
1438 |
uint32_t e3, e4; |
1439 |
|
1440 |
e3 = cpu_ldl_kernel(env, ptr + 8);
|
1441 |
e4 = cpu_ldl_kernel(env, ptr + 12);
|
1442 |
if ((e4 >> DESC_TYPE_SHIFT) & 0xf) { |
1443 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1444 |
} |
1445 |
load_seg_cache_raw_dt(&env->tr, e1, e2); |
1446 |
env->tr.base |= (target_ulong)e3 << 32;
|
1447 |
} else
|
1448 |
#endif
|
1449 |
{ |
1450 |
load_seg_cache_raw_dt(&env->tr, e1, e2); |
1451 |
} |
1452 |
e2 |= DESC_TSS_BUSY_MASK; |
1453 |
cpu_stl_kernel(env, ptr + 4, e2);
|
1454 |
} |
1455 |
env->tr.selector = selector; |
1456 |
} |
1457 |
|
1458 |
/* only works if protected mode and not VM86. seg_reg must be != R_CS */
|
1459 |
void helper_load_seg(CPUX86State *env, int seg_reg, int selector) |
1460 |
{ |
1461 |
uint32_t e1, e2; |
1462 |
int cpl, dpl, rpl;
|
1463 |
SegmentCache *dt; |
1464 |
int index;
|
1465 |
target_ulong ptr; |
1466 |
|
1467 |
selector &= 0xffff;
|
1468 |
cpl = env->hflags & HF_CPL_MASK; |
1469 |
if ((selector & 0xfffc) == 0) { |
1470 |
/* null selector case */
|
1471 |
if (seg_reg == R_SS
|
1472 |
#ifdef TARGET_X86_64
|
1473 |
&& (!(env->hflags & HF_CS64_MASK) || cpl == 3)
|
1474 |
#endif
|
1475 |
) { |
1476 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1477 |
} |
1478 |
cpu_x86_load_seg_cache(env, seg_reg, selector, 0, 0, 0); |
1479 |
} else {
|
1480 |
|
1481 |
if (selector & 0x4) { |
1482 |
dt = &env->ldt; |
1483 |
} else {
|
1484 |
dt = &env->gdt; |
1485 |
} |
1486 |
index = selector & ~7;
|
1487 |
if ((index + 7) > dt->limit) { |
1488 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1489 |
} |
1490 |
ptr = dt->base + index; |
1491 |
e1 = cpu_ldl_kernel(env, ptr); |
1492 |
e2 = cpu_ldl_kernel(env, ptr + 4);
|
1493 |
|
1494 |
if (!(e2 & DESC_S_MASK)) {
|
1495 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1496 |
} |
1497 |
rpl = selector & 3;
|
1498 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1499 |
if (seg_reg == R_SS) {
|
1500 |
/* must be writable segment */
|
1501 |
if ((e2 & DESC_CS_MASK) || !(e2 & DESC_W_MASK)) {
|
1502 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1503 |
} |
1504 |
if (rpl != cpl || dpl != cpl) {
|
1505 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1506 |
} |
1507 |
} else {
|
1508 |
/* must be readable segment */
|
1509 |
if ((e2 & (DESC_CS_MASK | DESC_R_MASK)) == DESC_CS_MASK) {
|
1510 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1511 |
} |
1512 |
|
1513 |
if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
|
1514 |
/* if not conforming code, test rights */
|
1515 |
if (dpl < cpl || dpl < rpl) {
|
1516 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1517 |
} |
1518 |
} |
1519 |
} |
1520 |
|
1521 |
if (!(e2 & DESC_P_MASK)) {
|
1522 |
if (seg_reg == R_SS) {
|
1523 |
raise_exception_err(env, EXCP0C_STACK, selector & 0xfffc);
|
1524 |
} else {
|
1525 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1526 |
} |
1527 |
} |
1528 |
|
1529 |
/* set the access bit if not already set */
|
1530 |
if (!(e2 & DESC_A_MASK)) {
|
1531 |
e2 |= DESC_A_MASK; |
1532 |
cpu_stl_kernel(env, ptr + 4, e2);
|
1533 |
} |
1534 |
|
1535 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
1536 |
get_seg_base(e1, e2), |
1537 |
get_seg_limit(e1, e2), |
1538 |
e2); |
1539 |
#if 0
|
1540 |
qemu_log("load_seg: sel=0x%04x base=0x%08lx limit=0x%08lx flags=%08x\n",
|
1541 |
selector, (unsigned long)sc->base, sc->limit, sc->flags);
|
1542 |
#endif
|
1543 |
} |
1544 |
} |
1545 |
|
1546 |
/* protected mode jump */
|
1547 |
void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
1548 |
int next_eip_addend)
|
1549 |
{ |
1550 |
int gate_cs, type;
|
1551 |
uint32_t e1, e2, cpl, dpl, rpl, limit; |
1552 |
target_ulong next_eip; |
1553 |
|
1554 |
if ((new_cs & 0xfffc) == 0) { |
1555 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1556 |
} |
1557 |
if (load_segment(env, &e1, &e2, new_cs) != 0) { |
1558 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1559 |
} |
1560 |
cpl = env->hflags & HF_CPL_MASK; |
1561 |
if (e2 & DESC_S_MASK) {
|
1562 |
if (!(e2 & DESC_CS_MASK)) {
|
1563 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1564 |
} |
1565 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1566 |
if (e2 & DESC_C_MASK) {
|
1567 |
/* conforming code segment */
|
1568 |
if (dpl > cpl) {
|
1569 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1570 |
} |
1571 |
} else {
|
1572 |
/* non conforming code segment */
|
1573 |
rpl = new_cs & 3;
|
1574 |
if (rpl > cpl) {
|
1575 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1576 |
} |
1577 |
if (dpl != cpl) {
|
1578 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1579 |
} |
1580 |
} |
1581 |
if (!(e2 & DESC_P_MASK)) {
|
1582 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1583 |
} |
1584 |
limit = get_seg_limit(e1, e2); |
1585 |
if (new_eip > limit &&
|
1586 |
!(env->hflags & HF_LMA_MASK) && !(e2 & DESC_L_MASK)) { |
1587 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1588 |
} |
1589 |
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
1590 |
get_seg_base(e1, e2), limit, e2); |
1591 |
env->eip = new_eip; |
1592 |
} else {
|
1593 |
/* jump to call or task gate */
|
1594 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1595 |
rpl = new_cs & 3;
|
1596 |
cpl = env->hflags & HF_CPL_MASK; |
1597 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
1598 |
switch (type) {
|
1599 |
case 1: /* 286 TSS */ |
1600 |
case 9: /* 386 TSS */ |
1601 |
case 5: /* task gate */ |
1602 |
if (dpl < cpl || dpl < rpl) {
|
1603 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1604 |
} |
1605 |
next_eip = env->eip + next_eip_addend; |
1606 |
switch_tss(env, new_cs, e1, e2, SWITCH_TSS_JMP, next_eip); |
1607 |
CC_OP = CC_OP_EFLAGS; |
1608 |
break;
|
1609 |
case 4: /* 286 call gate */ |
1610 |
case 12: /* 386 call gate */ |
1611 |
if ((dpl < cpl) || (dpl < rpl)) {
|
1612 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1613 |
} |
1614 |
if (!(e2 & DESC_P_MASK)) {
|
1615 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1616 |
} |
1617 |
gate_cs = e1 >> 16;
|
1618 |
new_eip = (e1 & 0xffff);
|
1619 |
if (type == 12) { |
1620 |
new_eip |= (e2 & 0xffff0000);
|
1621 |
} |
1622 |
if (load_segment(env, &e1, &e2, gate_cs) != 0) { |
1623 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1624 |
} |
1625 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1626 |
/* must be code segment */
|
1627 |
if (((e2 & (DESC_S_MASK | DESC_CS_MASK)) !=
|
1628 |
(DESC_S_MASK | DESC_CS_MASK))) { |
1629 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1630 |
} |
1631 |
if (((e2 & DESC_C_MASK) && (dpl > cpl)) ||
|
1632 |
(!(e2 & DESC_C_MASK) && (dpl != cpl))) { |
1633 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1634 |
} |
1635 |
if (!(e2 & DESC_P_MASK)) {
|
1636 |
raise_exception_err(env, EXCP0D_GPF, gate_cs & 0xfffc);
|
1637 |
} |
1638 |
limit = get_seg_limit(e1, e2); |
1639 |
if (new_eip > limit) {
|
1640 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1641 |
} |
1642 |
cpu_x86_load_seg_cache(env, R_CS, (gate_cs & 0xfffc) | cpl,
|
1643 |
get_seg_base(e1, e2), limit, e2); |
1644 |
env->eip = new_eip; |
1645 |
break;
|
1646 |
default:
|
1647 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1648 |
break;
|
1649 |
} |
1650 |
} |
1651 |
} |
1652 |
|
1653 |
/* real mode call */
|
1654 |
void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1, |
1655 |
int shift, int next_eip) |
1656 |
{ |
1657 |
int new_eip;
|
1658 |
uint32_t esp, esp_mask; |
1659 |
target_ulong ssp; |
1660 |
|
1661 |
new_eip = new_eip1; |
1662 |
esp = env->regs[R_ESP]; |
1663 |
esp_mask = get_sp_mask(env->segs[R_SS].flags); |
1664 |
ssp = env->segs[R_SS].base; |
1665 |
if (shift) {
|
1666 |
PUSHL(ssp, esp, esp_mask, env->segs[R_CS].selector); |
1667 |
PUSHL(ssp, esp, esp_mask, next_eip); |
1668 |
} else {
|
1669 |
PUSHW(ssp, esp, esp_mask, env->segs[R_CS].selector); |
1670 |
PUSHW(ssp, esp, esp_mask, next_eip); |
1671 |
} |
1672 |
|
1673 |
SET_ESP(esp, esp_mask); |
1674 |
env->eip = new_eip; |
1675 |
env->segs[R_CS].selector = new_cs; |
1676 |
env->segs[R_CS].base = (new_cs << 4);
|
1677 |
} |
1678 |
|
1679 |
/* protected mode call */
|
1680 |
void helper_lcall_protected(CPUX86State *env, int new_cs, target_ulong new_eip, |
1681 |
int shift, int next_eip_addend) |
1682 |
{ |
1683 |
int new_stack, i;
|
1684 |
uint32_t e1, e2, cpl, dpl, rpl, selector, offset, param_count; |
1685 |
uint32_t ss = 0, ss_e1 = 0, ss_e2 = 0, sp, type, ss_dpl, sp_mask; |
1686 |
uint32_t val, limit, old_sp_mask; |
1687 |
target_ulong ssp, old_ssp, next_eip; |
1688 |
|
1689 |
next_eip = env->eip + next_eip_addend; |
1690 |
LOG_PCALL("lcall %04x:%08x s=%d\n", new_cs, (uint32_t)new_eip, shift);
|
1691 |
LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); |
1692 |
if ((new_cs & 0xfffc) == 0) { |
1693 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1694 |
} |
1695 |
if (load_segment(env, &e1, &e2, new_cs) != 0) { |
1696 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1697 |
} |
1698 |
cpl = env->hflags & HF_CPL_MASK; |
1699 |
LOG_PCALL("desc=%08x:%08x\n", e1, e2);
|
1700 |
if (e2 & DESC_S_MASK) {
|
1701 |
if (!(e2 & DESC_CS_MASK)) {
|
1702 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1703 |
} |
1704 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1705 |
if (e2 & DESC_C_MASK) {
|
1706 |
/* conforming code segment */
|
1707 |
if (dpl > cpl) {
|
1708 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1709 |
} |
1710 |
} else {
|
1711 |
/* non conforming code segment */
|
1712 |
rpl = new_cs & 3;
|
1713 |
if (rpl > cpl) {
|
1714 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1715 |
} |
1716 |
if (dpl != cpl) {
|
1717 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1718 |
} |
1719 |
} |
1720 |
if (!(e2 & DESC_P_MASK)) {
|
1721 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1722 |
} |
1723 |
|
1724 |
#ifdef TARGET_X86_64
|
1725 |
/* XXX: check 16/32 bit cases in long mode */
|
1726 |
if (shift == 2) { |
1727 |
target_ulong rsp; |
1728 |
|
1729 |
/* 64 bit case */
|
1730 |
rsp = env->regs[R_ESP]; |
1731 |
PUSHQ(rsp, env->segs[R_CS].selector); |
1732 |
PUSHQ(rsp, next_eip); |
1733 |
/* from this point, not restartable */
|
1734 |
env->regs[R_ESP] = rsp; |
1735 |
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
1736 |
get_seg_base(e1, e2), |
1737 |
get_seg_limit(e1, e2), e2); |
1738 |
env->eip = new_eip; |
1739 |
} else
|
1740 |
#endif
|
1741 |
{ |
1742 |
sp = env->regs[R_ESP]; |
1743 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1744 |
ssp = env->segs[R_SS].base; |
1745 |
if (shift) {
|
1746 |
PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1747 |
PUSHL(ssp, sp, sp_mask, next_eip); |
1748 |
} else {
|
1749 |
PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1750 |
PUSHW(ssp, sp, sp_mask, next_eip); |
1751 |
} |
1752 |
|
1753 |
limit = get_seg_limit(e1, e2); |
1754 |
if (new_eip > limit) {
|
1755 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1756 |
} |
1757 |
/* from this point, not restartable */
|
1758 |
SET_ESP(sp, sp_mask); |
1759 |
cpu_x86_load_seg_cache(env, R_CS, (new_cs & 0xfffc) | cpl,
|
1760 |
get_seg_base(e1, e2), limit, e2); |
1761 |
env->eip = new_eip; |
1762 |
} |
1763 |
} else {
|
1764 |
/* check gate type */
|
1765 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x1f;
|
1766 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1767 |
rpl = new_cs & 3;
|
1768 |
switch (type) {
|
1769 |
case 1: /* available 286 TSS */ |
1770 |
case 9: /* available 386 TSS */ |
1771 |
case 5: /* task gate */ |
1772 |
if (dpl < cpl || dpl < rpl) {
|
1773 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1774 |
} |
1775 |
switch_tss(env, new_cs, e1, e2, SWITCH_TSS_CALL, next_eip); |
1776 |
CC_OP = CC_OP_EFLAGS; |
1777 |
return;
|
1778 |
case 4: /* 286 call gate */ |
1779 |
case 12: /* 386 call gate */ |
1780 |
break;
|
1781 |
default:
|
1782 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1783 |
break;
|
1784 |
} |
1785 |
shift = type >> 3;
|
1786 |
|
1787 |
if (dpl < cpl || dpl < rpl) {
|
1788 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
1789 |
} |
1790 |
/* check valid bit */
|
1791 |
if (!(e2 & DESC_P_MASK)) {
|
1792 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
1793 |
} |
1794 |
selector = e1 >> 16;
|
1795 |
offset = (e2 & 0xffff0000) | (e1 & 0x0000ffff); |
1796 |
param_count = e2 & 0x1f;
|
1797 |
if ((selector & 0xfffc) == 0) { |
1798 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
1799 |
} |
1800 |
|
1801 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
1802 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1803 |
} |
1804 |
if (!(e2 & DESC_S_MASK) || !(e2 & (DESC_CS_MASK))) {
|
1805 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1806 |
} |
1807 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1808 |
if (dpl > cpl) {
|
1809 |
raise_exception_err(env, EXCP0D_GPF, selector & 0xfffc);
|
1810 |
} |
1811 |
if (!(e2 & DESC_P_MASK)) {
|
1812 |
raise_exception_err(env, EXCP0B_NOSEG, selector & 0xfffc);
|
1813 |
} |
1814 |
|
1815 |
if (!(e2 & DESC_C_MASK) && dpl < cpl) {
|
1816 |
/* to inner privilege */
|
1817 |
get_ss_esp_from_tss(env, &ss, &sp, dpl); |
1818 |
LOG_PCALL("new ss:esp=%04x:%08x param_count=%d env->regs[R_ESP]="
|
1819 |
TARGET_FMT_lx "\n", ss, sp, param_count,
|
1820 |
env->regs[R_ESP]); |
1821 |
if ((ss & 0xfffc) == 0) { |
1822 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1823 |
} |
1824 |
if ((ss & 3) != dpl) { |
1825 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1826 |
} |
1827 |
if (load_segment(env, &ss_e1, &ss_e2, ss) != 0) { |
1828 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1829 |
} |
1830 |
ss_dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
1831 |
if (ss_dpl != dpl) {
|
1832 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1833 |
} |
1834 |
if (!(ss_e2 & DESC_S_MASK) ||
|
1835 |
(ss_e2 & DESC_CS_MASK) || |
1836 |
!(ss_e2 & DESC_W_MASK)) { |
1837 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1838 |
} |
1839 |
if (!(ss_e2 & DESC_P_MASK)) {
|
1840 |
raise_exception_err(env, EXCP0A_TSS, ss & 0xfffc);
|
1841 |
} |
1842 |
|
1843 |
/* push_size = ((param_count * 2) + 8) << shift; */
|
1844 |
|
1845 |
old_sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1846 |
old_ssp = env->segs[R_SS].base; |
1847 |
|
1848 |
sp_mask = get_sp_mask(ss_e2); |
1849 |
ssp = get_seg_base(ss_e1, ss_e2); |
1850 |
if (shift) {
|
1851 |
PUSHL(ssp, sp, sp_mask, env->segs[R_SS].selector); |
1852 |
PUSHL(ssp, sp, sp_mask, env->regs[R_ESP]); |
1853 |
for (i = param_count - 1; i >= 0; i--) { |
1854 |
val = cpu_ldl_kernel(env, old_ssp + |
1855 |
((env->regs[R_ESP] + i * 4) &
|
1856 |
old_sp_mask)); |
1857 |
PUSHL(ssp, sp, sp_mask, val); |
1858 |
} |
1859 |
} else {
|
1860 |
PUSHW(ssp, sp, sp_mask, env->segs[R_SS].selector); |
1861 |
PUSHW(ssp, sp, sp_mask, env->regs[R_ESP]); |
1862 |
for (i = param_count - 1; i >= 0; i--) { |
1863 |
val = cpu_lduw_kernel(env, old_ssp + |
1864 |
((env->regs[R_ESP] + i * 2) &
|
1865 |
old_sp_mask)); |
1866 |
PUSHW(ssp, sp, sp_mask, val); |
1867 |
} |
1868 |
} |
1869 |
new_stack = 1;
|
1870 |
} else {
|
1871 |
/* to same privilege */
|
1872 |
sp = env->regs[R_ESP]; |
1873 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1874 |
ssp = env->segs[R_SS].base; |
1875 |
/* push_size = (4 << shift); */
|
1876 |
new_stack = 0;
|
1877 |
} |
1878 |
|
1879 |
if (shift) {
|
1880 |
PUSHL(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1881 |
PUSHL(ssp, sp, sp_mask, next_eip); |
1882 |
} else {
|
1883 |
PUSHW(ssp, sp, sp_mask, env->segs[R_CS].selector); |
1884 |
PUSHW(ssp, sp, sp_mask, next_eip); |
1885 |
} |
1886 |
|
1887 |
/* from this point, not restartable */
|
1888 |
|
1889 |
if (new_stack) {
|
1890 |
ss = (ss & ~3) | dpl;
|
1891 |
cpu_x86_load_seg_cache(env, R_SS, ss, |
1892 |
ssp, |
1893 |
get_seg_limit(ss_e1, ss_e2), |
1894 |
ss_e2); |
1895 |
} |
1896 |
|
1897 |
selector = (selector & ~3) | dpl;
|
1898 |
cpu_x86_load_seg_cache(env, R_CS, selector, |
1899 |
get_seg_base(e1, e2), |
1900 |
get_seg_limit(e1, e2), |
1901 |
e2); |
1902 |
cpu_x86_set_cpl(env, dpl); |
1903 |
SET_ESP(sp, sp_mask); |
1904 |
env->eip = offset; |
1905 |
} |
1906 |
} |
1907 |
|
1908 |
/* real and vm86 mode iret */
|
1909 |
void helper_iret_real(CPUX86State *env, int shift) |
1910 |
{ |
1911 |
uint32_t sp, new_cs, new_eip, new_eflags, sp_mask; |
1912 |
target_ulong ssp; |
1913 |
int eflags_mask;
|
1914 |
|
1915 |
sp_mask = 0xffff; /* XXXX: use SS segment size? */ |
1916 |
sp = env->regs[R_ESP]; |
1917 |
ssp = env->segs[R_SS].base; |
1918 |
if (shift == 1) { |
1919 |
/* 32 bits */
|
1920 |
POPL(ssp, sp, sp_mask, new_eip); |
1921 |
POPL(ssp, sp, sp_mask, new_cs); |
1922 |
new_cs &= 0xffff;
|
1923 |
POPL(ssp, sp, sp_mask, new_eflags); |
1924 |
} else {
|
1925 |
/* 16 bits */
|
1926 |
POPW(ssp, sp, sp_mask, new_eip); |
1927 |
POPW(ssp, sp, sp_mask, new_cs); |
1928 |
POPW(ssp, sp, sp_mask, new_eflags); |
1929 |
} |
1930 |
env->regs[R_ESP] = (env->regs[R_ESP] & ~sp_mask) | (sp & sp_mask); |
1931 |
env->segs[R_CS].selector = new_cs; |
1932 |
env->segs[R_CS].base = (new_cs << 4);
|
1933 |
env->eip = new_eip; |
1934 |
if (env->eflags & VM_MASK) {
|
1935 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | RF_MASK | |
1936 |
NT_MASK; |
1937 |
} else {
|
1938 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | IF_MASK | IOPL_MASK | |
1939 |
RF_MASK | NT_MASK; |
1940 |
} |
1941 |
if (shift == 0) { |
1942 |
eflags_mask &= 0xffff;
|
1943 |
} |
1944 |
cpu_load_eflags(env, new_eflags, eflags_mask); |
1945 |
env->hflags2 &= ~HF2_NMI_MASK; |
1946 |
} |
1947 |
|
1948 |
static inline void validate_seg(CPUX86State *env, int seg_reg, int cpl) |
1949 |
{ |
1950 |
int dpl;
|
1951 |
uint32_t e2; |
1952 |
|
1953 |
/* XXX: on x86_64, we do not want to nullify FS and GS because
|
1954 |
they may still contain a valid base. I would be interested to
|
1955 |
know how a real x86_64 CPU behaves */
|
1956 |
if ((seg_reg == R_FS || seg_reg == R_GS) &&
|
1957 |
(env->segs[seg_reg].selector & 0xfffc) == 0) { |
1958 |
return;
|
1959 |
} |
1960 |
|
1961 |
e2 = env->segs[seg_reg].flags; |
1962 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
1963 |
if (!(e2 & DESC_CS_MASK) || !(e2 & DESC_C_MASK)) {
|
1964 |
/* data or non conforming code segment */
|
1965 |
if (dpl < cpl) {
|
1966 |
cpu_x86_load_seg_cache(env, seg_reg, 0, 0, 0, 0); |
1967 |
} |
1968 |
} |
1969 |
} |
1970 |
|
1971 |
/* protected mode iret */
|
1972 |
static inline void helper_ret_protected(CPUX86State *env, int shift, |
1973 |
int is_iret, int addend) |
1974 |
{ |
1975 |
uint32_t new_cs, new_eflags, new_ss; |
1976 |
uint32_t new_es, new_ds, new_fs, new_gs; |
1977 |
uint32_t e1, e2, ss_e1, ss_e2; |
1978 |
int cpl, dpl, rpl, eflags_mask, iopl;
|
1979 |
target_ulong ssp, sp, new_eip, new_esp, sp_mask; |
1980 |
|
1981 |
#ifdef TARGET_X86_64
|
1982 |
if (shift == 2) { |
1983 |
sp_mask = -1;
|
1984 |
} else
|
1985 |
#endif
|
1986 |
{ |
1987 |
sp_mask = get_sp_mask(env->segs[R_SS].flags); |
1988 |
} |
1989 |
sp = env->regs[R_ESP]; |
1990 |
ssp = env->segs[R_SS].base; |
1991 |
new_eflags = 0; /* avoid warning */ |
1992 |
#ifdef TARGET_X86_64
|
1993 |
if (shift == 2) { |
1994 |
POPQ(sp, new_eip); |
1995 |
POPQ(sp, new_cs); |
1996 |
new_cs &= 0xffff;
|
1997 |
if (is_iret) {
|
1998 |
POPQ(sp, new_eflags); |
1999 |
} |
2000 |
} else
|
2001 |
#endif
|
2002 |
{ |
2003 |
if (shift == 1) { |
2004 |
/* 32 bits */
|
2005 |
POPL(ssp, sp, sp_mask, new_eip); |
2006 |
POPL(ssp, sp, sp_mask, new_cs); |
2007 |
new_cs &= 0xffff;
|
2008 |
if (is_iret) {
|
2009 |
POPL(ssp, sp, sp_mask, new_eflags); |
2010 |
if (new_eflags & VM_MASK) {
|
2011 |
goto return_to_vm86;
|
2012 |
} |
2013 |
} |
2014 |
} else {
|
2015 |
/* 16 bits */
|
2016 |
POPW(ssp, sp, sp_mask, new_eip); |
2017 |
POPW(ssp, sp, sp_mask, new_cs); |
2018 |
if (is_iret) {
|
2019 |
POPW(ssp, sp, sp_mask, new_eflags); |
2020 |
} |
2021 |
} |
2022 |
} |
2023 |
LOG_PCALL("lret new %04x:" TARGET_FMT_lx " s=%d addend=0x%x\n", |
2024 |
new_cs, new_eip, shift, addend); |
2025 |
LOG_PCALL_STATE(CPU(x86_env_get_cpu(env))); |
2026 |
if ((new_cs & 0xfffc) == 0) { |
2027 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2028 |
} |
2029 |
if (load_segment(env, &e1, &e2, new_cs) != 0) { |
2030 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2031 |
} |
2032 |
if (!(e2 & DESC_S_MASK) ||
|
2033 |
!(e2 & DESC_CS_MASK)) { |
2034 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2035 |
} |
2036 |
cpl = env->hflags & HF_CPL_MASK; |
2037 |
rpl = new_cs & 3;
|
2038 |
if (rpl < cpl) {
|
2039 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2040 |
} |
2041 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2042 |
if (e2 & DESC_C_MASK) {
|
2043 |
if (dpl > rpl) {
|
2044 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2045 |
} |
2046 |
} else {
|
2047 |
if (dpl != rpl) {
|
2048 |
raise_exception_err(env, EXCP0D_GPF, new_cs & 0xfffc);
|
2049 |
} |
2050 |
} |
2051 |
if (!(e2 & DESC_P_MASK)) {
|
2052 |
raise_exception_err(env, EXCP0B_NOSEG, new_cs & 0xfffc);
|
2053 |
} |
2054 |
|
2055 |
sp += addend; |
2056 |
if (rpl == cpl && (!(env->hflags & HF_CS64_MASK) ||
|
2057 |
((env->hflags & HF_CS64_MASK) && !is_iret))) { |
2058 |
/* return to same privilege level */
|
2059 |
cpu_x86_load_seg_cache(env, R_CS, new_cs, |
2060 |
get_seg_base(e1, e2), |
2061 |
get_seg_limit(e1, e2), |
2062 |
e2); |
2063 |
} else {
|
2064 |
/* return to different privilege level */
|
2065 |
#ifdef TARGET_X86_64
|
2066 |
if (shift == 2) { |
2067 |
POPQ(sp, new_esp); |
2068 |
POPQ(sp, new_ss); |
2069 |
new_ss &= 0xffff;
|
2070 |
} else
|
2071 |
#endif
|
2072 |
{ |
2073 |
if (shift == 1) { |
2074 |
/* 32 bits */
|
2075 |
POPL(ssp, sp, sp_mask, new_esp); |
2076 |
POPL(ssp, sp, sp_mask, new_ss); |
2077 |
new_ss &= 0xffff;
|
2078 |
} else {
|
2079 |
/* 16 bits */
|
2080 |
POPW(ssp, sp, sp_mask, new_esp); |
2081 |
POPW(ssp, sp, sp_mask, new_ss); |
2082 |
} |
2083 |
} |
2084 |
LOG_PCALL("new ss:esp=%04x:" TARGET_FMT_lx "\n", |
2085 |
new_ss, new_esp); |
2086 |
if ((new_ss & 0xfffc) == 0) { |
2087 |
#ifdef TARGET_X86_64
|
2088 |
/* NULL ss is allowed in long mode if cpl != 3 */
|
2089 |
/* XXX: test CS64? */
|
2090 |
if ((env->hflags & HF_LMA_MASK) && rpl != 3) { |
2091 |
cpu_x86_load_seg_cache(env, R_SS, new_ss, |
2092 |
0, 0xffffffff, |
2093 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2094 |
DESC_S_MASK | (rpl << DESC_DPL_SHIFT) | |
2095 |
DESC_W_MASK | DESC_A_MASK); |
2096 |
ss_e2 = DESC_B_MASK; /* XXX: should not be needed? */
|
2097 |
} else
|
2098 |
#endif
|
2099 |
{ |
2100 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2101 |
} |
2102 |
} else {
|
2103 |
if ((new_ss & 3) != rpl) { |
2104 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2105 |
} |
2106 |
if (load_segment(env, &ss_e1, &ss_e2, new_ss) != 0) { |
2107 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2108 |
} |
2109 |
if (!(ss_e2 & DESC_S_MASK) ||
|
2110 |
(ss_e2 & DESC_CS_MASK) || |
2111 |
!(ss_e2 & DESC_W_MASK)) { |
2112 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2113 |
} |
2114 |
dpl = (ss_e2 >> DESC_DPL_SHIFT) & 3;
|
2115 |
if (dpl != rpl) {
|
2116 |
raise_exception_err(env, EXCP0D_GPF, new_ss & 0xfffc);
|
2117 |
} |
2118 |
if (!(ss_e2 & DESC_P_MASK)) {
|
2119 |
raise_exception_err(env, EXCP0B_NOSEG, new_ss & 0xfffc);
|
2120 |
} |
2121 |
cpu_x86_load_seg_cache(env, R_SS, new_ss, |
2122 |
get_seg_base(ss_e1, ss_e2), |
2123 |
get_seg_limit(ss_e1, ss_e2), |
2124 |
ss_e2); |
2125 |
} |
2126 |
|
2127 |
cpu_x86_load_seg_cache(env, R_CS, new_cs, |
2128 |
get_seg_base(e1, e2), |
2129 |
get_seg_limit(e1, e2), |
2130 |
e2); |
2131 |
cpu_x86_set_cpl(env, rpl); |
2132 |
sp = new_esp; |
2133 |
#ifdef TARGET_X86_64
|
2134 |
if (env->hflags & HF_CS64_MASK) {
|
2135 |
sp_mask = -1;
|
2136 |
} else
|
2137 |
#endif
|
2138 |
{ |
2139 |
sp_mask = get_sp_mask(ss_e2); |
2140 |
} |
2141 |
|
2142 |
/* validate data segments */
|
2143 |
validate_seg(env, R_ES, rpl); |
2144 |
validate_seg(env, R_DS, rpl); |
2145 |
validate_seg(env, R_FS, rpl); |
2146 |
validate_seg(env, R_GS, rpl); |
2147 |
|
2148 |
sp += addend; |
2149 |
} |
2150 |
SET_ESP(sp, sp_mask); |
2151 |
env->eip = new_eip; |
2152 |
if (is_iret) {
|
2153 |
/* NOTE: 'cpl' is the _old_ CPL */
|
2154 |
eflags_mask = TF_MASK | AC_MASK | ID_MASK | RF_MASK | NT_MASK; |
2155 |
if (cpl == 0) { |
2156 |
eflags_mask |= IOPL_MASK; |
2157 |
} |
2158 |
iopl = (env->eflags >> IOPL_SHIFT) & 3;
|
2159 |
if (cpl <= iopl) {
|
2160 |
eflags_mask |= IF_MASK; |
2161 |
} |
2162 |
if (shift == 0) { |
2163 |
eflags_mask &= 0xffff;
|
2164 |
} |
2165 |
cpu_load_eflags(env, new_eflags, eflags_mask); |
2166 |
} |
2167 |
return;
|
2168 |
|
2169 |
return_to_vm86:
|
2170 |
POPL(ssp, sp, sp_mask, new_esp); |
2171 |
POPL(ssp, sp, sp_mask, new_ss); |
2172 |
POPL(ssp, sp, sp_mask, new_es); |
2173 |
POPL(ssp, sp, sp_mask, new_ds); |
2174 |
POPL(ssp, sp, sp_mask, new_fs); |
2175 |
POPL(ssp, sp, sp_mask, new_gs); |
2176 |
|
2177 |
/* modify processor state */
|
2178 |
cpu_load_eflags(env, new_eflags, TF_MASK | AC_MASK | ID_MASK | |
2179 |
IF_MASK | IOPL_MASK | VM_MASK | NT_MASK | VIF_MASK | |
2180 |
VIP_MASK); |
2181 |
load_seg_vm(env, R_CS, new_cs & 0xffff);
|
2182 |
cpu_x86_set_cpl(env, 3);
|
2183 |
load_seg_vm(env, R_SS, new_ss & 0xffff);
|
2184 |
load_seg_vm(env, R_ES, new_es & 0xffff);
|
2185 |
load_seg_vm(env, R_DS, new_ds & 0xffff);
|
2186 |
load_seg_vm(env, R_FS, new_fs & 0xffff);
|
2187 |
load_seg_vm(env, R_GS, new_gs & 0xffff);
|
2188 |
|
2189 |
env->eip = new_eip & 0xffff;
|
2190 |
env->regs[R_ESP] = new_esp; |
2191 |
} |
2192 |
|
2193 |
void helper_iret_protected(CPUX86State *env, int shift, int next_eip) |
2194 |
{ |
2195 |
int tss_selector, type;
|
2196 |
uint32_t e1, e2; |
2197 |
|
2198 |
/* specific case for TSS */
|
2199 |
if (env->eflags & NT_MASK) {
|
2200 |
#ifdef TARGET_X86_64
|
2201 |
if (env->hflags & HF_LMA_MASK) {
|
2202 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2203 |
} |
2204 |
#endif
|
2205 |
tss_selector = cpu_lduw_kernel(env, env->tr.base + 0);
|
2206 |
if (tss_selector & 4) { |
2207 |
raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
2208 |
} |
2209 |
if (load_segment(env, &e1, &e2, tss_selector) != 0) { |
2210 |
raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
2211 |
} |
2212 |
type = (e2 >> DESC_TYPE_SHIFT) & 0x17;
|
2213 |
/* NOTE: we check both segment and busy TSS */
|
2214 |
if (type != 3) { |
2215 |
raise_exception_err(env, EXCP0A_TSS, tss_selector & 0xfffc);
|
2216 |
} |
2217 |
switch_tss(env, tss_selector, e1, e2, SWITCH_TSS_IRET, next_eip); |
2218 |
} else {
|
2219 |
helper_ret_protected(env, shift, 1, 0); |
2220 |
} |
2221 |
env->hflags2 &= ~HF2_NMI_MASK; |
2222 |
} |
2223 |
|
2224 |
void helper_lret_protected(CPUX86State *env, int shift, int addend) |
2225 |
{ |
2226 |
helper_ret_protected(env, shift, 0, addend);
|
2227 |
} |
2228 |
|
2229 |
void helper_sysenter(CPUX86State *env)
|
2230 |
{ |
2231 |
if (env->sysenter_cs == 0) { |
2232 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2233 |
} |
2234 |
env->eflags &= ~(VM_MASK | IF_MASK | RF_MASK); |
2235 |
cpu_x86_set_cpl(env, 0);
|
2236 |
|
2237 |
#ifdef TARGET_X86_64
|
2238 |
if (env->hflags & HF_LMA_MASK) {
|
2239 |
cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
|
2240 |
0, 0xffffffff, |
2241 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2242 |
DESC_S_MASK | |
2243 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
2244 |
DESC_L_MASK); |
2245 |
} else
|
2246 |
#endif
|
2247 |
{ |
2248 |
cpu_x86_load_seg_cache(env, R_CS, env->sysenter_cs & 0xfffc,
|
2249 |
0, 0xffffffff, |
2250 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2251 |
DESC_S_MASK | |
2252 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
2253 |
} |
2254 |
cpu_x86_load_seg_cache(env, R_SS, (env->sysenter_cs + 8) & 0xfffc, |
2255 |
0, 0xffffffff, |
2256 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2257 |
DESC_S_MASK | |
2258 |
DESC_W_MASK | DESC_A_MASK); |
2259 |
env->regs[R_ESP] = env->sysenter_esp; |
2260 |
env->eip = env->sysenter_eip; |
2261 |
} |
2262 |
|
2263 |
void helper_sysexit(CPUX86State *env, int dflag) |
2264 |
{ |
2265 |
int cpl;
|
2266 |
|
2267 |
cpl = env->hflags & HF_CPL_MASK; |
2268 |
if (env->sysenter_cs == 0 || cpl != 0) { |
2269 |
raise_exception_err(env, EXCP0D_GPF, 0);
|
2270 |
} |
2271 |
cpu_x86_set_cpl(env, 3);
|
2272 |
#ifdef TARGET_X86_64
|
2273 |
if (dflag == 2) { |
2274 |
cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 32) & 0xfffc) | |
2275 |
3, 0, 0xffffffff, |
2276 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2277 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2278 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK | |
2279 |
DESC_L_MASK); |
2280 |
cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 40) & 0xfffc) | |
2281 |
3, 0, 0xffffffff, |
2282 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2283 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2284 |
DESC_W_MASK | DESC_A_MASK); |
2285 |
} else
|
2286 |
#endif
|
2287 |
{ |
2288 |
cpu_x86_load_seg_cache(env, R_CS, ((env->sysenter_cs + 16) & 0xfffc) | |
2289 |
3, 0, 0xffffffff, |
2290 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2291 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2292 |
DESC_CS_MASK | DESC_R_MASK | DESC_A_MASK); |
2293 |
cpu_x86_load_seg_cache(env, R_SS, ((env->sysenter_cs + 24) & 0xfffc) | |
2294 |
3, 0, 0xffffffff, |
2295 |
DESC_G_MASK | DESC_B_MASK | DESC_P_MASK | |
2296 |
DESC_S_MASK | (3 << DESC_DPL_SHIFT) |
|
2297 |
DESC_W_MASK | DESC_A_MASK); |
2298 |
} |
2299 |
env->regs[R_ESP] = env->regs[R_ECX]; |
2300 |
env->eip = env->regs[R_EDX]; |
2301 |
} |
2302 |
|
2303 |
target_ulong helper_lsl(CPUX86State *env, target_ulong selector1) |
2304 |
{ |
2305 |
unsigned int limit; |
2306 |
uint32_t e1, e2, eflags, selector; |
2307 |
int rpl, dpl, cpl, type;
|
2308 |
|
2309 |
selector = selector1 & 0xffff;
|
2310 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2311 |
if ((selector & 0xfffc) == 0) { |
2312 |
goto fail;
|
2313 |
} |
2314 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2315 |
goto fail;
|
2316 |
} |
2317 |
rpl = selector & 3;
|
2318 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2319 |
cpl = env->hflags & HF_CPL_MASK; |
2320 |
if (e2 & DESC_S_MASK) {
|
2321 |
if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
|
2322 |
/* conforming */
|
2323 |
} else {
|
2324 |
if (dpl < cpl || dpl < rpl) {
|
2325 |
goto fail;
|
2326 |
} |
2327 |
} |
2328 |
} else {
|
2329 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
2330 |
switch (type) {
|
2331 |
case 1: |
2332 |
case 2: |
2333 |
case 3: |
2334 |
case 9: |
2335 |
case 11: |
2336 |
break;
|
2337 |
default:
|
2338 |
goto fail;
|
2339 |
} |
2340 |
if (dpl < cpl || dpl < rpl) {
|
2341 |
fail:
|
2342 |
CC_SRC = eflags & ~CC_Z; |
2343 |
return 0; |
2344 |
} |
2345 |
} |
2346 |
limit = get_seg_limit(e1, e2); |
2347 |
CC_SRC = eflags | CC_Z; |
2348 |
return limit;
|
2349 |
} |
2350 |
|
2351 |
target_ulong helper_lar(CPUX86State *env, target_ulong selector1) |
2352 |
{ |
2353 |
uint32_t e1, e2, eflags, selector; |
2354 |
int rpl, dpl, cpl, type;
|
2355 |
|
2356 |
selector = selector1 & 0xffff;
|
2357 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2358 |
if ((selector & 0xfffc) == 0) { |
2359 |
goto fail;
|
2360 |
} |
2361 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2362 |
goto fail;
|
2363 |
} |
2364 |
rpl = selector & 3;
|
2365 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2366 |
cpl = env->hflags & HF_CPL_MASK; |
2367 |
if (e2 & DESC_S_MASK) {
|
2368 |
if ((e2 & DESC_CS_MASK) && (e2 & DESC_C_MASK)) {
|
2369 |
/* conforming */
|
2370 |
} else {
|
2371 |
if (dpl < cpl || dpl < rpl) {
|
2372 |
goto fail;
|
2373 |
} |
2374 |
} |
2375 |
} else {
|
2376 |
type = (e2 >> DESC_TYPE_SHIFT) & 0xf;
|
2377 |
switch (type) {
|
2378 |
case 1: |
2379 |
case 2: |
2380 |
case 3: |
2381 |
case 4: |
2382 |
case 5: |
2383 |
case 9: |
2384 |
case 11: |
2385 |
case 12: |
2386 |
break;
|
2387 |
default:
|
2388 |
goto fail;
|
2389 |
} |
2390 |
if (dpl < cpl || dpl < rpl) {
|
2391 |
fail:
|
2392 |
CC_SRC = eflags & ~CC_Z; |
2393 |
return 0; |
2394 |
} |
2395 |
} |
2396 |
CC_SRC = eflags | CC_Z; |
2397 |
return e2 & 0x00f0ff00; |
2398 |
} |
2399 |
|
2400 |
void helper_verr(CPUX86State *env, target_ulong selector1)
|
2401 |
{ |
2402 |
uint32_t e1, e2, eflags, selector; |
2403 |
int rpl, dpl, cpl;
|
2404 |
|
2405 |
selector = selector1 & 0xffff;
|
2406 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2407 |
if ((selector & 0xfffc) == 0) { |
2408 |
goto fail;
|
2409 |
} |
2410 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2411 |
goto fail;
|
2412 |
} |
2413 |
if (!(e2 & DESC_S_MASK)) {
|
2414 |
goto fail;
|
2415 |
} |
2416 |
rpl = selector & 3;
|
2417 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2418 |
cpl = env->hflags & HF_CPL_MASK; |
2419 |
if (e2 & DESC_CS_MASK) {
|
2420 |
if (!(e2 & DESC_R_MASK)) {
|
2421 |
goto fail;
|
2422 |
} |
2423 |
if (!(e2 & DESC_C_MASK)) {
|
2424 |
if (dpl < cpl || dpl < rpl) {
|
2425 |
goto fail;
|
2426 |
} |
2427 |
} |
2428 |
} else {
|
2429 |
if (dpl < cpl || dpl < rpl) {
|
2430 |
fail:
|
2431 |
CC_SRC = eflags & ~CC_Z; |
2432 |
return;
|
2433 |
} |
2434 |
} |
2435 |
CC_SRC = eflags | CC_Z; |
2436 |
} |
2437 |
|
2438 |
void helper_verw(CPUX86State *env, target_ulong selector1)
|
2439 |
{ |
2440 |
uint32_t e1, e2, eflags, selector; |
2441 |
int rpl, dpl, cpl;
|
2442 |
|
2443 |
selector = selector1 & 0xffff;
|
2444 |
eflags = cpu_cc_compute_all(env, CC_OP); |
2445 |
if ((selector & 0xfffc) == 0) { |
2446 |
goto fail;
|
2447 |
} |
2448 |
if (load_segment(env, &e1, &e2, selector) != 0) { |
2449 |
goto fail;
|
2450 |
} |
2451 |
if (!(e2 & DESC_S_MASK)) {
|
2452 |
goto fail;
|
2453 |
} |
2454 |
rpl = selector & 3;
|
2455 |
dpl = (e2 >> DESC_DPL_SHIFT) & 3;
|
2456 |
cpl = env->hflags & HF_CPL_MASK; |
2457 |
if (e2 & DESC_CS_MASK) {
|
2458 |
goto fail;
|
2459 |
} else {
|
2460 |
if (dpl < cpl || dpl < rpl) {
|
2461 |
goto fail;
|
2462 |
} |
2463 |
if (!(e2 & DESC_W_MASK)) {
|
2464 |
fail:
|
2465 |
CC_SRC = eflags & ~CC_Z; |
2466 |
return;
|
2467 |
} |
2468 |
} |
2469 |
CC_SRC = eflags | CC_Z; |
2470 |
} |
2471 |
|
2472 |
#if defined(CONFIG_USER_ONLY)
|
2473 |
void cpu_x86_load_seg(CPUX86State *env, int seg_reg, int selector) |
2474 |
{ |
2475 |
if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) { |
2476 |
selector &= 0xffff;
|
2477 |
cpu_x86_load_seg_cache(env, seg_reg, selector, |
2478 |
(selector << 4), 0xffff, 0); |
2479 |
} else {
|
2480 |
helper_load_seg(env, seg_reg, selector); |
2481 |
} |
2482 |
} |
2483 |
#endif
|