Revision fe253235
b/target-mips/translate.c | ||
---|---|---|
733 | 733 |
|
734 | 734 |
static inline void check_cp0_enabled(DisasContext *ctx) |
735 | 735 |
{ |
736 |
if (!(ctx->hflags & MIPS_HFLAG_CP0))
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|
736 |
if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0)))
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|
737 | 737 |
generate_exception_err(ctx, EXCP_CpU, 1); |
738 | 738 |
} |
739 | 739 |
|
740 | 740 |
static inline void check_cp1_enabled(DisasContext *ctx) |
741 | 741 |
{ |
742 |
if (!(ctx->hflags & MIPS_HFLAG_FPU))
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|
742 |
if (unlikely(!(ctx->hflags & MIPS_HFLAG_FPU)))
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|
743 | 743 |
generate_exception_err(ctx, EXCP_CpU, 1); |
744 | 744 |
} |
745 | 745 |
|
746 | 746 |
static inline void check_cp1_64bitmode(DisasContext *ctx) |
747 | 747 |
{ |
748 |
if (!(ctx->hflags & MIPS_HFLAG_F64))
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|
748 |
if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64)))
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|
749 | 749 |
generate_exception(ctx, EXCP_RI); |
750 | 750 |
} |
751 | 751 |
|
... | ... | |
762 | 762 |
*/ |
763 | 763 |
void check_cp1_registers(DisasContext *ctx, int regs) |
764 | 764 |
{ |
765 |
if (!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))
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|
765 |
if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1)))
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|
766 | 766 |
generate_exception(ctx, EXCP_RI); |
767 | 767 |
} |
768 | 768 |
|
... | ... | |
778 | 778 |
CPU is not MIPS MT capable. */ |
779 | 779 |
static inline void check_mips_mt(CPUState *env, DisasContext *ctx) |
780 | 780 |
{ |
781 |
if (!(env->CP0_Config3 & (1 << CP0C3_MT)))
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|
781 |
if (unlikely(!(env->CP0_Config3 & (1 << CP0C3_MT))))
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|
782 | 782 |
generate_exception(ctx, EXCP_RI); |
783 | 783 |
} |
784 | 784 |
|
... | ... | |
786 | 786 |
instructions are not enabled. */ |
787 | 787 |
static inline void check_mips_64(DisasContext *ctx) |
788 | 788 |
{ |
789 |
if (!(ctx->hflags & MIPS_HFLAG_64))
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|
789 |
if (unlikely(!(ctx->hflags & MIPS_HFLAG_64)))
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790 | 790 |
generate_exception(ctx, EXCP_RI); |
791 | 791 |
} |
792 | 792 |
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