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1 | 4acb54ba | Edgar E. Iglesias | /*
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2 | 4acb54ba | Edgar E. Iglesias | * MicroBlaze virtual CPU header
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3 | 4acb54ba | Edgar E. Iglesias | *
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4 | 4acb54ba | Edgar E. Iglesias | * Copyright (c) 2009 Edgar E. Iglesias
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5 | 4acb54ba | Edgar E. Iglesias | *
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6 | 4acb54ba | Edgar E. Iglesias | * This library is free software; you can redistribute it and/or
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7 | 4acb54ba | Edgar E. Iglesias | * modify it under the terms of the GNU Lesser General Public
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8 | 4acb54ba | Edgar E. Iglesias | * License as published by the Free Software Foundation; either
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9 | 4acb54ba | Edgar E. Iglesias | * version 2 of the License, or (at your option) any later version.
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10 | 4acb54ba | Edgar E. Iglesias | *
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11 | 4acb54ba | Edgar E. Iglesias | * This library is distributed in the hope that it will be useful,
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12 | 4acb54ba | Edgar E. Iglesias | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4acb54ba | Edgar E. Iglesias | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4acb54ba | Edgar E. Iglesias | * General Public License for more details.
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15 | 4acb54ba | Edgar E. Iglesias | *
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16 | 4acb54ba | Edgar E. Iglesias | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 4acb54ba | Edgar E. Iglesias | */
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19 | 4acb54ba | Edgar E. Iglesias | #ifndef CPU_MICROBLAZE_H
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20 | 4acb54ba | Edgar E. Iglesias | #define CPU_MICROBLAZE_H
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21 | 4acb54ba | Edgar E. Iglesias | |
22 | 94598c1d | Stefan Weil | #include "config.h" |
23 | 94598c1d | Stefan Weil | #include "qemu-common.h" |
24 | 94598c1d | Stefan Weil | |
25 | 4acb54ba | Edgar E. Iglesias | #define TARGET_LONG_BITS 32 |
26 | 4acb54ba | Edgar E. Iglesias | |
27 | 9349b4f9 | Andreas Färber | #define CPUArchState struct CPUMBState |
28 | 4acb54ba | Edgar E. Iglesias | |
29 | 022c62cb | Paolo Bonzini | #include "exec/cpu-defs.h" |
30 | 6b4c305c | Paolo Bonzini | #include "fpu/softfloat.h" |
31 | 4acb54ba | Edgar E. Iglesias | struct CPUMBState;
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32 | 9b9a970a | Andreas Färber | typedef struct CPUMBState CPUMBState; |
33 | 4acb54ba | Edgar E. Iglesias | #if !defined(CONFIG_USER_ONLY)
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34 | 4acb54ba | Edgar E. Iglesias | #include "mmu.h" |
35 | 4acb54ba | Edgar E. Iglesias | #endif
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36 | 4acb54ba | Edgar E. Iglesias | |
37 | 4acb54ba | Edgar E. Iglesias | #define TARGET_HAS_ICE 1 |
38 | 4acb54ba | Edgar E. Iglesias | |
39 | 0d5d4699 | Edgar E. Iglesias | #define ELF_MACHINE EM_MICROBLAZE
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40 | 4acb54ba | Edgar E. Iglesias | |
41 | 4acb54ba | Edgar E. Iglesias | #define EXCP_NMI 1 |
42 | 4acb54ba | Edgar E. Iglesias | #define EXCP_MMU 2 |
43 | 4acb54ba | Edgar E. Iglesias | #define EXCP_IRQ 3 |
44 | 4acb54ba | Edgar E. Iglesias | #define EXCP_BREAK 4 |
45 | 4acb54ba | Edgar E. Iglesias | #define EXCP_HW_BREAK 5 |
46 | cedb936b | Edgar E. Iglesias | #define EXCP_HW_EXCP 6 |
47 | 4acb54ba | Edgar E. Iglesias | |
48 | 85097db6 | Richard Henderson | /* MicroBlaze-specific interrupt pending bits. */
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49 | 85097db6 | Richard Henderson | #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
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50 | 85097db6 | Richard Henderson | |
51 | 73c69456 | Alistair Francis | /* Meanings of the MBCPU object's two inbound GPIO lines */
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52 | 73c69456 | Alistair Francis | #define MB_CPU_IRQ 0 |
53 | 73c69456 | Alistair Francis | #define MB_CPU_FIR 1 |
54 | 73c69456 | Alistair Francis | |
55 | 4acb54ba | Edgar E. Iglesias | /* Register aliases. R0 - R15 */
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56 | 4acb54ba | Edgar E. Iglesias | #define R_SP 1 |
57 | 4acb54ba | Edgar E. Iglesias | #define SR_PC 0 |
58 | 4acb54ba | Edgar E. Iglesias | #define SR_MSR 1 |
59 | 4acb54ba | Edgar E. Iglesias | #define SR_EAR 3 |
60 | 4acb54ba | Edgar E. Iglesias | #define SR_ESR 5 |
61 | 4acb54ba | Edgar E. Iglesias | #define SR_FSR 7 |
62 | 4acb54ba | Edgar E. Iglesias | #define SR_BTR 0xb |
63 | 4acb54ba | Edgar E. Iglesias | #define SR_EDR 0xd |
64 | 4acb54ba | Edgar E. Iglesias | |
65 | 4acb54ba | Edgar E. Iglesias | /* MSR flags. */
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66 | 4acb54ba | Edgar E. Iglesias | #define MSR_BE (1<<0) /* 0x001 */ |
67 | 4acb54ba | Edgar E. Iglesias | #define MSR_IE (1<<1) /* 0x002 */ |
68 | 4acb54ba | Edgar E. Iglesias | #define MSR_C (1<<2) /* 0x004 */ |
69 | 4acb54ba | Edgar E. Iglesias | #define MSR_BIP (1<<3) /* 0x008 */ |
70 | 4acb54ba | Edgar E. Iglesias | #define MSR_FSL (1<<4) /* 0x010 */ |
71 | 4acb54ba | Edgar E. Iglesias | #define MSR_ICE (1<<5) /* 0x020 */ |
72 | 4acb54ba | Edgar E. Iglesias | #define MSR_DZ (1<<6) /* 0x040 */ |
73 | 4acb54ba | Edgar E. Iglesias | #define MSR_DCE (1<<7) /* 0x080 */ |
74 | 4acb54ba | Edgar E. Iglesias | #define MSR_EE (1<<8) /* 0x100 */ |
75 | 4acb54ba | Edgar E. Iglesias | #define MSR_EIP (1<<9) /* 0x200 */ |
76 | 8a84fc6b | Edgar E. Iglesias | #define MSR_PVR (1<<10) /* 0x400 */ |
77 | 4acb54ba | Edgar E. Iglesias | #define MSR_CC (1<<31) |
78 | 4acb54ba | Edgar E. Iglesias | |
79 | 4acb54ba | Edgar E. Iglesias | /* Machine State Register (MSR) Fields */
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80 | 4acb54ba | Edgar E. Iglesias | #define MSR_UM (1<<11) /* User Mode */ |
81 | 4acb54ba | Edgar E. Iglesias | #define MSR_UMS (1<<12) /* User Mode Save */ |
82 | 4acb54ba | Edgar E. Iglesias | #define MSR_VM (1<<13) /* Virtual Mode */ |
83 | 4acb54ba | Edgar E. Iglesias | #define MSR_VMS (1<<14) /* Virtual Mode Save */ |
84 | 4acb54ba | Edgar E. Iglesias | |
85 | 4acb54ba | Edgar E. Iglesias | #define MSR_KERNEL MSR_EE|MSR_VM
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86 | 4acb54ba | Edgar E. Iglesias | //#define MSR_USER MSR_KERNEL|MSR_UM|MSR_IE
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87 | 4acb54ba | Edgar E. Iglesias | #define MSR_KERNEL_VMS MSR_EE|MSR_VMS
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88 | 4acb54ba | Edgar E. Iglesias | //#define MSR_USER_VMS MSR_KERNEL_VMS|MSR_UMS|MSR_IE
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89 | 4acb54ba | Edgar E. Iglesias | |
90 | 4acb54ba | Edgar E. Iglesias | /* Exception State Register (ESR) Fields */
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91 | 4acb54ba | Edgar E. Iglesias | #define ESR_DIZ (1<<11) /* Zone Protection */ |
92 | 4acb54ba | Edgar E. Iglesias | #define ESR_S (1<<10) /* Store instruction */ |
93 | 4acb54ba | Edgar E. Iglesias | |
94 | 85453641 | Edgar E. Iglesias | #define ESR_ESS_FSL_OFFSET 5 |
95 | 85453641 | Edgar E. Iglesias | |
96 | cedb936b | Edgar E. Iglesias | #define ESR_EC_FSL 0 |
97 | cedb936b | Edgar E. Iglesias | #define ESR_EC_UNALIGNED_DATA 1 |
98 | cedb936b | Edgar E. Iglesias | #define ESR_EC_ILLEGAL_OP 2 |
99 | cedb936b | Edgar E. Iglesias | #define ESR_EC_INSN_BUS 3 |
100 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DATA_BUS 4 |
101 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DIVZERO 5 |
102 | cedb936b | Edgar E. Iglesias | #define ESR_EC_FPU 6 |
103 | cedb936b | Edgar E. Iglesias | #define ESR_EC_PRIVINSN 7 |
104 | 5818dee5 | Edgar E. Iglesias | #define ESR_EC_STACKPROT 7 /* Same as PRIVINSN. */ |
105 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DATA_STORAGE 8 |
106 | cedb936b | Edgar E. Iglesias | #define ESR_EC_INSN_STORAGE 9 |
107 | cedb936b | Edgar E. Iglesias | #define ESR_EC_DATA_TLB 10 |
108 | cedb936b | Edgar E. Iglesias | #define ESR_EC_INSN_TLB 11 |
109 | 3b584046 | Edgar E. Iglesias | #define ESR_EC_MASK 31 |
110 | 4acb54ba | Edgar E. Iglesias | |
111 | bdc0bf29 | Edgar E. Iglesias | /* Floating Point Status Register (FSR) Bits */
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112 | bdc0bf29 | Edgar E. Iglesias | #define FSR_IO (1<<4) /* Invalid operation */ |
113 | bdc0bf29 | Edgar E. Iglesias | #define FSR_DZ (1<<3) /* Divide-by-zero */ |
114 | bdc0bf29 | Edgar E. Iglesias | #define FSR_OF (1<<2) /* Overflow */ |
115 | bdc0bf29 | Edgar E. Iglesias | #define FSR_UF (1<<1) /* Underflow */ |
116 | bdc0bf29 | Edgar E. Iglesias | #define FSR_DO (1<<0) /* Denormalized operand error */ |
117 | bdc0bf29 | Edgar E. Iglesias | |
118 | 4acb54ba | Edgar E. Iglesias | /* Version reg. */
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119 | 4acb54ba | Edgar E. Iglesias | /* Basic PVR mask */
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120 | 4acb54ba | Edgar E. Iglesias | #define PVR0_PVR_FULL_MASK 0x80000000 |
121 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_BARREL_MASK 0x40000000 |
122 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_DIV_MASK 0x20000000 |
123 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_HW_MUL_MASK 0x10000000 |
124 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_FPU_MASK 0x08000000 |
125 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_EXC_MASK 0x04000000 |
126 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_ICACHE_MASK 0x02000000 |
127 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_DCACHE_MASK 0x01000000 |
128 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USE_MMU 0x00800000 /* new */ |
129 | c4374bb7 | Michal Simek | #define PVR0_USE_BTC 0x00400000 |
130 | c4374bb7 | Michal Simek | #define PVR0_ENDI 0x00200000 |
131 | c4374bb7 | Michal Simek | #define PVR0_FAULT 0x00100000 |
132 | 4acb54ba | Edgar E. Iglesias | #define PVR0_VERSION_MASK 0x0000FF00 |
133 | 4acb54ba | Edgar E. Iglesias | #define PVR0_USER1_MASK 0x000000FF |
134 | 4acb54ba | Edgar E. Iglesias | |
135 | 4acb54ba | Edgar E. Iglesias | /* User 2 PVR mask */
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136 | 4acb54ba | Edgar E. Iglesias | #define PVR1_USER2_MASK 0xFFFFFFFF |
137 | 4acb54ba | Edgar E. Iglesias | |
138 | 4acb54ba | Edgar E. Iglesias | /* Configuration PVR masks */
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139 | 4acb54ba | Edgar E. Iglesias | #define PVR2_D_OPB_MASK 0x80000000 |
140 | 4acb54ba | Edgar E. Iglesias | #define PVR2_D_LMB_MASK 0x40000000 |
141 | 4acb54ba | Edgar E. Iglesias | #define PVR2_I_OPB_MASK 0x20000000 |
142 | 4acb54ba | Edgar E. Iglesias | #define PVR2_I_LMB_MASK 0x10000000 |
143 | 4acb54ba | Edgar E. Iglesias | #define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000 |
144 | 4acb54ba | Edgar E. Iglesias | #define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000 |
145 | 4acb54ba | Edgar E. Iglesias | #define PVR2_D_PLB_MASK 0x02000000 /* new */ |
146 | 4acb54ba | Edgar E. Iglesias | #define PVR2_I_PLB_MASK 0x01000000 /* new */ |
147 | 4acb54ba | Edgar E. Iglesias | #define PVR2_INTERCONNECT 0x00800000 /* new */ |
148 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_EXTEND_FSL 0x00080000 /* new */ |
149 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_FSL_EXC 0x00040000 /* new */ |
150 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_MSR_INSTR 0x00020000 |
151 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_PCMP_INSTR 0x00010000 |
152 | 4acb54ba | Edgar E. Iglesias | #define PVR2_AREA_OPTIMISED 0x00008000 |
153 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_BARREL_MASK 0x00004000 |
154 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_DIV_MASK 0x00002000 |
155 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_HW_MUL_MASK 0x00001000 |
156 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_FPU_MASK 0x00000800 |
157 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_MUL64_MASK 0x00000400 |
158 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_FPU2_MASK 0x00000200 /* new */ |
159 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_IPLBEXC 0x00000100 |
160 | 4acb54ba | Edgar E. Iglesias | #define PVR2_USE_DPLBEXC 0x00000080 |
161 | 4acb54ba | Edgar E. Iglesias | #define PVR2_OPCODE_0x0_ILL_MASK 0x00000040 |
162 | 4acb54ba | Edgar E. Iglesias | #define PVR2_UNALIGNED_EXC_MASK 0x00000020 |
163 | 4acb54ba | Edgar E. Iglesias | #define PVR2_ILL_OPCODE_EXC_MASK 0x00000010 |
164 | 4acb54ba | Edgar E. Iglesias | #define PVR2_IOPB_BUS_EXC_MASK 0x00000008 |
165 | 4acb54ba | Edgar E. Iglesias | #define PVR2_DOPB_BUS_EXC_MASK 0x00000004 |
166 | 4acb54ba | Edgar E. Iglesias | #define PVR2_DIV_ZERO_EXC_MASK 0x00000002 |
167 | 4acb54ba | Edgar E. Iglesias | #define PVR2_FPU_EXC_MASK 0x00000001 |
168 | 4acb54ba | Edgar E. Iglesias | |
169 | 4acb54ba | Edgar E. Iglesias | /* Debug and exception PVR masks */
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170 | 4acb54ba | Edgar E. Iglesias | #define PVR3_DEBUG_ENABLED_MASK 0x80000000 |
171 | 4acb54ba | Edgar E. Iglesias | #define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000 |
172 | 4acb54ba | Edgar E. Iglesias | #define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000 |
173 | 4acb54ba | Edgar E. Iglesias | #define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000 |
174 | 4acb54ba | Edgar E. Iglesias | #define PVR3_FSL_LINKS_MASK 0x00000380 |
175 | 4acb54ba | Edgar E. Iglesias | |
176 | 4acb54ba | Edgar E. Iglesias | /* ICache config PVR masks */
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177 | 4acb54ba | Edgar E. Iglesias | #define PVR4_USE_ICACHE_MASK 0x80000000 |
178 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000 |
179 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_USE_FSL_MASK 0x02000000 |
180 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000 |
181 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000 |
182 | 4acb54ba | Edgar E. Iglesias | #define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000 |
183 | 4acb54ba | Edgar E. Iglesias | |
184 | 4acb54ba | Edgar E. Iglesias | /* DCache config PVR masks */
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185 | 4acb54ba | Edgar E. Iglesias | #define PVR5_USE_DCACHE_MASK 0x80000000 |
186 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000 |
187 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_USE_FSL_MASK 0x02000000 |
188 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000 |
189 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000 |
190 | 4acb54ba | Edgar E. Iglesias | #define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000 |
191 | c4374bb7 | Michal Simek | #define PVR5_DCACHE_WRITEBACK_MASK 0x00004000 |
192 | 4acb54ba | Edgar E. Iglesias | |
193 | 4acb54ba | Edgar E. Iglesias | /* ICache base address PVR mask */
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194 | 4acb54ba | Edgar E. Iglesias | #define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF |
195 | 4acb54ba | Edgar E. Iglesias | |
196 | 4acb54ba | Edgar E. Iglesias | /* ICache high address PVR mask */
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197 | 4acb54ba | Edgar E. Iglesias | #define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF |
198 | 4acb54ba | Edgar E. Iglesias | |
199 | 4acb54ba | Edgar E. Iglesias | /* DCache base address PVR mask */
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200 | 4acb54ba | Edgar E. Iglesias | #define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF |
201 | 4acb54ba | Edgar E. Iglesias | |
202 | 4acb54ba | Edgar E. Iglesias | /* DCache high address PVR mask */
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203 | 4acb54ba | Edgar E. Iglesias | #define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF |
204 | 4acb54ba | Edgar E. Iglesias | |
205 | 4acb54ba | Edgar E. Iglesias | /* Target family PVR mask */
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206 | 4acb54ba | Edgar E. Iglesias | #define PVR10_TARGET_FAMILY_MASK 0xFF000000 |
207 | 4acb54ba | Edgar E. Iglesias | |
208 | 4acb54ba | Edgar E. Iglesias | /* MMU descrtiption */
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209 | 4acb54ba | Edgar E. Iglesias | #define PVR11_USE_MMU 0xC0000000 |
210 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MMU_ITLB_SIZE 0x38000000 |
211 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MMU_DTLB_SIZE 0x07000000 |
212 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MMU_TLB_ACCESS 0x00C00000 |
213 | 7458a432 | Alejandro Cabrera | #define PVR11_MMU_ZONES 0x003E0000 |
214 | 4acb54ba | Edgar E. Iglesias | /* MSR Reset value PVR mask */
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215 | 4acb54ba | Edgar E. Iglesias | #define PVR11_MSR_RESET_VALUE_MASK 0x000007FF |
216 | 4acb54ba | Edgar E. Iglesias | |
217 | 4acb54ba | Edgar E. Iglesias | |
218 | 4acb54ba | Edgar E. Iglesias | |
219 | 4acb54ba | Edgar E. Iglesias | /* CPU flags. */
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220 | 4acb54ba | Edgar E. Iglesias | |
221 | 4acb54ba | Edgar E. Iglesias | /* Condition codes. */
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222 | 4acb54ba | Edgar E. Iglesias | #define CC_GE 5 |
223 | 4acb54ba | Edgar E. Iglesias | #define CC_GT 4 |
224 | 4acb54ba | Edgar E. Iglesias | #define CC_LE 3 |
225 | 4acb54ba | Edgar E. Iglesias | #define CC_LT 2 |
226 | 4acb54ba | Edgar E. Iglesias | #define CC_NE 1 |
227 | 4acb54ba | Edgar E. Iglesias | #define CC_EQ 0 |
228 | 4acb54ba | Edgar E. Iglesias | |
229 | 4acb54ba | Edgar E. Iglesias | #define NB_MMU_MODES 3 |
230 | 85453641 | Edgar E. Iglesias | |
231 | 85453641 | Edgar E. Iglesias | #define STREAM_EXCEPTION (1 << 0) |
232 | 85453641 | Edgar E. Iglesias | #define STREAM_ATOMIC (1 << 1) |
233 | 85453641 | Edgar E. Iglesias | #define STREAM_TEST (1 << 2) |
234 | 85453641 | Edgar E. Iglesias | #define STREAM_CONTROL (1 << 3) |
235 | 85453641 | Edgar E. Iglesias | #define STREAM_NONBLOCK (1 << 4) |
236 | 85453641 | Edgar E. Iglesias | |
237 | ae7d54d4 | Andreas Färber | struct CPUMBState {
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238 | 4acb54ba | Edgar E. Iglesias | uint32_t debug; |
239 | 4acb54ba | Edgar E. Iglesias | uint32_t btaken; |
240 | 4acb54ba | Edgar E. Iglesias | uint32_t btarget; |
241 | 4acb54ba | Edgar E. Iglesias | uint32_t bimm; |
242 | 4acb54ba | Edgar E. Iglesias | |
243 | 4acb54ba | Edgar E. Iglesias | uint32_t imm; |
244 | 4acb54ba | Edgar E. Iglesias | uint32_t regs[33];
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245 | 4acb54ba | Edgar E. Iglesias | uint32_t sregs[24];
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246 | 97694c57 | Edgar E. Iglesias | float_status fp_status; |
247 | 5818dee5 | Edgar E. Iglesias | /* Stack protectors. Yes, it's a hw feature. */
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248 | 5818dee5 | Edgar E. Iglesias | uint32_t slr, shr; |
249 | 4acb54ba | Edgar E. Iglesias | |
250 | 8cc9b43f | Peter A. G. Crosthwaite | /* lwx/swx reserved address */
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251 | 8cc9b43f | Peter A. G. Crosthwaite | #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ |
252 | 8cc9b43f | Peter A. G. Crosthwaite | uint32_t res_addr; |
253 | 11a76217 | Edgar E. Iglesias | uint32_t res_val; |
254 | 8cc9b43f | Peter A. G. Crosthwaite | |
255 | 4acb54ba | Edgar E. Iglesias | /* Internal flags. */
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256 | cedb936b | Edgar E. Iglesias | #define IMM_FLAG 4 |
257 | cedb936b | Edgar E. Iglesias | #define MSR_EE_FLAG (1 << 8) |
258 | 4acb54ba | Edgar E. Iglesias | #define DRTI_FLAG (1 << 16) |
259 | 4acb54ba | Edgar E. Iglesias | #define DRTE_FLAG (1 << 17) |
260 | 4acb54ba | Edgar E. Iglesias | #define DRTB_FLAG (1 << 18) |
261 | 4acb54ba | Edgar E. Iglesias | #define D_FLAG (1 << 19) /* Bit in ESR. */ |
262 | 68cee38a | Andreas Färber | /* TB dependent CPUMBState. */
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263 | fd1dc858 | Edgar E. Iglesias | #define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
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264 | 4acb54ba | Edgar E. Iglesias | uint32_t iflags; |
265 | 4acb54ba | Edgar E. Iglesias | |
266 | 4acb54ba | Edgar E. Iglesias | struct {
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267 | 4acb54ba | Edgar E. Iglesias | uint32_t regs[16];
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268 | 4acb54ba | Edgar E. Iglesias | } pvr; |
269 | 4acb54ba | Edgar E. Iglesias | |
270 | 4acb54ba | Edgar E. Iglesias | #if !defined(CONFIG_USER_ONLY)
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271 | 4acb54ba | Edgar E. Iglesias | /* Unified MMU. */
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272 | 4acb54ba | Edgar E. Iglesias | struct microblaze_mmu mmu;
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273 | 4acb54ba | Edgar E. Iglesias | #endif
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274 | 4acb54ba | Edgar E. Iglesias | |
275 | 4acb54ba | Edgar E. Iglesias | CPU_COMMON |
276 | ae7d54d4 | Andreas Färber | }; |
277 | 4acb54ba | Edgar E. Iglesias | |
278 | b77f98ca | Andreas Färber | #include "cpu-qom.h" |
279 | b77f98ca | Andreas Färber | |
280 | cd0c24f9 | Andreas Färber | void mb_tcg_init(void); |
281 | b33ab1f7 | Andreas Färber | MicroBlazeCPU *cpu_mb_init(const char *cpu_model); |
282 | 68cee38a | Andreas Färber | int cpu_mb_exec(CPUMBState *s);
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283 | 4acb54ba | Edgar E. Iglesias | /* you can call this signal handler from your SIGBUS and SIGSEGV
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284 | 4acb54ba | Edgar E. Iglesias | signal handlers to inform the virtual CPU of exceptions. non zero
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285 | 4acb54ba | Edgar E. Iglesias | is returned if the signal was handled by the virtual CPU. */
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286 | 4acb54ba | Edgar E. Iglesias | int cpu_mb_signal_handler(int host_signum, void *pinfo, |
287 | 4acb54ba | Edgar E. Iglesias | void *puc);
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288 | 4acb54ba | Edgar E. Iglesias | |
289 | 4acb54ba | Edgar E. Iglesias | enum {
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290 | 4acb54ba | Edgar E. Iglesias | CC_OP_DYNAMIC, /* Use env->cc_op */
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291 | 4acb54ba | Edgar E. Iglesias | CC_OP_FLAGS, |
292 | 4acb54ba | Edgar E. Iglesias | CC_OP_CMP, |
293 | 4acb54ba | Edgar E. Iglesias | }; |
294 | 4acb54ba | Edgar E. Iglesias | |
295 | 4acb54ba | Edgar E. Iglesias | /* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
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296 | 4acb54ba | Edgar E. Iglesias | #define TARGET_PAGE_BITS 12 |
297 | 4acb54ba | Edgar E. Iglesias | #define MMAP_SHIFT TARGET_PAGE_BITS
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298 | 4acb54ba | Edgar E. Iglesias | |
299 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 32 |
300 | 52705890 | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS 32 |
301 | 52705890 | Richard Henderson | |
302 | b33ab1f7 | Andreas Färber | static inline CPUMBState *cpu_init(const char *cpu_model) |
303 | b33ab1f7 | Andreas Färber | { |
304 | b33ab1f7 | Andreas Färber | MicroBlazeCPU *cpu = cpu_mb_init(cpu_model); |
305 | b33ab1f7 | Andreas Färber | if (cpu == NULL) { |
306 | b33ab1f7 | Andreas Färber | return NULL; |
307 | b33ab1f7 | Andreas Färber | } |
308 | b33ab1f7 | Andreas Färber | return &cpu->env;
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309 | b33ab1f7 | Andreas Färber | } |
310 | b33ab1f7 | Andreas Färber | |
311 | 4acb54ba | Edgar E. Iglesias | #define cpu_exec cpu_mb_exec
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312 | 4acb54ba | Edgar E. Iglesias | #define cpu_gen_code cpu_mb_gen_code
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313 | 4acb54ba | Edgar E. Iglesias | #define cpu_signal_handler cpu_mb_signal_handler
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314 | 4acb54ba | Edgar E. Iglesias | |
315 | 4acb54ba | Edgar E. Iglesias | /* MMU modes definitions */
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316 | 4acb54ba | Edgar E. Iglesias | #define MMU_MODE0_SUFFIX _nommu
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317 | 4acb54ba | Edgar E. Iglesias | #define MMU_MODE1_SUFFIX _kernel
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318 | 4acb54ba | Edgar E. Iglesias | #define MMU_MODE2_SUFFIX _user
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319 | 4acb54ba | Edgar E. Iglesias | #define MMU_NOMMU_IDX 0 |
320 | 4acb54ba | Edgar E. Iglesias | #define MMU_KERNEL_IDX 1 |
321 | 4acb54ba | Edgar E. Iglesias | #define MMU_USER_IDX 2 |
322 | 4acb54ba | Edgar E. Iglesias | /* See NB_MMU_MODES further up the file. */
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323 | 4acb54ba | Edgar E. Iglesias | |
324 | 68cee38a | Andreas Färber | static inline int cpu_mmu_index (CPUMBState *env) |
325 | 4acb54ba | Edgar E. Iglesias | { |
326 | 4acb54ba | Edgar E. Iglesias | /* Are we in nommu mode?. */
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327 | 4acb54ba | Edgar E. Iglesias | if (!(env->sregs[SR_MSR] & MSR_VM))
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328 | 4acb54ba | Edgar E. Iglesias | return MMU_NOMMU_IDX;
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329 | 4acb54ba | Edgar E. Iglesias | |
330 | 4acb54ba | Edgar E. Iglesias | if (env->sregs[SR_MSR] & MSR_UM)
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331 | 4acb54ba | Edgar E. Iglesias | return MMU_USER_IDX;
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332 | 4acb54ba | Edgar E. Iglesias | return MMU_KERNEL_IDX;
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333 | 4acb54ba | Edgar E. Iglesias | } |
334 | 4acb54ba | Edgar E. Iglesias | |
335 | 68cee38a | Andreas Färber | int cpu_mb_handle_mmu_fault(CPUMBState *env, target_ulong address, int rw, |
336 | 97b348e7 | Blue Swirl | int mmu_idx);
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337 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_mb_handle_mmu_fault
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338 | 4acb54ba | Edgar E. Iglesias | |
339 | 68cee38a | Andreas Färber | static inline int cpu_interrupts_enabled(CPUMBState *env) |
340 | 4acb54ba | Edgar E. Iglesias | { |
341 | 4acb54ba | Edgar E. Iglesias | return env->sregs[SR_MSR] & MSR_IE;
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342 | 4acb54ba | Edgar E. Iglesias | } |
343 | 4acb54ba | Edgar E. Iglesias | |
344 | 022c62cb | Paolo Bonzini | #include "exec/cpu-all.h" |
345 | 4acb54ba | Edgar E. Iglesias | |
346 | 68cee38a | Andreas Färber | static inline target_ulong cpu_get_pc(CPUMBState *env) |
347 | 4acb54ba | Edgar E. Iglesias | { |
348 | 4acb54ba | Edgar E. Iglesias | return env->sregs[SR_PC];
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349 | 4acb54ba | Edgar E. Iglesias | } |
350 | 4acb54ba | Edgar E. Iglesias | |
351 | 68cee38a | Andreas Färber | static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc, |
352 | 4acb54ba | Edgar E. Iglesias | target_ulong *cs_base, int *flags)
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353 | 4acb54ba | Edgar E. Iglesias | { |
354 | 4acb54ba | Edgar E. Iglesias | *pc = env->sregs[SR_PC]; |
355 | 4acb54ba | Edgar E. Iglesias | *cs_base = 0;
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356 | fd1dc858 | Edgar E. Iglesias | *flags = (env->iflags & IFLAGS_TB_MASK) | |
357 | fd1dc858 | Edgar E. Iglesias | (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE)); |
358 | 4acb54ba | Edgar E. Iglesias | } |
359 | faed1c2a | Edgar E. Iglesias | |
360 | 3c7b48b7 | Paul Brook | #if !defined(CONFIG_USER_ONLY)
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361 | c658b94f | Andreas Färber | void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
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362 | c658b94f | Andreas Färber | bool is_write, bool is_exec, int is_asi, |
363 | c658b94f | Andreas Färber | unsigned size);
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364 | 4acb54ba | Edgar E. Iglesias | #endif
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365 | f081c76c | Blue Swirl | |
366 | 3993c6bd | Andreas Färber | static inline bool cpu_has_work(CPUState *cpu) |
367 | f081c76c | Blue Swirl | { |
368 | 259186a7 | Andreas Färber | return cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI);
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369 | f081c76c | Blue Swirl | } |
370 | f081c76c | Blue Swirl | |
371 | 022c62cb | Paolo Bonzini | #include "exec/exec-all.h" |
372 | f081c76c | Blue Swirl | |
373 | 3c7b48b7 | Paul Brook | #endif |