Statistics
| Branch: | Revision:

root / hw / fdc.c @ feef3102

History | View | Annotate | Download (61.5 kB)

1 8977f3c1 bellard
/*
2 890fa6be bellard
 * QEMU Floppy disk emulator (Intel 82078)
3 5fafdf24 ths
 *
4 3ccacc4a blueswir1
 * Copyright (c) 2003, 2007 Jocelyn Mayer
5 65cef780 blueswir1
 * Copyright (c) 2008 Herv? Poussineau
6 5fafdf24 ths
 *
7 8977f3c1 bellard
 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 8977f3c1 bellard
 * of this software and associated documentation files (the "Software"), to deal
9 8977f3c1 bellard
 * in the Software without restriction, including without limitation the rights
10 8977f3c1 bellard
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 8977f3c1 bellard
 * copies of the Software, and to permit persons to whom the Software is
12 8977f3c1 bellard
 * furnished to do so, subject to the following conditions:
13 8977f3c1 bellard
 *
14 8977f3c1 bellard
 * The above copyright notice and this permission notice shall be included in
15 8977f3c1 bellard
 * all copies or substantial portions of the Software.
16 8977f3c1 bellard
 *
17 8977f3c1 bellard
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 8977f3c1 bellard
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 8977f3c1 bellard
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 8977f3c1 bellard
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 8977f3c1 bellard
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 8977f3c1 bellard
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 8977f3c1 bellard
 * THE SOFTWARE.
24 8977f3c1 bellard
 */
25 e80cfcfc bellard
/*
26 e80cfcfc bellard
 * The controller is used in Sun4m systems in a slightly different
27 e80cfcfc bellard
 * way. There are changes in DOR register and DMA is not available.
28 e80cfcfc bellard
 */
29 f64ab228 Blue Swirl
30 87ecb68b pbrook
#include "hw.h"
31 87ecb68b pbrook
#include "fdc.h"
32 87ecb68b pbrook
#include "block.h"
33 87ecb68b pbrook
#include "qemu-timer.h"
34 87ecb68b pbrook
#include "isa.h"
35 f64ab228 Blue Swirl
#include "sysbus.h"
36 e8133762 Blue Swirl
#include "qdev-addr.h"
37 8977f3c1 bellard
38 8977f3c1 bellard
/********************************************************/
39 8977f3c1 bellard
/* debug Floppy devices */
40 8977f3c1 bellard
//#define DEBUG_FLOPPY
41 8977f3c1 bellard
42 8977f3c1 bellard
#ifdef DEBUG_FLOPPY
43 001faf32 Blue Swirl
#define FLOPPY_DPRINTF(fmt, ...)                                \
44 001faf32 Blue Swirl
    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)
45 8977f3c1 bellard
#else
46 001faf32 Blue Swirl
#define FLOPPY_DPRINTF(fmt, ...)
47 8977f3c1 bellard
#endif
48 8977f3c1 bellard
49 001faf32 Blue Swirl
#define FLOPPY_ERROR(fmt, ...)                                          \
50 001faf32 Blue Swirl
    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)
51 8977f3c1 bellard
52 8977f3c1 bellard
/********************************************************/
53 8977f3c1 bellard
/* Floppy drive emulation                               */
54 8977f3c1 bellard
55 cefec4f5 blueswir1
#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)
56 cefec4f5 blueswir1
#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))
57 cefec4f5 blueswir1
58 8977f3c1 bellard
/* Will always be a fixed parameter for us */
59 f2d81b33 blueswir1
#define FD_SECTOR_LEN          512
60 f2d81b33 blueswir1
#define FD_SECTOR_SC           2   /* Sector size code */
61 f2d81b33 blueswir1
#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */
62 8977f3c1 bellard
63 8977f3c1 bellard
/* Floppy disk drive emulation */
64 8977f3c1 bellard
typedef enum fdisk_type_t {
65 8977f3c1 bellard
    FDRIVE_DISK_288   = 0x01, /* 2.88 MB disk           */
66 8977f3c1 bellard
    FDRIVE_DISK_144   = 0x02, /* 1.44 MB disk           */
67 8977f3c1 bellard
    FDRIVE_DISK_720   = 0x03, /* 720 kB disk            */
68 baca51fa bellard
    FDRIVE_DISK_USER  = 0x04, /* User defined geometry  */
69 baca51fa bellard
    FDRIVE_DISK_NONE  = 0x05, /* No disk                */
70 8977f3c1 bellard
} fdisk_type_t;
71 8977f3c1 bellard
72 8977f3c1 bellard
typedef enum fdrive_type_t {
73 8977f3c1 bellard
    FDRIVE_DRV_144  = 0x00,   /* 1.44 MB 3"5 drive      */
74 8977f3c1 bellard
    FDRIVE_DRV_288  = 0x01,   /* 2.88 MB 3"5 drive      */
75 8977f3c1 bellard
    FDRIVE_DRV_120  = 0x02,   /* 1.2  MB 5"25 drive     */
76 8977f3c1 bellard
    FDRIVE_DRV_NONE = 0x03,   /* No drive connected     */
77 8977f3c1 bellard
} fdrive_type_t;
78 8977f3c1 bellard
79 baca51fa bellard
typedef enum fdisk_flags_t {
80 baca51fa bellard
    FDISK_DBL_SIDES  = 0x01,
81 baca51fa bellard
} fdisk_flags_t;
82 baca51fa bellard
83 8977f3c1 bellard
typedef struct fdrive_t {
84 8977f3c1 bellard
    BlockDriverState *bs;
85 8977f3c1 bellard
    /* Drive status */
86 8977f3c1 bellard
    fdrive_type_t drive;
87 8977f3c1 bellard
    uint8_t perpendicular;    /* 2.88 MB access mode    */
88 8977f3c1 bellard
    /* Position */
89 8977f3c1 bellard
    uint8_t head;
90 8977f3c1 bellard
    uint8_t track;
91 8977f3c1 bellard
    uint8_t sect;
92 8977f3c1 bellard
    /* Media */
93 baca51fa bellard
    fdisk_flags_t flags;
94 8977f3c1 bellard
    uint8_t last_sect;        /* Nb sector per track    */
95 8977f3c1 bellard
    uint8_t max_track;        /* Nb of tracks           */
96 baca51fa bellard
    uint16_t bps;             /* Bytes per sector       */
97 8977f3c1 bellard
    uint8_t ro;               /* Is read-only           */
98 8977f3c1 bellard
} fdrive_t;
99 8977f3c1 bellard
100 caed8802 bellard
static void fd_init (fdrive_t *drv, BlockDriverState *bs)
101 8977f3c1 bellard
{
102 8977f3c1 bellard
    /* Drive */
103 caed8802 bellard
    drv->bs = bs;
104 b939777c bellard
    drv->drive = FDRIVE_DRV_NONE;
105 8977f3c1 bellard
    drv->perpendicular = 0;
106 8977f3c1 bellard
    /* Disk */
107 baca51fa bellard
    drv->last_sect = 0;
108 8977f3c1 bellard
    drv->max_track = 0;
109 8977f3c1 bellard
}
110 8977f3c1 bellard
111 8977f3c1 bellard
static int _fd_sector (uint8_t head, uint8_t track,
112 4f431960 j_mayer
                       uint8_t sect, uint8_t last_sect)
113 8977f3c1 bellard
{
114 8977f3c1 bellard
    return (((track * 2) + head) * last_sect) + sect - 1;
115 8977f3c1 bellard
}
116 8977f3c1 bellard
117 8977f3c1 bellard
/* Returns current position, in sectors, for given drive */
118 8977f3c1 bellard
static int fd_sector (fdrive_t *drv)
119 8977f3c1 bellard
{
120 8977f3c1 bellard
    return _fd_sector(drv->head, drv->track, drv->sect, drv->last_sect);
121 8977f3c1 bellard
}
122 8977f3c1 bellard
123 77370520 blueswir1
/* Seek to a new position:
124 77370520 blueswir1
 * returns 0 if already on right track
125 77370520 blueswir1
 * returns 1 if track changed
126 77370520 blueswir1
 * returns 2 if track is invalid
127 77370520 blueswir1
 * returns 3 if sector is invalid
128 77370520 blueswir1
 * returns 4 if seek is disabled
129 77370520 blueswir1
 */
130 8977f3c1 bellard
static int fd_seek (fdrive_t *drv, uint8_t head, uint8_t track, uint8_t sect,
131 8977f3c1 bellard
                    int enable_seek)
132 8977f3c1 bellard
{
133 8977f3c1 bellard
    uint32_t sector;
134 baca51fa bellard
    int ret;
135 baca51fa bellard
136 baca51fa bellard
    if (track > drv->max_track ||
137 4f431960 j_mayer
        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {
138 ed5fd2cc bellard
        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
139 ed5fd2cc bellard
                       head, track, sect, 1,
140 ed5fd2cc bellard
                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
141 ed5fd2cc bellard
                       drv->max_track, drv->last_sect);
142 8977f3c1 bellard
        return 2;
143 8977f3c1 bellard
    }
144 8977f3c1 bellard
    if (sect > drv->last_sect) {
145 ed5fd2cc bellard
        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",
146 ed5fd2cc bellard
                       head, track, sect, 1,
147 ed5fd2cc bellard
                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,
148 ed5fd2cc bellard
                       drv->max_track, drv->last_sect);
149 8977f3c1 bellard
        return 3;
150 8977f3c1 bellard
    }
151 8977f3c1 bellard
    sector = _fd_sector(head, track, sect, drv->last_sect);
152 baca51fa bellard
    ret = 0;
153 8977f3c1 bellard
    if (sector != fd_sector(drv)) {
154 8977f3c1 bellard
#if 0
155 8977f3c1 bellard
        if (!enable_seek) {
156 8977f3c1 bellard
            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",
157 8977f3c1 bellard
                         head, track, sect, 1, drv->max_track, drv->last_sect);
158 8977f3c1 bellard
            return 4;
159 8977f3c1 bellard
        }
160 8977f3c1 bellard
#endif
161 8977f3c1 bellard
        drv->head = head;
162 4f431960 j_mayer
        if (drv->track != track)
163 4f431960 j_mayer
            ret = 1;
164 8977f3c1 bellard
        drv->track = track;
165 8977f3c1 bellard
        drv->sect = sect;
166 8977f3c1 bellard
    }
167 8977f3c1 bellard
168 baca51fa bellard
    return ret;
169 8977f3c1 bellard
}
170 8977f3c1 bellard
171 8977f3c1 bellard
/* Set drive back to track 0 */
172 8977f3c1 bellard
static void fd_recalibrate (fdrive_t *drv)
173 8977f3c1 bellard
{
174 8977f3c1 bellard
    FLOPPY_DPRINTF("recalibrate\n");
175 8977f3c1 bellard
    drv->head = 0;
176 8977f3c1 bellard
    drv->track = 0;
177 8977f3c1 bellard
    drv->sect = 1;
178 8977f3c1 bellard
}
179 8977f3c1 bellard
180 a541f297 bellard
/* Recognize floppy formats */
181 a541f297 bellard
typedef struct fd_format_t {
182 a541f297 bellard
    fdrive_type_t drive;
183 a541f297 bellard
    fdisk_type_t  disk;
184 a541f297 bellard
    uint8_t last_sect;
185 a541f297 bellard
    uint8_t max_track;
186 a541f297 bellard
    uint8_t max_head;
187 60fe76f3 ths
    const char *str;
188 a541f297 bellard
} fd_format_t;
189 a541f297 bellard
190 51a65271 blueswir1
static const fd_format_t fd_formats[] = {
191 a541f297 bellard
    /* First entry is default format */
192 a541f297 bellard
    /* 1.44 MB 3"1/2 floppy disks */
193 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 18, 80, 1, "1.44 MB 3\"1/2", },
194 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 20, 80, 1,  "1.6 MB 3\"1/2", },
195 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 80, 1, "1.68 MB 3\"1/2", },
196 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 82, 1, "1.72 MB 3\"1/2", },
197 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 21, 83, 1, "1.74 MB 3\"1/2", },
198 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 22, 80, 1, "1.76 MB 3\"1/2", },
199 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 23, 80, 1, "1.84 MB 3\"1/2", },
200 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_144, 24, 80, 1, "1.92 MB 3\"1/2", },
201 a541f297 bellard
    /* 2.88 MB 3"1/2 floppy disks */
202 a541f297 bellard
    { FDRIVE_DRV_288, FDRIVE_DISK_288, 36, 80, 1, "2.88 MB 3\"1/2", },
203 a541f297 bellard
    { FDRIVE_DRV_288, FDRIVE_DISK_288, 39, 80, 1, "3.12 MB 3\"1/2", },
204 a541f297 bellard
    { FDRIVE_DRV_288, FDRIVE_DISK_288, 40, 80, 1,  "3.2 MB 3\"1/2", },
205 a541f297 bellard
    { FDRIVE_DRV_288, FDRIVE_DISK_288, 44, 80, 1, "3.52 MB 3\"1/2", },
206 a541f297 bellard
    { FDRIVE_DRV_288, FDRIVE_DISK_288, 48, 80, 1, "3.84 MB 3\"1/2", },
207 a541f297 bellard
    /* 720 kB 3"1/2 floppy disks */
208 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 1,  "720 kB 3\"1/2", },
209 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 80, 1,  "800 kB 3\"1/2", },
210 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 82, 1,  "820 kB 3\"1/2", },
211 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_720, 10, 83, 1,  "830 kB 3\"1/2", },
212 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_720, 13, 80, 1, "1.04 MB 3\"1/2", },
213 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_720, 14, 80, 1, "1.12 MB 3\"1/2", },
214 a541f297 bellard
    /* 1.2 MB 5"1/4 floppy disks */
215 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 15, 80, 1,  "1.2 kB 5\"1/4", },
216 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 80, 1, "1.44 MB 5\"1/4", },
217 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 82, 1, "1.48 MB 5\"1/4", },
218 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 18, 83, 1, "1.49 MB 5\"1/4", },
219 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 20, 80, 1,  "1.6 MB 5\"1/4", },
220 a541f297 bellard
    /* 720 kB 5"1/4 floppy disks */
221 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 80, 1,  "720 kB 5\"1/4", },
222 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 11, 80, 1,  "880 kB 5\"1/4", },
223 a541f297 bellard
    /* 360 kB 5"1/4 floppy disks */
224 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 1,  "360 kB 5\"1/4", },
225 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288,  9, 40, 0,  "180 kB 5\"1/4", },
226 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 41, 1,  "410 kB 5\"1/4", },
227 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288, 10, 42, 1,  "420 kB 5\"1/4", },
228 5fafdf24 ths
    /* 320 kB 5"1/4 floppy disks */
229 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 1,  "320 kB 5\"1/4", },
230 a541f297 bellard
    { FDRIVE_DRV_120, FDRIVE_DISK_288,  8, 40, 0,  "160 kB 5\"1/4", },
231 a541f297 bellard
    /* 360 kB must match 5"1/4 better than 3"1/2... */
232 a541f297 bellard
    { FDRIVE_DRV_144, FDRIVE_DISK_720,  9, 80, 0,  "360 kB 3\"1/2", },
233 a541f297 bellard
    /* end */
234 a541f297 bellard
    { FDRIVE_DRV_NONE, FDRIVE_DISK_NONE, -1, -1, 0, NULL, },
235 a541f297 bellard
};
236 a541f297 bellard
237 8977f3c1 bellard
/* Revalidate a disk drive after a disk change */
238 caed8802 bellard
static void fd_revalidate (fdrive_t *drv)
239 8977f3c1 bellard
{
240 51a65271 blueswir1
    const fd_format_t *parse;
241 96b8f136 ths
    uint64_t nb_sectors, size;
242 a541f297 bellard
    int i, first_match, match;
243 baca51fa bellard
    int nb_heads, max_track, last_sect, ro;
244 8977f3c1 bellard
245 8977f3c1 bellard
    FLOPPY_DPRINTF("revalidate\n");
246 a541f297 bellard
    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {
247 4f431960 j_mayer
        ro = bdrv_is_read_only(drv->bs);
248 4f431960 j_mayer
        bdrv_get_geometry_hint(drv->bs, &nb_heads, &max_track, &last_sect);
249 4f431960 j_mayer
        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {
250 4f431960 j_mayer
            FLOPPY_DPRINTF("User defined disk (%d %d %d)",
251 ed5fd2cc bellard
                           nb_heads - 1, max_track, last_sect);
252 4f431960 j_mayer
        } else {
253 4f431960 j_mayer
            bdrv_get_geometry(drv->bs, &nb_sectors);
254 4f431960 j_mayer
            match = -1;
255 4f431960 j_mayer
            first_match = -1;
256 4f431960 j_mayer
            for (i = 0;; i++) {
257 4f431960 j_mayer
                parse = &fd_formats[i];
258 4f431960 j_mayer
                if (parse->drive == FDRIVE_DRV_NONE)
259 4f431960 j_mayer
                    break;
260 4f431960 j_mayer
                if (drv->drive == parse->drive ||
261 4f431960 j_mayer
                    drv->drive == FDRIVE_DRV_NONE) {
262 4f431960 j_mayer
                    size = (parse->max_head + 1) * parse->max_track *
263 4f431960 j_mayer
                        parse->last_sect;
264 4f431960 j_mayer
                    if (nb_sectors == size) {
265 4f431960 j_mayer
                        match = i;
266 4f431960 j_mayer
                        break;
267 4f431960 j_mayer
                    }
268 4f431960 j_mayer
                    if (first_match == -1)
269 4f431960 j_mayer
                        first_match = i;
270 4f431960 j_mayer
                }
271 4f431960 j_mayer
            }
272 4f431960 j_mayer
            if (match == -1) {
273 4f431960 j_mayer
                if (first_match == -1)
274 4f431960 j_mayer
                    match = 1;
275 4f431960 j_mayer
                else
276 4f431960 j_mayer
                    match = first_match;
277 4f431960 j_mayer
                parse = &fd_formats[match];
278 4f431960 j_mayer
            }
279 4f431960 j_mayer
            nb_heads = parse->max_head + 1;
280 4f431960 j_mayer
            max_track = parse->max_track;
281 4f431960 j_mayer
            last_sect = parse->last_sect;
282 4f431960 j_mayer
            drv->drive = parse->drive;
283 4f431960 j_mayer
            FLOPPY_DPRINTF("%s floppy disk (%d h %d t %d s) %s\n", parse->str,
284 ed5fd2cc bellard
                           nb_heads, max_track, last_sect, ro ? "ro" : "rw");
285 4f431960 j_mayer
        }
286 4f431960 j_mayer
        if (nb_heads == 1) {
287 4f431960 j_mayer
            drv->flags &= ~FDISK_DBL_SIDES;
288 4f431960 j_mayer
        } else {
289 4f431960 j_mayer
            drv->flags |= FDISK_DBL_SIDES;
290 4f431960 j_mayer
        }
291 4f431960 j_mayer
        drv->max_track = max_track;
292 4f431960 j_mayer
        drv->last_sect = last_sect;
293 4f431960 j_mayer
        drv->ro = ro;
294 8977f3c1 bellard
    } else {
295 4f431960 j_mayer
        FLOPPY_DPRINTF("No disk in drive\n");
296 baca51fa bellard
        drv->last_sect = 0;
297 4f431960 j_mayer
        drv->max_track = 0;
298 4f431960 j_mayer
        drv->flags &= ~FDISK_DBL_SIDES;
299 8977f3c1 bellard
    }
300 caed8802 bellard
}
301 caed8802 bellard
302 8977f3c1 bellard
/********************************************************/
303 4b19ec0c bellard
/* Intel 82078 floppy disk controller emulation          */
304 8977f3c1 bellard
305 baca51fa bellard
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq);
306 baca51fa bellard
static void fdctrl_reset_fifo (fdctrl_t *fdctrl);
307 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
308 85571bc7 bellard
                                    int dma_pos, int dma_len);
309 77370520 blueswir1
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0);
310 baca51fa bellard
311 8c6a4d77 blueswir1
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl);
312 baca51fa bellard
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl);
313 baca51fa bellard
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl);
314 baca51fa bellard
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value);
315 baca51fa bellard
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl);
316 baca51fa bellard
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value);
317 baca51fa bellard
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl);
318 baca51fa bellard
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value);
319 baca51fa bellard
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl);
320 baca51fa bellard
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value);
321 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl);
322 8977f3c1 bellard
323 8977f3c1 bellard
enum {
324 8977f3c1 bellard
    FD_DIR_WRITE   = 0,
325 8977f3c1 bellard
    FD_DIR_READ    = 1,
326 8977f3c1 bellard
    FD_DIR_SCANE   = 2,
327 8977f3c1 bellard
    FD_DIR_SCANL   = 3,
328 8977f3c1 bellard
    FD_DIR_SCANH   = 4,
329 8977f3c1 bellard
};
330 8977f3c1 bellard
331 8977f3c1 bellard
enum {
332 b9b3d225 blueswir1
    FD_STATE_MULTI  = 0x01,        /* multi track flag */
333 b9b3d225 blueswir1
    FD_STATE_FORMAT = 0x02,        /* format flag */
334 b9b3d225 blueswir1
    FD_STATE_SEEK   = 0x04,        /* seek flag */
335 8977f3c1 bellard
};
336 8977f3c1 bellard
337 9fea808a blueswir1
enum {
338 8c6a4d77 blueswir1
    FD_REG_SRA = 0x00,
339 8c6a4d77 blueswir1
    FD_REG_SRB = 0x01,
340 9fea808a blueswir1
    FD_REG_DOR = 0x02,
341 9fea808a blueswir1
    FD_REG_TDR = 0x03,
342 9fea808a blueswir1
    FD_REG_MSR = 0x04,
343 9fea808a blueswir1
    FD_REG_DSR = 0x04,
344 9fea808a blueswir1
    FD_REG_FIFO = 0x05,
345 9fea808a blueswir1
    FD_REG_DIR = 0x07,
346 9fea808a blueswir1
};
347 9fea808a blueswir1
348 9fea808a blueswir1
enum {
349 65cef780 blueswir1
    FD_CMD_READ_TRACK = 0x02,
350 9fea808a blueswir1
    FD_CMD_SPECIFY = 0x03,
351 9fea808a blueswir1
    FD_CMD_SENSE_DRIVE_STATUS = 0x04,
352 65cef780 blueswir1
    FD_CMD_WRITE = 0x05,
353 65cef780 blueswir1
    FD_CMD_READ = 0x06,
354 9fea808a blueswir1
    FD_CMD_RECALIBRATE = 0x07,
355 9fea808a blueswir1
    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,
356 65cef780 blueswir1
    FD_CMD_WRITE_DELETED = 0x09,
357 65cef780 blueswir1
    FD_CMD_READ_ID = 0x0a,
358 65cef780 blueswir1
    FD_CMD_READ_DELETED = 0x0c,
359 65cef780 blueswir1
    FD_CMD_FORMAT_TRACK = 0x0d,
360 9fea808a blueswir1
    FD_CMD_DUMPREG = 0x0e,
361 9fea808a blueswir1
    FD_CMD_SEEK = 0x0f,
362 9fea808a blueswir1
    FD_CMD_VERSION = 0x10,
363 65cef780 blueswir1
    FD_CMD_SCAN_EQUAL = 0x11,
364 9fea808a blueswir1
    FD_CMD_PERPENDICULAR_MODE = 0x12,
365 9fea808a blueswir1
    FD_CMD_CONFIGURE = 0x13,
366 65cef780 blueswir1
    FD_CMD_LOCK = 0x14,
367 65cef780 blueswir1
    FD_CMD_VERIFY = 0x16,
368 9fea808a blueswir1
    FD_CMD_POWERDOWN_MODE = 0x17,
369 9fea808a blueswir1
    FD_CMD_PART_ID = 0x18,
370 65cef780 blueswir1
    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,
371 65cef780 blueswir1
    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,
372 9fea808a blueswir1
    FD_CMD_SAVE = 0x2c,
373 9fea808a blueswir1
    FD_CMD_OPTION = 0x33,
374 9fea808a blueswir1
    FD_CMD_RESTORE = 0x4c,
375 9fea808a blueswir1
    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,
376 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,
377 9fea808a blueswir1
    FD_CMD_FORMAT_AND_WRITE = 0xcd,
378 9fea808a blueswir1
    FD_CMD_RELATIVE_SEEK_IN = 0xcf,
379 9fea808a blueswir1
};
380 9fea808a blueswir1
381 9fea808a blueswir1
enum {
382 9fea808a blueswir1
    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */
383 9fea808a blueswir1
    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */
384 9fea808a blueswir1
    FD_CONFIG_POLL  = 0x10, /* Poll enabled */
385 9fea808a blueswir1
    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */
386 9fea808a blueswir1
    FD_CONFIG_EIS   = 0x40, /* No implied seeks */
387 9fea808a blueswir1
};
388 9fea808a blueswir1
389 9fea808a blueswir1
enum {
390 9fea808a blueswir1
    FD_SR0_EQPMT    = 0x10,
391 9fea808a blueswir1
    FD_SR0_SEEK     = 0x20,
392 9fea808a blueswir1
    FD_SR0_ABNTERM  = 0x40,
393 9fea808a blueswir1
    FD_SR0_INVCMD   = 0x80,
394 9fea808a blueswir1
    FD_SR0_RDYCHG   = 0xc0,
395 9fea808a blueswir1
};
396 9fea808a blueswir1
397 9fea808a blueswir1
enum {
398 77370520 blueswir1
    FD_SR1_EC       = 0x80, /* End of cylinder */
399 77370520 blueswir1
};
400 77370520 blueswir1
401 77370520 blueswir1
enum {
402 77370520 blueswir1
    FD_SR2_SNS      = 0x04, /* Scan not satisfied */
403 77370520 blueswir1
    FD_SR2_SEH      = 0x08, /* Scan equal hit */
404 77370520 blueswir1
};
405 77370520 blueswir1
406 77370520 blueswir1
enum {
407 8c6a4d77 blueswir1
    FD_SRA_DIR      = 0x01,
408 8c6a4d77 blueswir1
    FD_SRA_nWP      = 0x02,
409 8c6a4d77 blueswir1
    FD_SRA_nINDX    = 0x04,
410 8c6a4d77 blueswir1
    FD_SRA_HDSEL    = 0x08,
411 8c6a4d77 blueswir1
    FD_SRA_nTRK0    = 0x10,
412 8c6a4d77 blueswir1
    FD_SRA_STEP     = 0x20,
413 8c6a4d77 blueswir1
    FD_SRA_nDRV2    = 0x40,
414 8c6a4d77 blueswir1
    FD_SRA_INTPEND  = 0x80,
415 8c6a4d77 blueswir1
};
416 8c6a4d77 blueswir1
417 8c6a4d77 blueswir1
enum {
418 8c6a4d77 blueswir1
    FD_SRB_MTR0     = 0x01,
419 8c6a4d77 blueswir1
    FD_SRB_MTR1     = 0x02,
420 8c6a4d77 blueswir1
    FD_SRB_WGATE    = 0x04,
421 8c6a4d77 blueswir1
    FD_SRB_RDATA    = 0x08,
422 8c6a4d77 blueswir1
    FD_SRB_WDATA    = 0x10,
423 8c6a4d77 blueswir1
    FD_SRB_DR0      = 0x20,
424 8c6a4d77 blueswir1
};
425 8c6a4d77 blueswir1
426 8c6a4d77 blueswir1
enum {
427 78ae820c blueswir1
#if MAX_FD == 4
428 78ae820c blueswir1
    FD_DOR_SELMASK  = 0x03,
429 78ae820c blueswir1
#else
430 9fea808a blueswir1
    FD_DOR_SELMASK  = 0x01,
431 78ae820c blueswir1
#endif
432 9fea808a blueswir1
    FD_DOR_nRESET   = 0x04,
433 9fea808a blueswir1
    FD_DOR_DMAEN    = 0x08,
434 9fea808a blueswir1
    FD_DOR_MOTEN0   = 0x10,
435 9fea808a blueswir1
    FD_DOR_MOTEN1   = 0x20,
436 9fea808a blueswir1
    FD_DOR_MOTEN2   = 0x40,
437 9fea808a blueswir1
    FD_DOR_MOTEN3   = 0x80,
438 9fea808a blueswir1
};
439 9fea808a blueswir1
440 9fea808a blueswir1
enum {
441 78ae820c blueswir1
#if MAX_FD == 4
442 9fea808a blueswir1
    FD_TDR_BOOTSEL  = 0x0c,
443 78ae820c blueswir1
#else
444 78ae820c blueswir1
    FD_TDR_BOOTSEL  = 0x04,
445 78ae820c blueswir1
#endif
446 9fea808a blueswir1
};
447 9fea808a blueswir1
448 9fea808a blueswir1
enum {
449 9fea808a blueswir1
    FD_DSR_DRATEMASK= 0x03,
450 9fea808a blueswir1
    FD_DSR_PWRDOWN  = 0x40,
451 9fea808a blueswir1
    FD_DSR_SWRESET  = 0x80,
452 9fea808a blueswir1
};
453 9fea808a blueswir1
454 9fea808a blueswir1
enum {
455 9fea808a blueswir1
    FD_MSR_DRV0BUSY = 0x01,
456 9fea808a blueswir1
    FD_MSR_DRV1BUSY = 0x02,
457 9fea808a blueswir1
    FD_MSR_DRV2BUSY = 0x04,
458 9fea808a blueswir1
    FD_MSR_DRV3BUSY = 0x08,
459 9fea808a blueswir1
    FD_MSR_CMDBUSY  = 0x10,
460 9fea808a blueswir1
    FD_MSR_NONDMA   = 0x20,
461 9fea808a blueswir1
    FD_MSR_DIO      = 0x40,
462 9fea808a blueswir1
    FD_MSR_RQM      = 0x80,
463 9fea808a blueswir1
};
464 9fea808a blueswir1
465 9fea808a blueswir1
enum {
466 9fea808a blueswir1
    FD_DIR_DSKCHG   = 0x80,
467 9fea808a blueswir1
};
468 9fea808a blueswir1
469 8977f3c1 bellard
#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)
470 8977f3c1 bellard
#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)
471 baca51fa bellard
#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)
472 8977f3c1 bellard
473 baca51fa bellard
struct fdctrl_t {
474 4b19ec0c bellard
    /* Controller's identification */
475 8977f3c1 bellard
    uint8_t version;
476 8977f3c1 bellard
    /* HW */
477 d537cf6c pbrook
    qemu_irq irq;
478 8977f3c1 bellard
    int dma_chann;
479 4b19ec0c bellard
    /* Controller state */
480 ed5fd2cc bellard
    QEMUTimer *result_timer;
481 8c6a4d77 blueswir1
    uint8_t sra;
482 8c6a4d77 blueswir1
    uint8_t srb;
483 368df94d blueswir1
    uint8_t dor;
484 d7a6c270 Juan Quintela
    uint8_t dor_vmstate; /* only used as temp during vmstate */
485 46d3233b blueswir1
    uint8_t tdr;
486 b9b3d225 blueswir1
    uint8_t dsr;
487 368df94d blueswir1
    uint8_t msr;
488 8977f3c1 bellard
    uint8_t cur_drv;
489 77370520 blueswir1
    uint8_t status0;
490 77370520 blueswir1
    uint8_t status1;
491 77370520 blueswir1
    uint8_t status2;
492 8977f3c1 bellard
    /* Command FIFO */
493 33f00271 balrog
    uint8_t *fifo;
494 d7a6c270 Juan Quintela
    int32_t fifo_size;
495 8977f3c1 bellard
    uint32_t data_pos;
496 8977f3c1 bellard
    uint32_t data_len;
497 8977f3c1 bellard
    uint8_t data_state;
498 8977f3c1 bellard
    uint8_t data_dir;
499 890fa6be bellard
    uint8_t eot; /* last wanted sector */
500 8977f3c1 bellard
    /* States kept only to be returned back */
501 8977f3c1 bellard
    /* Timers state */
502 8977f3c1 bellard
    uint8_t timer0;
503 8977f3c1 bellard
    uint8_t timer1;
504 8977f3c1 bellard
    /* precompensation */
505 8977f3c1 bellard
    uint8_t precomp_trk;
506 8977f3c1 bellard
    uint8_t config;
507 8977f3c1 bellard
    uint8_t lock;
508 8977f3c1 bellard
    /* Power down config (also with status regB access mode */
509 8977f3c1 bellard
    uint8_t pwrd;
510 741402f9 blueswir1
    /* Sun4m quirks? */
511 a06e5a3c blueswir1
    int sun4m;
512 8977f3c1 bellard
    /* Floppy drives */
513 d7a6c270 Juan Quintela
    uint8_t num_floppies;
514 78ae820c blueswir1
    fdrive_t drives[MAX_FD];
515 f2d81b33 blueswir1
    int reset_sensei;
516 baca51fa bellard
};
517 baca51fa bellard
518 8baf73ad Gerd Hoffmann
typedef struct fdctrl_sysbus_t {
519 8baf73ad Gerd Hoffmann
    SysBusDevice busdev;
520 8baf73ad Gerd Hoffmann
    struct fdctrl_t state;
521 8baf73ad Gerd Hoffmann
} fdctrl_sysbus_t;
522 8baf73ad Gerd Hoffmann
523 8baf73ad Gerd Hoffmann
typedef struct fdctrl_isabus_t {
524 8baf73ad Gerd Hoffmann
    ISADevice busdev;
525 8baf73ad Gerd Hoffmann
    struct fdctrl_t state;
526 8baf73ad Gerd Hoffmann
} fdctrl_isabus_t;
527 8baf73ad Gerd Hoffmann
528 baca51fa bellard
static uint32_t fdctrl_read (void *opaque, uint32_t reg)
529 baca51fa bellard
{
530 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
531 baca51fa bellard
    uint32_t retval;
532 baca51fa bellard
533 e64d7d59 blueswir1
    switch (reg) {
534 8c6a4d77 blueswir1
    case FD_REG_SRA:
535 8c6a4d77 blueswir1
        retval = fdctrl_read_statusA(fdctrl);
536 4f431960 j_mayer
        break;
537 8c6a4d77 blueswir1
    case FD_REG_SRB:
538 4f431960 j_mayer
        retval = fdctrl_read_statusB(fdctrl);
539 4f431960 j_mayer
        break;
540 9fea808a blueswir1
    case FD_REG_DOR:
541 4f431960 j_mayer
        retval = fdctrl_read_dor(fdctrl);
542 4f431960 j_mayer
        break;
543 9fea808a blueswir1
    case FD_REG_TDR:
544 baca51fa bellard
        retval = fdctrl_read_tape(fdctrl);
545 4f431960 j_mayer
        break;
546 9fea808a blueswir1
    case FD_REG_MSR:
547 baca51fa bellard
        retval = fdctrl_read_main_status(fdctrl);
548 4f431960 j_mayer
        break;
549 9fea808a blueswir1
    case FD_REG_FIFO:
550 baca51fa bellard
        retval = fdctrl_read_data(fdctrl);
551 4f431960 j_mayer
        break;
552 9fea808a blueswir1
    case FD_REG_DIR:
553 baca51fa bellard
        retval = fdctrl_read_dir(fdctrl);
554 4f431960 j_mayer
        break;
555 a541f297 bellard
    default:
556 4f431960 j_mayer
        retval = (uint32_t)(-1);
557 4f431960 j_mayer
        break;
558 a541f297 bellard
    }
559 ed5fd2cc bellard
    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);
560 baca51fa bellard
561 baca51fa bellard
    return retval;
562 baca51fa bellard
}
563 baca51fa bellard
564 baca51fa bellard
static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)
565 baca51fa bellard
{
566 baca51fa bellard
    fdctrl_t *fdctrl = opaque;
567 baca51fa bellard
568 ed5fd2cc bellard
    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);
569 ed5fd2cc bellard
570 e64d7d59 blueswir1
    switch (reg) {
571 9fea808a blueswir1
    case FD_REG_DOR:
572 4f431960 j_mayer
        fdctrl_write_dor(fdctrl, value);
573 4f431960 j_mayer
        break;
574 9fea808a blueswir1
    case FD_REG_TDR:
575 baca51fa bellard
        fdctrl_write_tape(fdctrl, value);
576 4f431960 j_mayer
        break;
577 9fea808a blueswir1
    case FD_REG_DSR:
578 baca51fa bellard
        fdctrl_write_rate(fdctrl, value);
579 4f431960 j_mayer
        break;
580 9fea808a blueswir1
    case FD_REG_FIFO:
581 baca51fa bellard
        fdctrl_write_data(fdctrl, value);
582 4f431960 j_mayer
        break;
583 a541f297 bellard
    default:
584 4f431960 j_mayer
        break;
585 a541f297 bellard
    }
586 baca51fa bellard
}
587 baca51fa bellard
588 e64d7d59 blueswir1
static uint32_t fdctrl_read_port (void *opaque, uint32_t reg)
589 e64d7d59 blueswir1
{
590 e64d7d59 blueswir1
    return fdctrl_read(opaque, reg & 7);
591 e64d7d59 blueswir1
}
592 e64d7d59 blueswir1
593 e64d7d59 blueswir1
static void fdctrl_write_port (void *opaque, uint32_t reg, uint32_t value)
594 e64d7d59 blueswir1
{
595 e64d7d59 blueswir1
    fdctrl_write(opaque, reg & 7, value);
596 e64d7d59 blueswir1
}
597 e64d7d59 blueswir1
598 62a46c61 bellard
static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)
599 62a46c61 bellard
{
600 5dcb6b91 blueswir1
    return fdctrl_read(opaque, (uint32_t)reg);
601 62a46c61 bellard
}
602 62a46c61 bellard
603 5fafdf24 ths
static void fdctrl_write_mem (void *opaque,
604 62a46c61 bellard
                              target_phys_addr_t reg, uint32_t value)
605 62a46c61 bellard
{
606 5dcb6b91 blueswir1
    fdctrl_write(opaque, (uint32_t)reg, value);
607 62a46c61 bellard
}
608 62a46c61 bellard
609 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {
610 62a46c61 bellard
    fdctrl_read_mem,
611 62a46c61 bellard
    fdctrl_read_mem,
612 62a46c61 bellard
    fdctrl_read_mem,
613 e80cfcfc bellard
};
614 e80cfcfc bellard
615 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {
616 62a46c61 bellard
    fdctrl_write_mem,
617 62a46c61 bellard
    fdctrl_write_mem,
618 62a46c61 bellard
    fdctrl_write_mem,
619 e80cfcfc bellard
};
620 e80cfcfc bellard
621 d60efc6b Blue Swirl
static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {
622 7c560456 blueswir1
    fdctrl_read_mem,
623 7c560456 blueswir1
    NULL,
624 7c560456 blueswir1
    NULL,
625 7c560456 blueswir1
};
626 7c560456 blueswir1
627 d60efc6b Blue Swirl
static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {
628 7c560456 blueswir1
    fdctrl_write_mem,
629 7c560456 blueswir1
    NULL,
630 7c560456 blueswir1
    NULL,
631 7c560456 blueswir1
};
632 7c560456 blueswir1
633 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdrive = {
634 d7a6c270 Juan Quintela
    .name = "fdrive",
635 d7a6c270 Juan Quintela
    .version_id = 1,
636 d7a6c270 Juan Quintela
    .minimum_version_id = 1,
637 d7a6c270 Juan Quintela
    .minimum_version_id_old = 1,
638 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
639 d7a6c270 Juan Quintela
        VMSTATE_UINT8(head, fdrive_t),
640 d7a6c270 Juan Quintela
        VMSTATE_UINT8(track, fdrive_t),
641 d7a6c270 Juan Quintela
        VMSTATE_UINT8(sect, fdrive_t),
642 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
643 d7a6c270 Juan Quintela
    }
644 d7a6c270 Juan Quintela
};
645 3ccacc4a blueswir1
646 d7a6c270 Juan Quintela
static void fdc_pre_save(const void *opaque)
647 3ccacc4a blueswir1
{
648 d7a6c270 Juan Quintela
    fdctrl_t *s = (void *)opaque;
649 3ccacc4a blueswir1
650 d7a6c270 Juan Quintela
    s->dor_vmstate = s->dor | GET_CUR_DRV(s);
651 3ccacc4a blueswir1
}
652 3ccacc4a blueswir1
653 d7a6c270 Juan Quintela
static int fdc_post_load(void *opaque)
654 3ccacc4a blueswir1
{
655 d7a6c270 Juan Quintela
    fdctrl_t *s = opaque;
656 3ccacc4a blueswir1
657 d7a6c270 Juan Quintela
    SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);
658 d7a6c270 Juan Quintela
    s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;
659 3ccacc4a blueswir1
    return 0;
660 3ccacc4a blueswir1
}
661 3ccacc4a blueswir1
662 d7a6c270 Juan Quintela
static const VMStateDescription vmstate_fdc = {
663 d7a6c270 Juan Quintela
    .name = "fdc",
664 d7a6c270 Juan Quintela
    .version_id = 2,
665 d7a6c270 Juan Quintela
    .minimum_version_id = 2,
666 d7a6c270 Juan Quintela
    .minimum_version_id_old = 2,
667 d7a6c270 Juan Quintela
    .pre_save = fdc_pre_save,
668 d7a6c270 Juan Quintela
    .post_load = fdc_post_load,
669 d7a6c270 Juan Quintela
    .fields      = (VMStateField []) {
670 d7a6c270 Juan Quintela
        /* Controller State */
671 d7a6c270 Juan Quintela
        VMSTATE_UINT8(sra, fdctrl_t),
672 d7a6c270 Juan Quintela
        VMSTATE_UINT8(srb, fdctrl_t),
673 d7a6c270 Juan Quintela
        VMSTATE_UINT8(dor_vmstate, fdctrl_t),
674 d7a6c270 Juan Quintela
        VMSTATE_UINT8(tdr, fdctrl_t),
675 d7a6c270 Juan Quintela
        VMSTATE_UINT8(dsr, fdctrl_t),
676 d7a6c270 Juan Quintela
        VMSTATE_UINT8(msr, fdctrl_t),
677 d7a6c270 Juan Quintela
        VMSTATE_UINT8(status0, fdctrl_t),
678 d7a6c270 Juan Quintela
        VMSTATE_UINT8(status1, fdctrl_t),
679 d7a6c270 Juan Quintela
        VMSTATE_UINT8(status2, fdctrl_t),
680 d7a6c270 Juan Quintela
        /* Command FIFO */
681 d7a6c270 Juan Quintela
        VMSTATE_VARRAY(fifo, fdctrl_t, fifo_size, 0, vmstate_info_uint8, uint8),
682 d7a6c270 Juan Quintela
        VMSTATE_UINT32(data_pos, fdctrl_t),
683 d7a6c270 Juan Quintela
        VMSTATE_UINT32(data_len, fdctrl_t),
684 d7a6c270 Juan Quintela
        VMSTATE_UINT8(data_state, fdctrl_t),
685 d7a6c270 Juan Quintela
        VMSTATE_UINT8(data_dir, fdctrl_t),
686 d7a6c270 Juan Quintela
        VMSTATE_UINT8(eot, fdctrl_t),
687 d7a6c270 Juan Quintela
        /* States kept only to be returned back */
688 d7a6c270 Juan Quintela
        VMSTATE_UINT8(timer0, fdctrl_t),
689 d7a6c270 Juan Quintela
        VMSTATE_UINT8(timer1, fdctrl_t),
690 d7a6c270 Juan Quintela
        VMSTATE_UINT8(precomp_trk, fdctrl_t),
691 d7a6c270 Juan Quintela
        VMSTATE_UINT8(config, fdctrl_t),
692 d7a6c270 Juan Quintela
        VMSTATE_UINT8(lock, fdctrl_t),
693 d7a6c270 Juan Quintela
        VMSTATE_UINT8(pwrd, fdctrl_t),
694 d7a6c270 Juan Quintela
        VMSTATE_UINT8_EQUAL(num_floppies, fdctrl_t),
695 d7a6c270 Juan Quintela
        VMSTATE_STRUCT_ARRAY(drives, fdctrl_t, MAX_FD, 1,
696 d7a6c270 Juan Quintela
                             vmstate_fdrive, fdrive_t),
697 d7a6c270 Juan Quintela
        VMSTATE_END_OF_LIST()
698 78ae820c blueswir1
    }
699 d7a6c270 Juan Quintela
};
700 3ccacc4a blueswir1
701 3ccacc4a blueswir1
static void fdctrl_external_reset(void *opaque)
702 3ccacc4a blueswir1
{
703 3ccacc4a blueswir1
    fdctrl_t *s = opaque;
704 3ccacc4a blueswir1
705 3ccacc4a blueswir1
    fdctrl_reset(s, 0);
706 3ccacc4a blueswir1
}
707 3ccacc4a blueswir1
708 2be17ebd blueswir1
static void fdctrl_handle_tc(void *opaque, int irq, int level)
709 2be17ebd blueswir1
{
710 2be17ebd blueswir1
    //fdctrl_t *s = opaque;
711 2be17ebd blueswir1
712 2be17ebd blueswir1
    if (level) {
713 2be17ebd blueswir1
        // XXX
714 2be17ebd blueswir1
        FLOPPY_DPRINTF("TC pulsed\n");
715 2be17ebd blueswir1
    }
716 2be17ebd blueswir1
}
717 2be17ebd blueswir1
718 baca51fa bellard
/* XXX: may change if moved to bdrv */
719 baca51fa bellard
int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num)
720 caed8802 bellard
{
721 baca51fa bellard
    return fdctrl->drives[drive_num].drive;
722 8977f3c1 bellard
}
723 8977f3c1 bellard
724 8977f3c1 bellard
/* Change IRQ state */
725 baca51fa bellard
static void fdctrl_reset_irq (fdctrl_t *fdctrl)
726 8977f3c1 bellard
{
727 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND))
728 8c6a4d77 blueswir1
        return;
729 ed5fd2cc bellard
    FLOPPY_DPRINTF("Reset interrupt\n");
730 d537cf6c pbrook
    qemu_set_irq(fdctrl->irq, 0);
731 8c6a4d77 blueswir1
    fdctrl->sra &= ~FD_SRA_INTPEND;
732 8977f3c1 bellard
}
733 8977f3c1 bellard
734 77370520 blueswir1
static void fdctrl_raise_irq (fdctrl_t *fdctrl, uint8_t status0)
735 8977f3c1 bellard
{
736 b9b3d225 blueswir1
    /* Sparc mutation */
737 b9b3d225 blueswir1
    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {
738 b9b3d225 blueswir1
        /* XXX: not sure */
739 b9b3d225 blueswir1
        fdctrl->msr &= ~FD_MSR_CMDBUSY;
740 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
741 77370520 blueswir1
        fdctrl->status0 = status0;
742 4f431960 j_mayer
        return;
743 6f7e9aec bellard
    }
744 8c6a4d77 blueswir1
    if (!(fdctrl->sra & FD_SRA_INTPEND)) {
745 d537cf6c pbrook
        qemu_set_irq(fdctrl->irq, 1);
746 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_INTPEND;
747 8977f3c1 bellard
    }
748 f2d81b33 blueswir1
    fdctrl->reset_sensei = 0;
749 77370520 blueswir1
    fdctrl->status0 = status0;
750 77370520 blueswir1
    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);
751 8977f3c1 bellard
}
752 8977f3c1 bellard
753 4b19ec0c bellard
/* Reset controller */
754 baca51fa bellard
static void fdctrl_reset (fdctrl_t *fdctrl, int do_irq)
755 8977f3c1 bellard
{
756 8977f3c1 bellard
    int i;
757 8977f3c1 bellard
758 4b19ec0c bellard
    FLOPPY_DPRINTF("reset controller\n");
759 baca51fa bellard
    fdctrl_reset_irq(fdctrl);
760 4b19ec0c bellard
    /* Initialise controller */
761 8c6a4d77 blueswir1
    fdctrl->sra = 0;
762 8c6a4d77 blueswir1
    fdctrl->srb = 0xc0;
763 8c6a4d77 blueswir1
    if (!fdctrl->drives[1].bs)
764 8c6a4d77 blueswir1
        fdctrl->sra |= FD_SRA_nDRV2;
765 baca51fa bellard
    fdctrl->cur_drv = 0;
766 1c346df2 blueswir1
    fdctrl->dor = FD_DOR_nRESET;
767 368df94d blueswir1
    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;
768 b9b3d225 blueswir1
    fdctrl->msr = FD_MSR_RQM;
769 8977f3c1 bellard
    /* FIFO state */
770 baca51fa bellard
    fdctrl->data_pos = 0;
771 baca51fa bellard
    fdctrl->data_len = 0;
772 b9b3d225 blueswir1
    fdctrl->data_state = 0;
773 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
774 8977f3c1 bellard
    for (i = 0; i < MAX_FD; i++)
775 1c346df2 blueswir1
        fd_recalibrate(&fdctrl->drives[i]);
776 baca51fa bellard
    fdctrl_reset_fifo(fdctrl);
777 77370520 blueswir1
    if (do_irq) {
778 9fea808a blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);
779 f2d81b33 blueswir1
        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;
780 77370520 blueswir1
    }
781 baca51fa bellard
}
782 baca51fa bellard
783 baca51fa bellard
static inline fdrive_t *drv0 (fdctrl_t *fdctrl)
784 baca51fa bellard
{
785 46d3233b blueswir1
    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];
786 baca51fa bellard
}
787 baca51fa bellard
788 baca51fa bellard
static inline fdrive_t *drv1 (fdctrl_t *fdctrl)
789 baca51fa bellard
{
790 46d3233b blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))
791 46d3233b blueswir1
        return &fdctrl->drives[1];
792 46d3233b blueswir1
    else
793 46d3233b blueswir1
        return &fdctrl->drives[0];
794 baca51fa bellard
}
795 baca51fa bellard
796 78ae820c blueswir1
#if MAX_FD == 4
797 78ae820c blueswir1
static inline fdrive_t *drv2 (fdctrl_t *fdctrl)
798 78ae820c blueswir1
{
799 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))
800 78ae820c blueswir1
        return &fdctrl->drives[2];
801 78ae820c blueswir1
    else
802 78ae820c blueswir1
        return &fdctrl->drives[1];
803 78ae820c blueswir1
}
804 78ae820c blueswir1
805 78ae820c blueswir1
static inline fdrive_t *drv3 (fdctrl_t *fdctrl)
806 78ae820c blueswir1
{
807 78ae820c blueswir1
    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))
808 78ae820c blueswir1
        return &fdctrl->drives[3];
809 78ae820c blueswir1
    else
810 78ae820c blueswir1
        return &fdctrl->drives[2];
811 78ae820c blueswir1
}
812 78ae820c blueswir1
#endif
813 78ae820c blueswir1
814 baca51fa bellard
static fdrive_t *get_cur_drv (fdctrl_t *fdctrl)
815 baca51fa bellard
{
816 78ae820c blueswir1
    switch (fdctrl->cur_drv) {
817 78ae820c blueswir1
        case 0: return drv0(fdctrl);
818 78ae820c blueswir1
        case 1: return drv1(fdctrl);
819 78ae820c blueswir1
#if MAX_FD == 4
820 78ae820c blueswir1
        case 2: return drv2(fdctrl);
821 78ae820c blueswir1
        case 3: return drv3(fdctrl);
822 78ae820c blueswir1
#endif
823 78ae820c blueswir1
        default: return NULL;
824 78ae820c blueswir1
    }
825 8977f3c1 bellard
}
826 8977f3c1 bellard
827 8c6a4d77 blueswir1
/* Status A register : 0x00 (read-only) */
828 8c6a4d77 blueswir1
static uint32_t fdctrl_read_statusA (fdctrl_t *fdctrl)
829 8c6a4d77 blueswir1
{
830 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->sra;
831 8c6a4d77 blueswir1
832 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);
833 8c6a4d77 blueswir1
834 8c6a4d77 blueswir1
    return retval;
835 8c6a4d77 blueswir1
}
836 8c6a4d77 blueswir1
837 8977f3c1 bellard
/* Status B register : 0x01 (read-only) */
838 baca51fa bellard
static uint32_t fdctrl_read_statusB (fdctrl_t *fdctrl)
839 8977f3c1 bellard
{
840 8c6a4d77 blueswir1
    uint32_t retval = fdctrl->srb;
841 8c6a4d77 blueswir1
842 8c6a4d77 blueswir1
    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);
843 8c6a4d77 blueswir1
844 8c6a4d77 blueswir1
    return retval;
845 8977f3c1 bellard
}
846 8977f3c1 bellard
847 8977f3c1 bellard
/* Digital output register : 0x02 */
848 baca51fa bellard
static uint32_t fdctrl_read_dor (fdctrl_t *fdctrl)
849 8977f3c1 bellard
{
850 1c346df2 blueswir1
    uint32_t retval = fdctrl->dor;
851 8977f3c1 bellard
852 8977f3c1 bellard
    /* Selected drive */
853 baca51fa bellard
    retval |= fdctrl->cur_drv;
854 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);
855 8977f3c1 bellard
856 8977f3c1 bellard
    return retval;
857 8977f3c1 bellard
}
858 8977f3c1 bellard
859 baca51fa bellard
static void fdctrl_write_dor (fdctrl_t *fdctrl, uint32_t value)
860 8977f3c1 bellard
{
861 8977f3c1 bellard
    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);
862 8c6a4d77 blueswir1
863 8c6a4d77 blueswir1
    /* Motors */
864 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN0)
865 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR0;
866 8c6a4d77 blueswir1
    else
867 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR0;
868 8c6a4d77 blueswir1
    if (value & FD_DOR_MOTEN1)
869 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_MTR1;
870 8c6a4d77 blueswir1
    else
871 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_MTR1;
872 8c6a4d77 blueswir1
873 8c6a4d77 blueswir1
    /* Drive */
874 8c6a4d77 blueswir1
    if (value & 1)
875 8c6a4d77 blueswir1
        fdctrl->srb |= FD_SRB_DR0;
876 8c6a4d77 blueswir1
    else
877 8c6a4d77 blueswir1
        fdctrl->srb &= ~FD_SRB_DR0;
878 8c6a4d77 blueswir1
879 8977f3c1 bellard
    /* Reset */
880 9fea808a blueswir1
    if (!(value & FD_DOR_nRESET)) {
881 1c346df2 blueswir1
        if (fdctrl->dor & FD_DOR_nRESET) {
882 4b19ec0c bellard
            FLOPPY_DPRINTF("controller enter RESET state\n");
883 8977f3c1 bellard
        }
884 8977f3c1 bellard
    } else {
885 1c346df2 blueswir1
        if (!(fdctrl->dor & FD_DOR_nRESET)) {
886 4b19ec0c bellard
            FLOPPY_DPRINTF("controller out of RESET state\n");
887 fb6cf1d0 bellard
            fdctrl_reset(fdctrl, 1);
888 b9b3d225 blueswir1
            fdctrl->dsr &= ~FD_DSR_PWRDOWN;
889 8977f3c1 bellard
        }
890 8977f3c1 bellard
    }
891 8977f3c1 bellard
    /* Selected drive */
892 9fea808a blueswir1
    fdctrl->cur_drv = value & FD_DOR_SELMASK;
893 368df94d blueswir1
894 368df94d blueswir1
    fdctrl->dor = value;
895 8977f3c1 bellard
}
896 8977f3c1 bellard
897 8977f3c1 bellard
/* Tape drive register : 0x03 */
898 baca51fa bellard
static uint32_t fdctrl_read_tape (fdctrl_t *fdctrl)
899 8977f3c1 bellard
{
900 46d3233b blueswir1
    uint32_t retval = fdctrl->tdr;
901 8977f3c1 bellard
902 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);
903 8977f3c1 bellard
904 8977f3c1 bellard
    return retval;
905 8977f3c1 bellard
}
906 8977f3c1 bellard
907 baca51fa bellard
static void fdctrl_write_tape (fdctrl_t *fdctrl, uint32_t value)
908 8977f3c1 bellard
{
909 8977f3c1 bellard
    /* Reset mode */
910 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
911 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
912 8977f3c1 bellard
        return;
913 8977f3c1 bellard
    }
914 8977f3c1 bellard
    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);
915 8977f3c1 bellard
    /* Disk boot selection indicator */
916 46d3233b blueswir1
    fdctrl->tdr = value & FD_TDR_BOOTSEL;
917 8977f3c1 bellard
    /* Tape indicators: never allow */
918 8977f3c1 bellard
}
919 8977f3c1 bellard
920 8977f3c1 bellard
/* Main status register : 0x04 (read) */
921 baca51fa bellard
static uint32_t fdctrl_read_main_status (fdctrl_t *fdctrl)
922 8977f3c1 bellard
{
923 b9b3d225 blueswir1
    uint32_t retval = fdctrl->msr;
924 8977f3c1 bellard
925 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
926 1c346df2 blueswir1
    fdctrl->dor |= FD_DOR_nRESET;
927 b9b3d225 blueswir1
928 8977f3c1 bellard
    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);
929 8977f3c1 bellard
930 8977f3c1 bellard
    return retval;
931 8977f3c1 bellard
}
932 8977f3c1 bellard
933 8977f3c1 bellard
/* Data select rate register : 0x04 (write) */
934 baca51fa bellard
static void fdctrl_write_rate (fdctrl_t *fdctrl, uint32_t value)
935 8977f3c1 bellard
{
936 8977f3c1 bellard
    /* Reset mode */
937 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
938 4f431960 j_mayer
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
939 4f431960 j_mayer
        return;
940 4f431960 j_mayer
    }
941 8977f3c1 bellard
    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);
942 8977f3c1 bellard
    /* Reset: autoclear */
943 9fea808a blueswir1
    if (value & FD_DSR_SWRESET) {
944 1c346df2 blueswir1
        fdctrl->dor &= ~FD_DOR_nRESET;
945 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
946 1c346df2 blueswir1
        fdctrl->dor |= FD_DOR_nRESET;
947 8977f3c1 bellard
    }
948 9fea808a blueswir1
    if (value & FD_DSR_PWRDOWN) {
949 baca51fa bellard
        fdctrl_reset(fdctrl, 1);
950 8977f3c1 bellard
    }
951 b9b3d225 blueswir1
    fdctrl->dsr = value;
952 8977f3c1 bellard
}
953 8977f3c1 bellard
954 ea185bbd bellard
static int fdctrl_media_changed(fdrive_t *drv)
955 ea185bbd bellard
{
956 ea185bbd bellard
    int ret;
957 4f431960 j_mayer
958 5fafdf24 ths
    if (!drv->bs)
959 ea185bbd bellard
        return 0;
960 ea185bbd bellard
    ret = bdrv_media_changed(drv->bs);
961 ea185bbd bellard
    if (ret) {
962 ea185bbd bellard
        fd_revalidate(drv);
963 ea185bbd bellard
    }
964 ea185bbd bellard
    return ret;
965 ea185bbd bellard
}
966 ea185bbd bellard
967 8977f3c1 bellard
/* Digital input register : 0x07 (read-only) */
968 baca51fa bellard
static uint32_t fdctrl_read_dir (fdctrl_t *fdctrl)
969 8977f3c1 bellard
{
970 8977f3c1 bellard
    uint32_t retval = 0;
971 8977f3c1 bellard
972 78ae820c blueswir1
    if (fdctrl_media_changed(drv0(fdctrl))
973 78ae820c blueswir1
     || fdctrl_media_changed(drv1(fdctrl))
974 78ae820c blueswir1
#if MAX_FD == 4
975 78ae820c blueswir1
     || fdctrl_media_changed(drv2(fdctrl))
976 78ae820c blueswir1
     || fdctrl_media_changed(drv3(fdctrl))
977 78ae820c blueswir1
#endif
978 78ae820c blueswir1
        )
979 9fea808a blueswir1
        retval |= FD_DIR_DSKCHG;
980 8977f3c1 bellard
    if (retval != 0)
981 baca51fa bellard
        FLOPPY_DPRINTF("Floppy digital input register: 0x%02x\n", retval);
982 8977f3c1 bellard
983 8977f3c1 bellard
    return retval;
984 8977f3c1 bellard
}
985 8977f3c1 bellard
986 8977f3c1 bellard
/* FIFO state control */
987 baca51fa bellard
static void fdctrl_reset_fifo (fdctrl_t *fdctrl)
988 8977f3c1 bellard
{
989 baca51fa bellard
    fdctrl->data_dir = FD_DIR_WRITE;
990 baca51fa bellard
    fdctrl->data_pos = 0;
991 b9b3d225 blueswir1
    fdctrl->msr &= ~(FD_MSR_CMDBUSY | FD_MSR_DIO);
992 8977f3c1 bellard
}
993 8977f3c1 bellard
994 8977f3c1 bellard
/* Set FIFO status for the host to read */
995 baca51fa bellard
static void fdctrl_set_fifo (fdctrl_t *fdctrl, int fifo_len, int do_irq)
996 8977f3c1 bellard
{
997 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
998 baca51fa bellard
    fdctrl->data_len = fifo_len;
999 baca51fa bellard
    fdctrl->data_pos = 0;
1000 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY | FD_MSR_RQM | FD_MSR_DIO;
1001 8977f3c1 bellard
    if (do_irq)
1002 baca51fa bellard
        fdctrl_raise_irq(fdctrl, 0x00);
1003 8977f3c1 bellard
}
1004 8977f3c1 bellard
1005 8977f3c1 bellard
/* Set an error: unimplemented/unknown command */
1006 65cef780 blueswir1
static void fdctrl_unimplemented (fdctrl_t *fdctrl, int direction)
1007 8977f3c1 bellard
{
1008 77370520 blueswir1
    FLOPPY_ERROR("unimplemented command 0x%02x\n", fdctrl->fifo[0]);
1009 9fea808a blueswir1
    fdctrl->fifo[0] = FD_SR0_INVCMD;
1010 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 1, 0);
1011 8977f3c1 bellard
}
1012 8977f3c1 bellard
1013 746d6de7 blueswir1
/* Seek to next sector */
1014 746d6de7 blueswir1
static int fdctrl_seek_to_next_sect (fdctrl_t *fdctrl, fdrive_t *cur_drv)
1015 746d6de7 blueswir1
{
1016 746d6de7 blueswir1
    FLOPPY_DPRINTF("seek to next sector (%d %02x %02x => %d)\n",
1017 746d6de7 blueswir1
                   cur_drv->head, cur_drv->track, cur_drv->sect,
1018 746d6de7 blueswir1
                   fd_sector(cur_drv));
1019 746d6de7 blueswir1
    /* XXX: cur_drv->sect >= cur_drv->last_sect should be an
1020 746d6de7 blueswir1
       error in fact */
1021 746d6de7 blueswir1
    if (cur_drv->sect >= cur_drv->last_sect ||
1022 746d6de7 blueswir1
        cur_drv->sect == fdctrl->eot) {
1023 746d6de7 blueswir1
        cur_drv->sect = 1;
1024 746d6de7 blueswir1
        if (FD_MULTI_TRACK(fdctrl->data_state)) {
1025 746d6de7 blueswir1
            if (cur_drv->head == 0 &&
1026 746d6de7 blueswir1
                (cur_drv->flags & FDISK_DBL_SIDES) != 0) {
1027 746d6de7 blueswir1
                cur_drv->head = 1;
1028 746d6de7 blueswir1
            } else {
1029 746d6de7 blueswir1
                cur_drv->head = 0;
1030 746d6de7 blueswir1
                cur_drv->track++;
1031 746d6de7 blueswir1
                if ((cur_drv->flags & FDISK_DBL_SIDES) == 0)
1032 746d6de7 blueswir1
                    return 0;
1033 746d6de7 blueswir1
            }
1034 746d6de7 blueswir1
        } else {
1035 746d6de7 blueswir1
            cur_drv->track++;
1036 746d6de7 blueswir1
            return 0;
1037 746d6de7 blueswir1
        }
1038 746d6de7 blueswir1
        FLOPPY_DPRINTF("seek to next track (%d %02x %02x => %d)\n",
1039 746d6de7 blueswir1
                       cur_drv->head, cur_drv->track,
1040 746d6de7 blueswir1
                       cur_drv->sect, fd_sector(cur_drv));
1041 746d6de7 blueswir1
    } else {
1042 746d6de7 blueswir1
        cur_drv->sect++;
1043 746d6de7 blueswir1
    }
1044 746d6de7 blueswir1
    return 1;
1045 746d6de7 blueswir1
}
1046 746d6de7 blueswir1
1047 8977f3c1 bellard
/* Callback for transfer end (stop or abort) */
1048 baca51fa bellard
static void fdctrl_stop_transfer (fdctrl_t *fdctrl, uint8_t status0,
1049 4f431960 j_mayer
                                  uint8_t status1, uint8_t status2)
1050 8977f3c1 bellard
{
1051 baca51fa bellard
    fdrive_t *cur_drv;
1052 8977f3c1 bellard
1053 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1054 8977f3c1 bellard
    FLOPPY_DPRINTF("transfer status: %02x %02x %02x (%02x)\n",
1055 8977f3c1 bellard
                   status0, status1, status2,
1056 cefec4f5 blueswir1
                   status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl));
1057 cefec4f5 blueswir1
    fdctrl->fifo[0] = status0 | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1058 baca51fa bellard
    fdctrl->fifo[1] = status1;
1059 baca51fa bellard
    fdctrl->fifo[2] = status2;
1060 baca51fa bellard
    fdctrl->fifo[3] = cur_drv->track;
1061 baca51fa bellard
    fdctrl->fifo[4] = cur_drv->head;
1062 baca51fa bellard
    fdctrl->fifo[5] = cur_drv->sect;
1063 baca51fa bellard
    fdctrl->fifo[6] = FD_SECTOR_SC;
1064 baca51fa bellard
    fdctrl->data_dir = FD_DIR_READ;
1065 368df94d blueswir1
    if (!(fdctrl->msr & FD_MSR_NONDMA)) {
1066 baca51fa bellard
        DMA_release_DREQ(fdctrl->dma_chann);
1067 ed5fd2cc bellard
    }
1068 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;
1069 368df94d blueswir1
    fdctrl->msr &= ~FD_MSR_NONDMA;
1070 baca51fa bellard
    fdctrl_set_fifo(fdctrl, 7, 1);
1071 8977f3c1 bellard
}
1072 8977f3c1 bellard
1073 8977f3c1 bellard
/* Prepare a data transfer (either DMA or FIFO) */
1074 baca51fa bellard
static void fdctrl_start_transfer (fdctrl_t *fdctrl, int direction)
1075 8977f3c1 bellard
{
1076 baca51fa bellard
    fdrive_t *cur_drv;
1077 8977f3c1 bellard
    uint8_t kh, kt, ks;
1078 77370520 blueswir1
    int did_seek = 0;
1079 8977f3c1 bellard
1080 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1081 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1082 baca51fa bellard
    kt = fdctrl->fifo[2];
1083 baca51fa bellard
    kh = fdctrl->fifo[3];
1084 baca51fa bellard
    ks = fdctrl->fifo[4];
1085 4b19ec0c bellard
    FLOPPY_DPRINTF("Start transfer at %d %d %02x %02x (%d)\n",
1086 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1087 8977f3c1 bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1088 77370520 blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1089 8977f3c1 bellard
    case 2:
1090 8977f3c1 bellard
        /* sect too big */
1091 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1092 baca51fa bellard
        fdctrl->fifo[3] = kt;
1093 baca51fa bellard
        fdctrl->fifo[4] = kh;
1094 baca51fa bellard
        fdctrl->fifo[5] = ks;
1095 8977f3c1 bellard
        return;
1096 8977f3c1 bellard
    case 3:
1097 8977f3c1 bellard
        /* track too big */
1098 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1099 baca51fa bellard
        fdctrl->fifo[3] = kt;
1100 baca51fa bellard
        fdctrl->fifo[4] = kh;
1101 baca51fa bellard
        fdctrl->fifo[5] = ks;
1102 8977f3c1 bellard
        return;
1103 8977f3c1 bellard
    case 4:
1104 8977f3c1 bellard
        /* No seek enabled */
1105 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1106 baca51fa bellard
        fdctrl->fifo[3] = kt;
1107 baca51fa bellard
        fdctrl->fifo[4] = kh;
1108 baca51fa bellard
        fdctrl->fifo[5] = ks;
1109 8977f3c1 bellard
        return;
1110 8977f3c1 bellard
    case 1:
1111 8977f3c1 bellard
        did_seek = 1;
1112 8977f3c1 bellard
        break;
1113 8977f3c1 bellard
    default:
1114 8977f3c1 bellard
        break;
1115 8977f3c1 bellard
    }
1116 b9b3d225 blueswir1
1117 8977f3c1 bellard
    /* Set the FIFO state */
1118 baca51fa bellard
    fdctrl->data_dir = direction;
1119 baca51fa bellard
    fdctrl->data_pos = 0;
1120 b9b3d225 blueswir1
    fdctrl->msr |= FD_MSR_CMDBUSY;
1121 baca51fa bellard
    if (fdctrl->fifo[0] & 0x80)
1122 baca51fa bellard
        fdctrl->data_state |= FD_STATE_MULTI;
1123 baca51fa bellard
    else
1124 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_MULTI;
1125 8977f3c1 bellard
    if (did_seek)
1126 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1127 baca51fa bellard
    else
1128 baca51fa bellard
        fdctrl->data_state &= ~FD_STATE_SEEK;
1129 baca51fa bellard
    if (fdctrl->fifo[5] == 00) {
1130 baca51fa bellard
        fdctrl->data_len = fdctrl->fifo[8];
1131 baca51fa bellard
    } else {
1132 4f431960 j_mayer
        int tmp;
1133 3bcb80f1 ths
        fdctrl->data_len = 128 << (fdctrl->fifo[5] > 7 ? 7 : fdctrl->fifo[5]);
1134 771effeb blueswir1
        tmp = (fdctrl->fifo[6] - ks + 1);
1135 baca51fa bellard
        if (fdctrl->fifo[0] & 0x80)
1136 771effeb blueswir1
            tmp += fdctrl->fifo[6];
1137 4f431960 j_mayer
        fdctrl->data_len *= tmp;
1138 baca51fa bellard
    }
1139 890fa6be bellard
    fdctrl->eot = fdctrl->fifo[6];
1140 368df94d blueswir1
    if (fdctrl->dor & FD_DOR_DMAEN) {
1141 8977f3c1 bellard
        int dma_mode;
1142 8977f3c1 bellard
        /* DMA transfer are enabled. Check if DMA channel is well programmed */
1143 baca51fa bellard
        dma_mode = DMA_get_channel_mode(fdctrl->dma_chann);
1144 8977f3c1 bellard
        dma_mode = (dma_mode >> 2) & 3;
1145 baca51fa bellard
        FLOPPY_DPRINTF("dma_mode=%d direction=%d (%d - %d)\n",
1146 4f431960 j_mayer
                       dma_mode, direction,
1147 baca51fa bellard
                       (128 << fdctrl->fifo[5]) *
1148 4f431960 j_mayer
                       (cur_drv->last_sect - ks + 1), fdctrl->data_len);
1149 8977f3c1 bellard
        if (((direction == FD_DIR_SCANE || direction == FD_DIR_SCANL ||
1150 8977f3c1 bellard
              direction == FD_DIR_SCANH) && dma_mode == 0) ||
1151 8977f3c1 bellard
            (direction == FD_DIR_WRITE && dma_mode == 2) ||
1152 8977f3c1 bellard
            (direction == FD_DIR_READ && dma_mode == 1)) {
1153 8977f3c1 bellard
            /* No access is allowed until DMA transfer has completed */
1154 b9b3d225 blueswir1
            fdctrl->msr &= ~FD_MSR_RQM;
1155 4b19ec0c bellard
            /* Now, we just have to wait for the DMA controller to
1156 8977f3c1 bellard
             * recall us...
1157 8977f3c1 bellard
             */
1158 baca51fa bellard
            DMA_hold_DREQ(fdctrl->dma_chann);
1159 baca51fa bellard
            DMA_schedule(fdctrl->dma_chann);
1160 8977f3c1 bellard
            return;
1161 baca51fa bellard
        } else {
1162 4f431960 j_mayer
            FLOPPY_ERROR("dma_mode=%d direction=%d\n", dma_mode, direction);
1163 8977f3c1 bellard
        }
1164 8977f3c1 bellard
    }
1165 8977f3c1 bellard
    FLOPPY_DPRINTF("start non-DMA transfer\n");
1166 368df94d blueswir1
    fdctrl->msr |= FD_MSR_NONDMA;
1167 b9b3d225 blueswir1
    if (direction != FD_DIR_WRITE)
1168 b9b3d225 blueswir1
        fdctrl->msr |= FD_MSR_DIO;
1169 8977f3c1 bellard
    /* IO based transfer: calculate len */
1170 baca51fa bellard
    fdctrl_raise_irq(fdctrl, 0x00);
1171 8977f3c1 bellard
1172 8977f3c1 bellard
    return;
1173 8977f3c1 bellard
}
1174 8977f3c1 bellard
1175 8977f3c1 bellard
/* Prepare a transfer of deleted data */
1176 baca51fa bellard
static void fdctrl_start_transfer_del (fdctrl_t *fdctrl, int direction)
1177 8977f3c1 bellard
{
1178 77370520 blueswir1
    FLOPPY_ERROR("fdctrl_start_transfer_del() unimplemented\n");
1179 77370520 blueswir1
1180 8977f3c1 bellard
    /* We don't handle deleted data,
1181 8977f3c1 bellard
     * so we don't return *ANYTHING*
1182 8977f3c1 bellard
     */
1183 9fea808a blueswir1
    fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1184 8977f3c1 bellard
}
1185 8977f3c1 bellard
1186 8977f3c1 bellard
/* handlers for DMA transfers */
1187 85571bc7 bellard
static int fdctrl_transfer_handler (void *opaque, int nchan,
1188 85571bc7 bellard
                                    int dma_pos, int dma_len)
1189 8977f3c1 bellard
{
1190 baca51fa bellard
    fdctrl_t *fdctrl;
1191 baca51fa bellard
    fdrive_t *cur_drv;
1192 baca51fa bellard
    int len, start_pos, rel_pos;
1193 8977f3c1 bellard
    uint8_t status0 = 0x00, status1 = 0x00, status2 = 0x00;
1194 8977f3c1 bellard
1195 baca51fa bellard
    fdctrl = opaque;
1196 b9b3d225 blueswir1
    if (fdctrl->msr & FD_MSR_RQM) {
1197 8977f3c1 bellard
        FLOPPY_DPRINTF("Not in DMA transfer mode !\n");
1198 8977f3c1 bellard
        return 0;
1199 8977f3c1 bellard
    }
1200 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1201 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE || fdctrl->data_dir == FD_DIR_SCANL ||
1202 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1203 77370520 blueswir1
        status2 = FD_SR2_SNS;
1204 85571bc7 bellard
    if (dma_len > fdctrl->data_len)
1205 85571bc7 bellard
        dma_len = fdctrl->data_len;
1206 890fa6be bellard
    if (cur_drv->bs == NULL) {
1207 4f431960 j_mayer
        if (fdctrl->data_dir == FD_DIR_WRITE)
1208 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1209 4f431960 j_mayer
        else
1210 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1211 4f431960 j_mayer
        len = 0;
1212 890fa6be bellard
        goto transfer_error;
1213 890fa6be bellard
    }
1214 baca51fa bellard
    rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1215 85571bc7 bellard
    for (start_pos = fdctrl->data_pos; fdctrl->data_pos < dma_len;) {
1216 85571bc7 bellard
        len = dma_len - fdctrl->data_pos;
1217 baca51fa bellard
        if (len + rel_pos > FD_SECTOR_LEN)
1218 baca51fa bellard
            len = FD_SECTOR_LEN - rel_pos;
1219 6f7e9aec bellard
        FLOPPY_DPRINTF("copy %d bytes (%d %d %d) %d pos %d %02x "
1220 6f7e9aec bellard
                       "(%d-0x%08x 0x%08x)\n", len, dma_len, fdctrl->data_pos,
1221 cefec4f5 blueswir1
                       fdctrl->data_len, GET_CUR_DRV(fdctrl), cur_drv->head,
1222 baca51fa bellard
                       cur_drv->track, cur_drv->sect, fd_sector(cur_drv),
1223 9fea808a blueswir1
                       fd_sector(cur_drv) * FD_SECTOR_LEN);
1224 baca51fa bellard
        if (fdctrl->data_dir != FD_DIR_WRITE ||
1225 4f431960 j_mayer
            len < FD_SECTOR_LEN || rel_pos != 0) {
1226 baca51fa bellard
            /* READ & SCAN commands and realign to a sector for WRITE */
1227 baca51fa bellard
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv),
1228 4f431960 j_mayer
                          fdctrl->fifo, 1) < 0) {
1229 8977f3c1 bellard
                FLOPPY_DPRINTF("Floppy: error getting sector %d\n",
1230 8977f3c1 bellard
                               fd_sector(cur_drv));
1231 8977f3c1 bellard
                /* Sure, image size is too small... */
1232 baca51fa bellard
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1233 8977f3c1 bellard
            }
1234 890fa6be bellard
        }
1235 4f431960 j_mayer
        switch (fdctrl->data_dir) {
1236 4f431960 j_mayer
        case FD_DIR_READ:
1237 4f431960 j_mayer
            /* READ commands */
1238 85571bc7 bellard
            DMA_write_memory (nchan, fdctrl->fifo + rel_pos,
1239 85571bc7 bellard
                              fdctrl->data_pos, len);
1240 4f431960 j_mayer
            break;
1241 4f431960 j_mayer
        case FD_DIR_WRITE:
1242 baca51fa bellard
            /* WRITE commands */
1243 85571bc7 bellard
            DMA_read_memory (nchan, fdctrl->fifo + rel_pos,
1244 85571bc7 bellard
                             fdctrl->data_pos, len);
1245 baca51fa bellard
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv),
1246 4f431960 j_mayer
                           fdctrl->fifo, 1) < 0) {
1247 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1248 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1249 baca51fa bellard
                goto transfer_error;
1250 890fa6be bellard
            }
1251 4f431960 j_mayer
            break;
1252 4f431960 j_mayer
        default:
1253 4f431960 j_mayer
            /* SCAN commands */
1254 baca51fa bellard
            {
1255 4f431960 j_mayer
                uint8_t tmpbuf[FD_SECTOR_LEN];
1256 baca51fa bellard
                int ret;
1257 85571bc7 bellard
                DMA_read_memory (nchan, tmpbuf, fdctrl->data_pos, len);
1258 baca51fa bellard
                ret = memcmp(tmpbuf, fdctrl->fifo + rel_pos, len);
1259 8977f3c1 bellard
                if (ret == 0) {
1260 77370520 blueswir1
                    status2 = FD_SR2_SEH;
1261 8977f3c1 bellard
                    goto end_transfer;
1262 8977f3c1 bellard
                }
1263 baca51fa bellard
                if ((ret < 0 && fdctrl->data_dir == FD_DIR_SCANL) ||
1264 baca51fa bellard
                    (ret > 0 && fdctrl->data_dir == FD_DIR_SCANH)) {
1265 8977f3c1 bellard
                    status2 = 0x00;
1266 8977f3c1 bellard
                    goto end_transfer;
1267 8977f3c1 bellard
                }
1268 8977f3c1 bellard
            }
1269 4f431960 j_mayer
            break;
1270 8977f3c1 bellard
        }
1271 4f431960 j_mayer
        fdctrl->data_pos += len;
1272 4f431960 j_mayer
        rel_pos = fdctrl->data_pos % FD_SECTOR_LEN;
1273 baca51fa bellard
        if (rel_pos == 0) {
1274 8977f3c1 bellard
            /* Seek to next sector */
1275 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv))
1276 746d6de7 blueswir1
                break;
1277 8977f3c1 bellard
        }
1278 8977f3c1 bellard
    }
1279 4f431960 j_mayer
 end_transfer:
1280 baca51fa bellard
    len = fdctrl->data_pos - start_pos;
1281 baca51fa bellard
    FLOPPY_DPRINTF("end transfer %d %d %d\n",
1282 4f431960 j_mayer
                   fdctrl->data_pos, len, fdctrl->data_len);
1283 baca51fa bellard
    if (fdctrl->data_dir == FD_DIR_SCANE ||
1284 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANL ||
1285 baca51fa bellard
        fdctrl->data_dir == FD_DIR_SCANH)
1286 77370520 blueswir1
        status2 = FD_SR2_SEH;
1287 baca51fa bellard
    if (FD_DID_SEEK(fdctrl->data_state))
1288 9fea808a blueswir1
        status0 |= FD_SR0_SEEK;
1289 baca51fa bellard
    fdctrl->data_len -= len;
1290 890fa6be bellard
    fdctrl_stop_transfer(fdctrl, status0, status1, status2);
1291 4f431960 j_mayer
 transfer_error:
1292 8977f3c1 bellard
1293 baca51fa bellard
    return len;
1294 8977f3c1 bellard
}
1295 8977f3c1 bellard
1296 8977f3c1 bellard
/* Data register : 0x05 */
1297 baca51fa bellard
static uint32_t fdctrl_read_data (fdctrl_t *fdctrl)
1298 8977f3c1 bellard
{
1299 baca51fa bellard
    fdrive_t *cur_drv;
1300 8977f3c1 bellard
    uint32_t retval = 0;
1301 746d6de7 blueswir1
    int pos;
1302 8977f3c1 bellard
1303 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1304 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1305 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || !(fdctrl->msr & FD_MSR_DIO)) {
1306 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for reading\n");
1307 8977f3c1 bellard
        return 0;
1308 8977f3c1 bellard
    }
1309 baca51fa bellard
    pos = fdctrl->data_pos;
1310 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1311 8977f3c1 bellard
        pos %= FD_SECTOR_LEN;
1312 8977f3c1 bellard
        if (pos == 0) {
1313 746d6de7 blueswir1
            if (fdctrl->data_pos != 0)
1314 746d6de7 blueswir1
                if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1315 746d6de7 blueswir1
                    FLOPPY_DPRINTF("error seeking to next sector %d\n",
1316 746d6de7 blueswir1
                                   fd_sector(cur_drv));
1317 746d6de7 blueswir1
                    return 0;
1318 746d6de7 blueswir1
                }
1319 77370520 blueswir1
            if (bdrv_read(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1320 77370520 blueswir1
                FLOPPY_DPRINTF("error getting sector %d\n",
1321 77370520 blueswir1
                               fd_sector(cur_drv));
1322 77370520 blueswir1
                /* Sure, image size is too small... */
1323 77370520 blueswir1
                memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1324 77370520 blueswir1
            }
1325 8977f3c1 bellard
        }
1326 8977f3c1 bellard
    }
1327 baca51fa bellard
    retval = fdctrl->fifo[pos];
1328 baca51fa bellard
    if (++fdctrl->data_pos == fdctrl->data_len) {
1329 baca51fa bellard
        fdctrl->data_pos = 0;
1330 890fa6be bellard
        /* Switch from transfer mode to status mode
1331 8977f3c1 bellard
         * then from status mode to command mode
1332 8977f3c1 bellard
         */
1333 368df94d blueswir1
        if (fdctrl->msr & FD_MSR_NONDMA) {
1334 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1335 ed5fd2cc bellard
        } else {
1336 baca51fa bellard
            fdctrl_reset_fifo(fdctrl);
1337 ed5fd2cc bellard
            fdctrl_reset_irq(fdctrl);
1338 ed5fd2cc bellard
        }
1339 8977f3c1 bellard
    }
1340 8977f3c1 bellard
    FLOPPY_DPRINTF("data register: 0x%02x\n", retval);
1341 8977f3c1 bellard
1342 8977f3c1 bellard
    return retval;
1343 8977f3c1 bellard
}
1344 8977f3c1 bellard
1345 baca51fa bellard
static void fdctrl_format_sector (fdctrl_t *fdctrl)
1346 8977f3c1 bellard
{
1347 baca51fa bellard
    fdrive_t *cur_drv;
1348 baca51fa bellard
    uint8_t kh, kt, ks;
1349 8977f3c1 bellard
1350 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1351 baca51fa bellard
    cur_drv = get_cur_drv(fdctrl);
1352 baca51fa bellard
    kt = fdctrl->fifo[6];
1353 baca51fa bellard
    kh = fdctrl->fifo[7];
1354 baca51fa bellard
    ks = fdctrl->fifo[8];
1355 baca51fa bellard
    FLOPPY_DPRINTF("format sector at %d %d %02x %02x (%d)\n",
1356 cefec4f5 blueswir1
                   GET_CUR_DRV(fdctrl), kh, kt, ks,
1357 baca51fa bellard
                   _fd_sector(kh, kt, ks, cur_drv->last_sect));
1358 9fea808a blueswir1
    switch (fd_seek(cur_drv, kh, kt, ks, fdctrl->config & FD_CONFIG_EIS)) {
1359 baca51fa bellard
    case 2:
1360 baca51fa bellard
        /* sect too big */
1361 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1362 baca51fa bellard
        fdctrl->fifo[3] = kt;
1363 baca51fa bellard
        fdctrl->fifo[4] = kh;
1364 baca51fa bellard
        fdctrl->fifo[5] = ks;
1365 baca51fa bellard
        return;
1366 baca51fa bellard
    case 3:
1367 baca51fa bellard
        /* track too big */
1368 77370520 blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, FD_SR1_EC, 0x00);
1369 baca51fa bellard
        fdctrl->fifo[3] = kt;
1370 baca51fa bellard
        fdctrl->fifo[4] = kh;
1371 baca51fa bellard
        fdctrl->fifo[5] = ks;
1372 baca51fa bellard
        return;
1373 baca51fa bellard
    case 4:
1374 baca51fa bellard
        /* No seek enabled */
1375 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM, 0x00, 0x00);
1376 baca51fa bellard
        fdctrl->fifo[3] = kt;
1377 baca51fa bellard
        fdctrl->fifo[4] = kh;
1378 baca51fa bellard
        fdctrl->fifo[5] = ks;
1379 baca51fa bellard
        return;
1380 baca51fa bellard
    case 1:
1381 baca51fa bellard
        fdctrl->data_state |= FD_STATE_SEEK;
1382 baca51fa bellard
        break;
1383 baca51fa bellard
    default:
1384 baca51fa bellard
        break;
1385 baca51fa bellard
    }
1386 baca51fa bellard
    memset(fdctrl->fifo, 0, FD_SECTOR_LEN);
1387 baca51fa bellard
    if (cur_drv->bs == NULL ||
1388 baca51fa bellard
        bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1389 37a4c539 ths
        FLOPPY_ERROR("formatting sector %d\n", fd_sector(cur_drv));
1390 9fea808a blueswir1
        fdctrl_stop_transfer(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK, 0x00, 0x00);
1391 baca51fa bellard
    } else {
1392 4f431960 j_mayer
        if (cur_drv->sect == cur_drv->last_sect) {
1393 4f431960 j_mayer
            fdctrl->data_state &= ~FD_STATE_FORMAT;
1394 4f431960 j_mayer
            /* Last sector done */
1395 4f431960 j_mayer
            if (FD_DID_SEEK(fdctrl->data_state))
1396 9fea808a blueswir1
                fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1397 4f431960 j_mayer
            else
1398 4f431960 j_mayer
                fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1399 4f431960 j_mayer
        } else {
1400 4f431960 j_mayer
            /* More to do */
1401 4f431960 j_mayer
            fdctrl->data_pos = 0;
1402 4f431960 j_mayer
            fdctrl->data_len = 4;
1403 4f431960 j_mayer
        }
1404 baca51fa bellard
    }
1405 baca51fa bellard
}
1406 baca51fa bellard
1407 65cef780 blueswir1
static void fdctrl_handle_lock (fdctrl_t *fdctrl, int direction)
1408 65cef780 blueswir1
{
1409 65cef780 blueswir1
    fdctrl->lock = (fdctrl->fifo[0] & 0x80) ? 1 : 0;
1410 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->lock << 4;
1411 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, fdctrl->lock);
1412 65cef780 blueswir1
}
1413 65cef780 blueswir1
1414 65cef780 blueswir1
static void fdctrl_handle_dumpreg (fdctrl_t *fdctrl, int direction)
1415 65cef780 blueswir1
{
1416 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1417 65cef780 blueswir1
1418 65cef780 blueswir1
    /* Drives position */
1419 65cef780 blueswir1
    fdctrl->fifo[0] = drv0(fdctrl)->track;
1420 65cef780 blueswir1
    fdctrl->fifo[1] = drv1(fdctrl)->track;
1421 78ae820c blueswir1
#if MAX_FD == 4
1422 78ae820c blueswir1
    fdctrl->fifo[2] = drv2(fdctrl)->track;
1423 78ae820c blueswir1
    fdctrl->fifo[3] = drv3(fdctrl)->track;
1424 78ae820c blueswir1
#else
1425 65cef780 blueswir1
    fdctrl->fifo[2] = 0;
1426 65cef780 blueswir1
    fdctrl->fifo[3] = 0;
1427 78ae820c blueswir1
#endif
1428 65cef780 blueswir1
    /* timers */
1429 65cef780 blueswir1
    fdctrl->fifo[4] = fdctrl->timer0;
1430 368df94d blueswir1
    fdctrl->fifo[5] = (fdctrl->timer1 << 1) | (fdctrl->dor & FD_DOR_DMAEN ? 1 : 0);
1431 65cef780 blueswir1
    fdctrl->fifo[6] = cur_drv->last_sect;
1432 65cef780 blueswir1
    fdctrl->fifo[7] = (fdctrl->lock << 7) |
1433 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1434 65cef780 blueswir1
    fdctrl->fifo[8] = fdctrl->config;
1435 65cef780 blueswir1
    fdctrl->fifo[9] = fdctrl->precomp_trk;
1436 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 10, 0);
1437 65cef780 blueswir1
}
1438 65cef780 blueswir1
1439 65cef780 blueswir1
static void fdctrl_handle_version (fdctrl_t *fdctrl, int direction)
1440 65cef780 blueswir1
{
1441 65cef780 blueswir1
    /* Controller's version */
1442 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->version;
1443 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1444 65cef780 blueswir1
}
1445 65cef780 blueswir1
1446 65cef780 blueswir1
static void fdctrl_handle_partid (fdctrl_t *fdctrl, int direction)
1447 65cef780 blueswir1
{
1448 65cef780 blueswir1
    fdctrl->fifo[0] = 0x41; /* Stepping 1 */
1449 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1450 65cef780 blueswir1
}
1451 65cef780 blueswir1
1452 65cef780 blueswir1
static void fdctrl_handle_restore (fdctrl_t *fdctrl, int direction)
1453 65cef780 blueswir1
{
1454 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1455 65cef780 blueswir1
1456 65cef780 blueswir1
    /* Drives position */
1457 65cef780 blueswir1
    drv0(fdctrl)->track = fdctrl->fifo[3];
1458 65cef780 blueswir1
    drv1(fdctrl)->track = fdctrl->fifo[4];
1459 78ae820c blueswir1
#if MAX_FD == 4
1460 78ae820c blueswir1
    drv2(fdctrl)->track = fdctrl->fifo[5];
1461 78ae820c blueswir1
    drv3(fdctrl)->track = fdctrl->fifo[6];
1462 78ae820c blueswir1
#endif
1463 65cef780 blueswir1
    /* timers */
1464 65cef780 blueswir1
    fdctrl->timer0 = fdctrl->fifo[7];
1465 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[8];
1466 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[9];
1467 65cef780 blueswir1
    fdctrl->lock = fdctrl->fifo[10] >> 7;
1468 65cef780 blueswir1
    cur_drv->perpendicular = (fdctrl->fifo[10] >> 2) & 0xF;
1469 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[11];
1470 65cef780 blueswir1
    fdctrl->precomp_trk = fdctrl->fifo[12];
1471 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[13];
1472 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1473 65cef780 blueswir1
}
1474 65cef780 blueswir1
1475 65cef780 blueswir1
static void fdctrl_handle_save (fdctrl_t *fdctrl, int direction)
1476 65cef780 blueswir1
{
1477 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1478 65cef780 blueswir1
1479 65cef780 blueswir1
    fdctrl->fifo[0] = 0;
1480 65cef780 blueswir1
    fdctrl->fifo[1] = 0;
1481 65cef780 blueswir1
    /* Drives position */
1482 65cef780 blueswir1
    fdctrl->fifo[2] = drv0(fdctrl)->track;
1483 65cef780 blueswir1
    fdctrl->fifo[3] = drv1(fdctrl)->track;
1484 78ae820c blueswir1
#if MAX_FD == 4
1485 78ae820c blueswir1
    fdctrl->fifo[4] = drv2(fdctrl)->track;
1486 78ae820c blueswir1
    fdctrl->fifo[5] = drv3(fdctrl)->track;
1487 78ae820c blueswir1
#else
1488 65cef780 blueswir1
    fdctrl->fifo[4] = 0;
1489 65cef780 blueswir1
    fdctrl->fifo[5] = 0;
1490 78ae820c blueswir1
#endif
1491 65cef780 blueswir1
    /* timers */
1492 65cef780 blueswir1
    fdctrl->fifo[6] = fdctrl->timer0;
1493 65cef780 blueswir1
    fdctrl->fifo[7] = fdctrl->timer1;
1494 65cef780 blueswir1
    fdctrl->fifo[8] = cur_drv->last_sect;
1495 65cef780 blueswir1
    fdctrl->fifo[9] = (fdctrl->lock << 7) |
1496 65cef780 blueswir1
        (cur_drv->perpendicular << 2);
1497 65cef780 blueswir1
    fdctrl->fifo[10] = fdctrl->config;
1498 65cef780 blueswir1
    fdctrl->fifo[11] = fdctrl->precomp_trk;
1499 65cef780 blueswir1
    fdctrl->fifo[12] = fdctrl->pwrd;
1500 65cef780 blueswir1
    fdctrl->fifo[13] = 0;
1501 65cef780 blueswir1
    fdctrl->fifo[14] = 0;
1502 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 15, 1);
1503 65cef780 blueswir1
}
1504 65cef780 blueswir1
1505 65cef780 blueswir1
static void fdctrl_handle_readid (fdctrl_t *fdctrl, int direction)
1506 65cef780 blueswir1
{
1507 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1508 65cef780 blueswir1
1509 65cef780 blueswir1
    /* XXX: should set main status register to busy */
1510 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1511 65cef780 blueswir1
    qemu_mod_timer(fdctrl->result_timer,
1512 6ee093c9 Juan Quintela
                   qemu_get_clock(vm_clock) + (get_ticks_per_sec() / 50));
1513 65cef780 blueswir1
}
1514 65cef780 blueswir1
1515 65cef780 blueswir1
static void fdctrl_handle_format_track (fdctrl_t *fdctrl, int direction)
1516 65cef780 blueswir1
{
1517 65cef780 blueswir1
    fdrive_t *cur_drv;
1518 65cef780 blueswir1
1519 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1520 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1521 65cef780 blueswir1
    fdctrl->data_state |= FD_STATE_FORMAT;
1522 65cef780 blueswir1
    if (fdctrl->fifo[0] & 0x80)
1523 65cef780 blueswir1
        fdctrl->data_state |= FD_STATE_MULTI;
1524 65cef780 blueswir1
    else
1525 65cef780 blueswir1
        fdctrl->data_state &= ~FD_STATE_MULTI;
1526 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_SEEK;
1527 65cef780 blueswir1
    cur_drv->bps =
1528 65cef780 blueswir1
        fdctrl->fifo[2] > 7 ? 16384 : 128 << fdctrl->fifo[2];
1529 65cef780 blueswir1
#if 0
1530 65cef780 blueswir1
    cur_drv->last_sect =
1531 65cef780 blueswir1
        cur_drv->flags & FDISK_DBL_SIDES ? fdctrl->fifo[3] :
1532 65cef780 blueswir1
        fdctrl->fifo[3] / 2;
1533 65cef780 blueswir1
#else
1534 65cef780 blueswir1
    cur_drv->last_sect = fdctrl->fifo[3];
1535 65cef780 blueswir1
#endif
1536 65cef780 blueswir1
    /* TODO: implement format using DMA expected by the Bochs BIOS
1537 65cef780 blueswir1
     * and Linux fdformat (read 3 bytes per sector via DMA and fill
1538 65cef780 blueswir1
     * the sector with the specified fill byte
1539 65cef780 blueswir1
     */
1540 65cef780 blueswir1
    fdctrl->data_state &= ~FD_STATE_FORMAT;
1541 65cef780 blueswir1
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1542 65cef780 blueswir1
}
1543 65cef780 blueswir1
1544 65cef780 blueswir1
static void fdctrl_handle_specify (fdctrl_t *fdctrl, int direction)
1545 65cef780 blueswir1
{
1546 65cef780 blueswir1
    fdctrl->timer0 = (fdctrl->fifo[1] >> 4) & 0xF;
1547 65cef780 blueswir1
    fdctrl->timer1 = fdctrl->fifo[2] >> 1;
1548 368df94d blueswir1
    if (fdctrl->fifo[2] & 1)
1549 368df94d blueswir1
        fdctrl->dor &= ~FD_DOR_DMAEN;
1550 368df94d blueswir1
    else
1551 368df94d blueswir1
        fdctrl->dor |= FD_DOR_DMAEN;
1552 65cef780 blueswir1
    /* No result back */
1553 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1554 65cef780 blueswir1
}
1555 65cef780 blueswir1
1556 65cef780 blueswir1
static void fdctrl_handle_sense_drive_status (fdctrl_t *fdctrl, int direction)
1557 65cef780 blueswir1
{
1558 65cef780 blueswir1
    fdrive_t *cur_drv;
1559 65cef780 blueswir1
1560 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1561 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1562 65cef780 blueswir1
    cur_drv->head = (fdctrl->fifo[1] >> 2) & 1;
1563 65cef780 blueswir1
    /* 1 Byte status back */
1564 65cef780 blueswir1
    fdctrl->fifo[0] = (cur_drv->ro << 6) |
1565 65cef780 blueswir1
        (cur_drv->track == 0 ? 0x10 : 0x00) |
1566 65cef780 blueswir1
        (cur_drv->head << 2) |
1567 cefec4f5 blueswir1
        GET_CUR_DRV(fdctrl) |
1568 65cef780 blueswir1
        0x28;
1569 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 0);
1570 65cef780 blueswir1
}
1571 65cef780 blueswir1
1572 65cef780 blueswir1
static void fdctrl_handle_recalibrate (fdctrl_t *fdctrl, int direction)
1573 65cef780 blueswir1
{
1574 65cef780 blueswir1
    fdrive_t *cur_drv;
1575 65cef780 blueswir1
1576 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1577 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1578 65cef780 blueswir1
    fd_recalibrate(cur_drv);
1579 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1580 65cef780 blueswir1
    /* Raise Interrupt */
1581 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1582 65cef780 blueswir1
}
1583 65cef780 blueswir1
1584 65cef780 blueswir1
static void fdctrl_handle_sense_interrupt_status (fdctrl_t *fdctrl, int direction)
1585 65cef780 blueswir1
{
1586 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1587 65cef780 blueswir1
1588 f2d81b33 blueswir1
    if(fdctrl->reset_sensei > 0) {
1589 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1590 f2d81b33 blueswir1
            FD_SR0_RDYCHG + FD_RESET_SENSEI_COUNT - fdctrl->reset_sensei;
1591 f2d81b33 blueswir1
        fdctrl->reset_sensei--;
1592 f2d81b33 blueswir1
    } else {
1593 f2d81b33 blueswir1
        /* XXX: status0 handling is broken for read/write
1594 f2d81b33 blueswir1
           commands, so we do this hack. It should be suppressed
1595 f2d81b33 blueswir1
           ASAP */
1596 f2d81b33 blueswir1
        fdctrl->fifo[0] =
1597 f2d81b33 blueswir1
            FD_SR0_SEEK | (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1598 f2d81b33 blueswir1
    }
1599 f2d81b33 blueswir1
1600 65cef780 blueswir1
    fdctrl->fifo[1] = cur_drv->track;
1601 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 2, 0);
1602 65cef780 blueswir1
    fdctrl_reset_irq(fdctrl);
1603 77370520 blueswir1
    fdctrl->status0 = FD_SR0_RDYCHG;
1604 65cef780 blueswir1
}
1605 65cef780 blueswir1
1606 65cef780 blueswir1
static void fdctrl_handle_seek (fdctrl_t *fdctrl, int direction)
1607 65cef780 blueswir1
{
1608 65cef780 blueswir1
    fdrive_t *cur_drv;
1609 65cef780 blueswir1
1610 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1611 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1612 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1613 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->max_track) {
1614 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_ABNTERM | FD_SR0_SEEK);
1615 65cef780 blueswir1
    } else {
1616 65cef780 blueswir1
        cur_drv->track = fdctrl->fifo[2];
1617 65cef780 blueswir1
        /* Raise Interrupt */
1618 65cef780 blueswir1
        fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1619 65cef780 blueswir1
    }
1620 65cef780 blueswir1
}
1621 65cef780 blueswir1
1622 65cef780 blueswir1
static void fdctrl_handle_perpendicular_mode (fdctrl_t *fdctrl, int direction)
1623 65cef780 blueswir1
{
1624 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1625 65cef780 blueswir1
1626 65cef780 blueswir1
    if (fdctrl->fifo[1] & 0x80)
1627 65cef780 blueswir1
        cur_drv->perpendicular = fdctrl->fifo[1] & 0x7;
1628 65cef780 blueswir1
    /* No result back */
1629 1c346df2 blueswir1
    fdctrl_reset_fifo(fdctrl);
1630 65cef780 blueswir1
}
1631 65cef780 blueswir1
1632 65cef780 blueswir1
static void fdctrl_handle_configure (fdctrl_t *fdctrl, int direction)
1633 65cef780 blueswir1
{
1634 65cef780 blueswir1
    fdctrl->config = fdctrl->fifo[2];
1635 65cef780 blueswir1
    fdctrl->precomp_trk =  fdctrl->fifo[3];
1636 65cef780 blueswir1
    /* No result back */
1637 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1638 65cef780 blueswir1
}
1639 65cef780 blueswir1
1640 65cef780 blueswir1
static void fdctrl_handle_powerdown_mode (fdctrl_t *fdctrl, int direction)
1641 65cef780 blueswir1
{
1642 65cef780 blueswir1
    fdctrl->pwrd = fdctrl->fifo[1];
1643 65cef780 blueswir1
    fdctrl->fifo[0] = fdctrl->fifo[1];
1644 65cef780 blueswir1
    fdctrl_set_fifo(fdctrl, 1, 1);
1645 65cef780 blueswir1
}
1646 65cef780 blueswir1
1647 65cef780 blueswir1
static void fdctrl_handle_option (fdctrl_t *fdctrl, int direction)
1648 65cef780 blueswir1
{
1649 65cef780 blueswir1
    /* No result back */
1650 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1651 65cef780 blueswir1
}
1652 65cef780 blueswir1
1653 65cef780 blueswir1
static void fdctrl_handle_drive_specification_command (fdctrl_t *fdctrl, int direction)
1654 65cef780 blueswir1
{
1655 65cef780 blueswir1
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1656 65cef780 blueswir1
1657 65cef780 blueswir1
    if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x80) {
1658 65cef780 blueswir1
        /* Command parameters done */
1659 65cef780 blueswir1
        if (fdctrl->fifo[fdctrl->data_pos - 1] & 0x40) {
1660 65cef780 blueswir1
            fdctrl->fifo[0] = fdctrl->fifo[1];
1661 65cef780 blueswir1
            fdctrl->fifo[2] = 0;
1662 65cef780 blueswir1
            fdctrl->fifo[3] = 0;
1663 65cef780 blueswir1
            fdctrl_set_fifo(fdctrl, 4, 1);
1664 65cef780 blueswir1
        } else {
1665 65cef780 blueswir1
            fdctrl_reset_fifo(fdctrl);
1666 65cef780 blueswir1
        }
1667 65cef780 blueswir1
    } else if (fdctrl->data_len > 7) {
1668 65cef780 blueswir1
        /* ERROR */
1669 65cef780 blueswir1
        fdctrl->fifo[0] = 0x80 |
1670 cefec4f5 blueswir1
            (cur_drv->head << 2) | GET_CUR_DRV(fdctrl);
1671 65cef780 blueswir1
        fdctrl_set_fifo(fdctrl, 1, 1);
1672 65cef780 blueswir1
    }
1673 65cef780 blueswir1
}
1674 65cef780 blueswir1
1675 65cef780 blueswir1
static void fdctrl_handle_relative_seek_out (fdctrl_t *fdctrl, int direction)
1676 65cef780 blueswir1
{
1677 77370520 blueswir1
    fdrive_t *cur_drv;
1678 65cef780 blueswir1
1679 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1680 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1681 65cef780 blueswir1
    if (fdctrl->fifo[2] + cur_drv->track >= cur_drv->max_track) {
1682 65cef780 blueswir1
        cur_drv->track = cur_drv->max_track - 1;
1683 65cef780 blueswir1
    } else {
1684 65cef780 blueswir1
        cur_drv->track += fdctrl->fifo[2];
1685 65cef780 blueswir1
    }
1686 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1687 77370520 blueswir1
    /* Raise Interrupt */
1688 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1689 65cef780 blueswir1
}
1690 65cef780 blueswir1
1691 65cef780 blueswir1
static void fdctrl_handle_relative_seek_in (fdctrl_t *fdctrl, int direction)
1692 65cef780 blueswir1
{
1693 77370520 blueswir1
    fdrive_t *cur_drv;
1694 65cef780 blueswir1
1695 cefec4f5 blueswir1
    SET_CUR_DRV(fdctrl, fdctrl->fifo[1] & FD_DOR_SELMASK);
1696 65cef780 blueswir1
    cur_drv = get_cur_drv(fdctrl);
1697 65cef780 blueswir1
    if (fdctrl->fifo[2] > cur_drv->track) {
1698 65cef780 blueswir1
        cur_drv->track = 0;
1699 65cef780 blueswir1
    } else {
1700 65cef780 blueswir1
        cur_drv->track -= fdctrl->fifo[2];
1701 65cef780 blueswir1
    }
1702 65cef780 blueswir1
    fdctrl_reset_fifo(fdctrl);
1703 65cef780 blueswir1
    /* Raise Interrupt */
1704 65cef780 blueswir1
    fdctrl_raise_irq(fdctrl, FD_SR0_SEEK);
1705 65cef780 blueswir1
}
1706 65cef780 blueswir1
1707 678803ab blueswir1
static const struct {
1708 678803ab blueswir1
    uint8_t value;
1709 678803ab blueswir1
    uint8_t mask;
1710 678803ab blueswir1
    const char* name;
1711 678803ab blueswir1
    int parameters;
1712 678803ab blueswir1
    void (*handler)(fdctrl_t *fdctrl, int direction);
1713 678803ab blueswir1
    int direction;
1714 678803ab blueswir1
} handlers[] = {
1715 678803ab blueswir1
    { FD_CMD_READ, 0x1f, "READ", 8, fdctrl_start_transfer, FD_DIR_READ },
1716 678803ab blueswir1
    { FD_CMD_WRITE, 0x3f, "WRITE", 8, fdctrl_start_transfer, FD_DIR_WRITE },
1717 678803ab blueswir1
    { FD_CMD_SEEK, 0xff, "SEEK", 2, fdctrl_handle_seek },
1718 678803ab blueswir1
    { FD_CMD_SENSE_INTERRUPT_STATUS, 0xff, "SENSE INTERRUPT STATUS", 0, fdctrl_handle_sense_interrupt_status },
1719 678803ab blueswir1
    { FD_CMD_RECALIBRATE, 0xff, "RECALIBRATE", 1, fdctrl_handle_recalibrate },
1720 678803ab blueswir1
    { FD_CMD_FORMAT_TRACK, 0xbf, "FORMAT TRACK", 5, fdctrl_handle_format_track },
1721 678803ab blueswir1
    { FD_CMD_READ_TRACK, 0xbf, "READ TRACK", 8, fdctrl_start_transfer, FD_DIR_READ },
1722 678803ab blueswir1
    { FD_CMD_RESTORE, 0xff, "RESTORE", 17, fdctrl_handle_restore }, /* part of READ DELETED DATA */
1723 678803ab blueswir1
    { FD_CMD_SAVE, 0xff, "SAVE", 0, fdctrl_handle_save }, /* part of READ DELETED DATA */
1724 678803ab blueswir1
    { FD_CMD_READ_DELETED, 0x1f, "READ DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_READ },
1725 678803ab blueswir1
    { FD_CMD_SCAN_EQUAL, 0x1f, "SCAN EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANE },
1726 678803ab blueswir1
    { FD_CMD_VERIFY, 0x1f, "VERIFY", 8, fdctrl_unimplemented },
1727 678803ab blueswir1
    { FD_CMD_SCAN_LOW_OR_EQUAL, 0x1f, "SCAN LOW OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANL },
1728 678803ab blueswir1
    { FD_CMD_SCAN_HIGH_OR_EQUAL, 0x1f, "SCAN HIGH OR EQUAL", 8, fdctrl_start_transfer, FD_DIR_SCANH },
1729 678803ab blueswir1
    { FD_CMD_WRITE_DELETED, 0x3f, "WRITE DELETED DATA", 8, fdctrl_start_transfer_del, FD_DIR_WRITE },
1730 678803ab blueswir1
    { FD_CMD_READ_ID, 0xbf, "READ ID", 1, fdctrl_handle_readid },
1731 678803ab blueswir1
    { FD_CMD_SPECIFY, 0xff, "SPECIFY", 2, fdctrl_handle_specify },
1732 678803ab blueswir1
    { FD_CMD_SENSE_DRIVE_STATUS, 0xff, "SENSE DRIVE STATUS", 1, fdctrl_handle_sense_drive_status },
1733 678803ab blueswir1
    { FD_CMD_PERPENDICULAR_MODE, 0xff, "PERPENDICULAR MODE", 1, fdctrl_handle_perpendicular_mode },
1734 678803ab blueswir1
    { FD_CMD_CONFIGURE, 0xff, "CONFIGURE", 3, fdctrl_handle_configure },
1735 678803ab blueswir1
    { FD_CMD_POWERDOWN_MODE, 0xff, "POWERDOWN MODE", 2, fdctrl_handle_powerdown_mode },
1736 678803ab blueswir1
    { FD_CMD_OPTION, 0xff, "OPTION", 1, fdctrl_handle_option },
1737 678803ab blueswir1
    { FD_CMD_DRIVE_SPECIFICATION_COMMAND, 0xff, "DRIVE SPECIFICATION COMMAND", 5, fdctrl_handle_drive_specification_command },
1738 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_OUT, 0xff, "RELATIVE SEEK OUT", 2, fdctrl_handle_relative_seek_out },
1739 678803ab blueswir1
    { FD_CMD_FORMAT_AND_WRITE, 0xff, "FORMAT AND WRITE", 10, fdctrl_unimplemented },
1740 678803ab blueswir1
    { FD_CMD_RELATIVE_SEEK_IN, 0xff, "RELATIVE SEEK IN", 2, fdctrl_handle_relative_seek_in },
1741 678803ab blueswir1
    { FD_CMD_LOCK, 0x7f, "LOCK", 0, fdctrl_handle_lock },
1742 678803ab blueswir1
    { FD_CMD_DUMPREG, 0xff, "DUMPREG", 0, fdctrl_handle_dumpreg },
1743 678803ab blueswir1
    { FD_CMD_VERSION, 0xff, "VERSION", 0, fdctrl_handle_version },
1744 678803ab blueswir1
    { FD_CMD_PART_ID, 0xff, "PART ID", 0, fdctrl_handle_partid },
1745 678803ab blueswir1
    { FD_CMD_WRITE, 0x1f, "WRITE (BeOS)", 8, fdctrl_start_transfer, FD_DIR_WRITE }, /* not in specification ; BeOS 4.5 bug */
1746 678803ab blueswir1
    { 0, 0, "unknown", 0, fdctrl_unimplemented }, /* default handler */
1747 678803ab blueswir1
};
1748 678803ab blueswir1
/* Associate command to an index in the 'handlers' array */
1749 678803ab blueswir1
static uint8_t command_to_handler[256];
1750 678803ab blueswir1
1751 baca51fa bellard
static void fdctrl_write_data (fdctrl_t *fdctrl, uint32_t value)
1752 baca51fa bellard
{
1753 baca51fa bellard
    fdrive_t *cur_drv;
1754 65cef780 blueswir1
    int pos;
1755 baca51fa bellard
1756 8977f3c1 bellard
    /* Reset mode */
1757 1c346df2 blueswir1
    if (!(fdctrl->dor & FD_DOR_nRESET)) {
1758 4b19ec0c bellard
        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");
1759 8977f3c1 bellard
        return;
1760 8977f3c1 bellard
    }
1761 b9b3d225 blueswir1
    if (!(fdctrl->msr & FD_MSR_RQM) || (fdctrl->msr & FD_MSR_DIO)) {
1762 b9b3d225 blueswir1
        FLOPPY_ERROR("controller not ready for writing\n");
1763 8977f3c1 bellard
        return;
1764 8977f3c1 bellard
    }
1765 b9b3d225 blueswir1
    fdctrl->dsr &= ~FD_DSR_PWRDOWN;
1766 8977f3c1 bellard
    /* Is it write command time ? */
1767 368df94d blueswir1
    if (fdctrl->msr & FD_MSR_NONDMA) {
1768 8977f3c1 bellard
        /* FIFO data write */
1769 b3bc1540 blueswir1
        pos = fdctrl->data_pos++;
1770 b3bc1540 blueswir1
        pos %= FD_SECTOR_LEN;
1771 b3bc1540 blueswir1
        fdctrl->fifo[pos] = value;
1772 b3bc1540 blueswir1
        if (pos == FD_SECTOR_LEN - 1 ||
1773 baca51fa bellard
            fdctrl->data_pos == fdctrl->data_len) {
1774 77370520 blueswir1
            cur_drv = get_cur_drv(fdctrl);
1775 77370520 blueswir1
            if (bdrv_write(cur_drv->bs, fd_sector(cur_drv), fdctrl->fifo, 1) < 0) {
1776 77370520 blueswir1
                FLOPPY_ERROR("writing sector %d\n", fd_sector(cur_drv));
1777 77370520 blueswir1
                return;
1778 77370520 blueswir1
            }
1779 746d6de7 blueswir1
            if (!fdctrl_seek_to_next_sect(fdctrl, cur_drv)) {
1780 746d6de7 blueswir1
                FLOPPY_DPRINTF("error seeking to next sector %d\n",
1781 746d6de7 blueswir1
                               fd_sector(cur_drv));
1782 746d6de7 blueswir1
                return;
1783 746d6de7 blueswir1
            }
1784 8977f3c1 bellard
        }
1785 890fa6be bellard
        /* Switch from transfer mode to status mode
1786 8977f3c1 bellard
         * then from status mode to command mode
1787 8977f3c1 bellard
         */
1788 b9b3d225 blueswir1
        if (fdctrl->data_pos == fdctrl->data_len)
1789 9fea808a blueswir1
            fdctrl_stop_transfer(fdctrl, FD_SR0_SEEK, 0x00, 0x00);
1790 8977f3c1 bellard
        return;
1791 8977f3c1 bellard
    }
1792 baca51fa bellard
    if (fdctrl->data_pos == 0) {
1793 8977f3c1 bellard
        /* Command */
1794 678803ab blueswir1
        pos = command_to_handler[value & 0xff];
1795 678803ab blueswir1
        FLOPPY_DPRINTF("%s command\n", handlers[pos].name);
1796 678803ab blueswir1
        fdctrl->data_len = handlers[pos].parameters + 1;
1797 8977f3c1 bellard
    }
1798 678803ab blueswir1
1799 baca51fa bellard
    FLOPPY_DPRINTF("%s: %02x\n", __func__, value);
1800 77370520 blueswir1
    fdctrl->fifo[fdctrl->data_pos++] = value;
1801 77370520 blueswir1
    if (fdctrl->data_pos == fdctrl->data_len) {
1802 8977f3c1 bellard
        /* We now have all parameters
1803 8977f3c1 bellard
         * and will be able to treat the command
1804 8977f3c1 bellard
         */
1805 4f431960 j_mayer
        if (fdctrl->data_state & FD_STATE_FORMAT) {
1806 4f431960 j_mayer
            fdctrl_format_sector(fdctrl);
1807 8977f3c1 bellard
            return;
1808 8977f3c1 bellard
        }
1809 65cef780 blueswir1
1810 678803ab blueswir1
        pos = command_to_handler[fdctrl->fifo[0] & 0xff];
1811 678803ab blueswir1
        FLOPPY_DPRINTF("treat %s command\n", handlers[pos].name);
1812 678803ab blueswir1
        (*handlers[pos].handler)(fdctrl, handlers[pos].direction);
1813 8977f3c1 bellard
    }
1814 8977f3c1 bellard
}
1815 ed5fd2cc bellard
1816 ed5fd2cc bellard
static void fdctrl_result_timer(void *opaque)
1817 ed5fd2cc bellard
{
1818 ed5fd2cc bellard
    fdctrl_t *fdctrl = opaque;
1819 b7ffa3b1 ths
    fdrive_t *cur_drv = get_cur_drv(fdctrl);
1820 4f431960 j_mayer
1821 b7ffa3b1 ths
    /* Pretend we are spinning.
1822 b7ffa3b1 ths
     * This is needed for Coherent, which uses READ ID to check for
1823 b7ffa3b1 ths
     * sector interleaving.
1824 b7ffa3b1 ths
     */
1825 b7ffa3b1 ths
    if (cur_drv->last_sect != 0) {
1826 b7ffa3b1 ths
        cur_drv->sect = (cur_drv->sect % cur_drv->last_sect) + 1;
1827 b7ffa3b1 ths
    }
1828 ed5fd2cc bellard
    fdctrl_stop_transfer(fdctrl, 0x00, 0x00, 0x00);
1829 ed5fd2cc bellard
}
1830 678803ab blueswir1
1831 678803ab blueswir1
/* Init functions */
1832 12a71a02 Blue Swirl
static void fdctrl_connect_drives(fdctrl_t *fdctrl, BlockDriverState **fds)
1833 678803ab blueswir1
{
1834 12a71a02 Blue Swirl
    unsigned int i;
1835 678803ab blueswir1
1836 678803ab blueswir1
    for (i = 0; i < MAX_FD; i++) {
1837 678803ab blueswir1
        fd_init(&fdctrl->drives[i], fds[i]);
1838 678803ab blueswir1
        fd_revalidate(&fdctrl->drives[i]);
1839 678803ab blueswir1
    }
1840 678803ab blueswir1
}
1841 678803ab blueswir1
1842 86c86157 Gerd Hoffmann
fdctrl_t *fdctrl_init_isa(BlockDriverState **fds)
1843 678803ab blueswir1
{
1844 678803ab blueswir1
    fdctrl_t *fdctrl;
1845 2091ba23 Gerd Hoffmann
    ISADevice *dev;
1846 86c86157 Gerd Hoffmann
    int dma_chann = 2;
1847 678803ab blueswir1
1848 2e15e23b Gerd Hoffmann
    dev = isa_create_simple("isa-fdc");
1849 2091ba23 Gerd Hoffmann
    fdctrl = &(DO_UPCAST(fdctrl_isabus_t, busdev, dev)->state);
1850 8baf73ad Gerd Hoffmann
1851 2091ba23 Gerd Hoffmann
    fdctrl->dma_chann = dma_chann;
1852 2091ba23 Gerd Hoffmann
    DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1853 8baf73ad Gerd Hoffmann
1854 2091ba23 Gerd Hoffmann
    fdctrl_connect_drives(fdctrl, fds);
1855 2091ba23 Gerd Hoffmann
1856 2091ba23 Gerd Hoffmann
    return fdctrl;
1857 2091ba23 Gerd Hoffmann
}
1858 2091ba23 Gerd Hoffmann
1859 2091ba23 Gerd Hoffmann
fdctrl_t *fdctrl_init_sysbus(qemu_irq irq, int dma_chann,
1860 2091ba23 Gerd Hoffmann
                             target_phys_addr_t mmio_base,
1861 2091ba23 Gerd Hoffmann
                             BlockDriverState **fds)
1862 2091ba23 Gerd Hoffmann
{
1863 2091ba23 Gerd Hoffmann
    fdctrl_t *fdctrl;
1864 2091ba23 Gerd Hoffmann
    DeviceState *dev;
1865 2091ba23 Gerd Hoffmann
    fdctrl_sysbus_t *sys;
1866 2091ba23 Gerd Hoffmann
1867 2091ba23 Gerd Hoffmann
    dev = qdev_create(NULL, "sysbus-fdc");
1868 2091ba23 Gerd Hoffmann
    qdev_init(dev);
1869 2091ba23 Gerd Hoffmann
    sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1870 2091ba23 Gerd Hoffmann
    fdctrl = &sys->state;
1871 2091ba23 Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1872 2091ba23 Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, mmio_base);
1873 8baf73ad Gerd Hoffmann
1874 12a71a02 Blue Swirl
    fdctrl->dma_chann = dma_chann;
1875 12a71a02 Blue Swirl
    DMA_register_channel(dma_chann, &fdctrl_transfer_handler, fdctrl);
1876 12a71a02 Blue Swirl
    fdctrl_connect_drives(fdctrl, fds);
1877 f64ab228 Blue Swirl
1878 678803ab blueswir1
    return fdctrl;
1879 678803ab blueswir1
}
1880 678803ab blueswir1
1881 678803ab blueswir1
fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base,
1882 678803ab blueswir1
                             BlockDriverState **fds, qemu_irq *fdc_tc)
1883 678803ab blueswir1
{
1884 f64ab228 Blue Swirl
    DeviceState *dev;
1885 8baf73ad Gerd Hoffmann
    fdctrl_sysbus_t *sys;
1886 678803ab blueswir1
    fdctrl_t *fdctrl;
1887 678803ab blueswir1
1888 12a71a02 Blue Swirl
    dev = qdev_create(NULL, "SUNW,fdtwo");
1889 f64ab228 Blue Swirl
    qdev_init(dev);
1890 8baf73ad Gerd Hoffmann
    sys = DO_UPCAST(fdctrl_sysbus_t, busdev.qdev, dev);
1891 8baf73ad Gerd Hoffmann
    fdctrl = &sys->state;
1892 8baf73ad Gerd Hoffmann
    sysbus_connect_irq(&sys->busdev, 0, irq);
1893 8baf73ad Gerd Hoffmann
    sysbus_mmio_map(&sys->busdev, 0, io_base);
1894 f64ab228 Blue Swirl
    *fdc_tc = qdev_get_gpio_in(dev, 0);
1895 f64ab228 Blue Swirl
1896 12a71a02 Blue Swirl
    fdctrl->dma_chann = -1;
1897 12a71a02 Blue Swirl
1898 12a71a02 Blue Swirl
    fdctrl_connect_drives(fdctrl, fds);
1899 678803ab blueswir1
1900 678803ab blueswir1
    return fdctrl;
1901 678803ab blueswir1
}
1902 f64ab228 Blue Swirl
1903 81a322d4 Gerd Hoffmann
static int fdctrl_init_common(fdctrl_t *fdctrl)
1904 f64ab228 Blue Swirl
{
1905 12a71a02 Blue Swirl
    int i, j;
1906 12a71a02 Blue Swirl
    static int command_tables_inited = 0;
1907 f64ab228 Blue Swirl
1908 12a71a02 Blue Swirl
    /* Fill 'command_to_handler' lookup table */
1909 12a71a02 Blue Swirl
    if (!command_tables_inited) {
1910 12a71a02 Blue Swirl
        command_tables_inited = 1;
1911 12a71a02 Blue Swirl
        for (i = ARRAY_SIZE(handlers) - 1; i >= 0; i--) {
1912 12a71a02 Blue Swirl
            for (j = 0; j < sizeof(command_to_handler); j++) {
1913 12a71a02 Blue Swirl
                if ((j & handlers[i].mask) == handlers[i].value) {
1914 12a71a02 Blue Swirl
                    command_to_handler[j] = i;
1915 12a71a02 Blue Swirl
                }
1916 12a71a02 Blue Swirl
            }
1917 12a71a02 Blue Swirl
        }
1918 12a71a02 Blue Swirl
    }
1919 12a71a02 Blue Swirl
1920 12a71a02 Blue Swirl
    FLOPPY_DPRINTF("init controller\n");
1921 12a71a02 Blue Swirl
    fdctrl->fifo = qemu_memalign(512, FD_SECTOR_LEN);
1922 d7a6c270 Juan Quintela
    fdctrl->fifo_size = 512;
1923 12a71a02 Blue Swirl
    fdctrl->result_timer = qemu_new_timer(vm_clock,
1924 12a71a02 Blue Swirl
                                          fdctrl_result_timer, fdctrl);
1925 12a71a02 Blue Swirl
1926 12a71a02 Blue Swirl
    fdctrl->version = 0x90; /* Intel 82078 controller */
1927 12a71a02 Blue Swirl
    fdctrl->config = FD_CONFIG_EIS | FD_CONFIG_EFIFO; /* Implicit seek, polling & FIFO enabled */
1928 d7a6c270 Juan Quintela
    fdctrl->num_floppies = MAX_FD;
1929 12a71a02 Blue Swirl
1930 12a71a02 Blue Swirl
    fdctrl_external_reset(fdctrl);
1931 d7a6c270 Juan Quintela
    vmstate_register(-1, &vmstate_fdc, fdctrl);
1932 12a71a02 Blue Swirl
    qemu_register_reset(fdctrl_external_reset, fdctrl);
1933 81a322d4 Gerd Hoffmann
    return 0;
1934 f64ab228 Blue Swirl
}
1935 f64ab228 Blue Swirl
1936 81a322d4 Gerd Hoffmann
static int isabus_fdc_init1(ISADevice *dev)
1937 8baf73ad Gerd Hoffmann
{
1938 8baf73ad Gerd Hoffmann
    fdctrl_isabus_t *isa = DO_UPCAST(fdctrl_isabus_t, busdev, dev);
1939 8baf73ad Gerd Hoffmann
    fdctrl_t *fdctrl = &isa->state;
1940 86c86157 Gerd Hoffmann
    int iobase = 0x3f0;
1941 2e15e23b Gerd Hoffmann
    int isairq = 6;
1942 8baf73ad Gerd Hoffmann
1943 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x01, 5, 1,
1944 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1945 86c86157 Gerd Hoffmann
    register_ioport_read(iobase + 0x07, 1, 1,
1946 8baf73ad Gerd Hoffmann
                         &fdctrl_read_port, fdctrl);
1947 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x01, 5, 1,
1948 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1949 86c86157 Gerd Hoffmann
    register_ioport_write(iobase + 0x07, 1, 1,
1950 8baf73ad Gerd Hoffmann
                          &fdctrl_write_port, fdctrl);
1951 2e15e23b Gerd Hoffmann
    isa_init_irq(&isa->busdev, &fdctrl->irq, isairq);
1952 8baf73ad Gerd Hoffmann
1953 81a322d4 Gerd Hoffmann
    return fdctrl_init_common(fdctrl);
1954 8baf73ad Gerd Hoffmann
}
1955 8baf73ad Gerd Hoffmann
1956 81a322d4 Gerd Hoffmann
static int sysbus_fdc_init1(SysBusDevice *dev)
1957 12a71a02 Blue Swirl
{
1958 8baf73ad Gerd Hoffmann
    fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1959 12a71a02 Blue Swirl
    int io;
1960 12a71a02 Blue Swirl
1961 12a71a02 Blue Swirl
    io = cpu_register_io_memory(fdctrl_mem_read, fdctrl_mem_write, fdctrl);
1962 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
1963 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
1964 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1965 8baf73ad Gerd Hoffmann
1966 81a322d4 Gerd Hoffmann
    return fdctrl_init_common(fdctrl);
1967 12a71a02 Blue Swirl
}
1968 12a71a02 Blue Swirl
1969 81a322d4 Gerd Hoffmann
static int sun4m_fdc_init1(SysBusDevice *dev)
1970 12a71a02 Blue Swirl
{
1971 8baf73ad Gerd Hoffmann
    fdctrl_t *fdctrl = &(FROM_SYSBUS(fdctrl_sysbus_t, dev)->state);
1972 12a71a02 Blue Swirl
    int io;
1973 12a71a02 Blue Swirl
1974 12a71a02 Blue Swirl
    io = cpu_register_io_memory(fdctrl_mem_read_strict,
1975 12a71a02 Blue Swirl
                                fdctrl_mem_write_strict, fdctrl);
1976 8baf73ad Gerd Hoffmann
    sysbus_init_mmio(dev, 0x08, io);
1977 8baf73ad Gerd Hoffmann
    sysbus_init_irq(dev, &fdctrl->irq);
1978 8baf73ad Gerd Hoffmann
    qdev_init_gpio_in(&dev->qdev, fdctrl_handle_tc, 1);
1979 8baf73ad Gerd Hoffmann
1980 8baf73ad Gerd Hoffmann
    fdctrl->sun4m = 1;
1981 81a322d4 Gerd Hoffmann
    return fdctrl_init_common(fdctrl);
1982 12a71a02 Blue Swirl
}
1983 f64ab228 Blue Swirl
1984 8baf73ad Gerd Hoffmann
static ISADeviceInfo isa_fdc_info = {
1985 8baf73ad Gerd Hoffmann
    .init = isabus_fdc_init1,
1986 8baf73ad Gerd Hoffmann
    .qdev.name  = "isa-fdc",
1987 8baf73ad Gerd Hoffmann
    .qdev.size  = sizeof(fdctrl_isabus_t),
1988 8baf73ad Gerd Hoffmann
};
1989 8baf73ad Gerd Hoffmann
1990 8baf73ad Gerd Hoffmann
static SysBusDeviceInfo sysbus_fdc_info = {
1991 8baf73ad Gerd Hoffmann
    .init = sysbus_fdc_init1,
1992 8baf73ad Gerd Hoffmann
    .qdev.name  = "sysbus-fdc",
1993 8baf73ad Gerd Hoffmann
    .qdev.size  = sizeof(fdctrl_sysbus_t),
1994 12a71a02 Blue Swirl
};
1995 12a71a02 Blue Swirl
1996 12a71a02 Blue Swirl
static SysBusDeviceInfo sun4m_fdc_info = {
1997 12a71a02 Blue Swirl
    .init = sun4m_fdc_init1,
1998 12a71a02 Blue Swirl
    .qdev.name  = "SUNW,fdtwo",
1999 8baf73ad Gerd Hoffmann
    .qdev.size  = sizeof(fdctrl_sysbus_t),
2000 f64ab228 Blue Swirl
};
2001 f64ab228 Blue Swirl
2002 f64ab228 Blue Swirl
static void fdc_register_devices(void)
2003 f64ab228 Blue Swirl
{
2004 8baf73ad Gerd Hoffmann
    isa_qdev_register(&isa_fdc_info);
2005 8baf73ad Gerd Hoffmann
    sysbus_register_withprop(&sysbus_fdc_info);
2006 12a71a02 Blue Swirl
    sysbus_register_withprop(&sun4m_fdc_info);
2007 f64ab228 Blue Swirl
}
2008 f64ab228 Blue Swirl
2009 f64ab228 Blue Swirl
device_init(fdc_register_devices)