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1 | 7e7c5e4c | balrog | /*
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2 | 7e7c5e4c | balrog | * TI TWL92230C energy-management companion device for the OMAP24xx.
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3 | 7e7c5e4c | balrog | * Aka. Menelaus (N4200 MENELAUS1_V2.2)
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4 | 7e7c5e4c | balrog | *
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5 | 7e7c5e4c | balrog | * Copyright (C) 2008 Nokia Corporation
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6 | 7e7c5e4c | balrog | * Written by Andrzej Zaborowski <andrew@openedhand.com>
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7 | 7e7c5e4c | balrog | *
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8 | 7e7c5e4c | balrog | * This program is free software; you can redistribute it and/or
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9 | 7e7c5e4c | balrog | * modify it under the terms of the GNU General Public License as
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10 | 7e7c5e4c | balrog | * published by the Free Software Foundation; either version 2 or
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11 | 7e7c5e4c | balrog | * (at your option) version 3 of the License.
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12 | 7e7c5e4c | balrog | *
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13 | 7e7c5e4c | balrog | * This program is distributed in the hope that it will be useful,
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14 | 7e7c5e4c | balrog | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 | 7e7c5e4c | balrog | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 | 7e7c5e4c | balrog | * GNU General Public License for more details.
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17 | 7e7c5e4c | balrog | *
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18 | fad6cb1a | aurel32 | * You should have received a copy of the GNU General Public License along
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19 | fad6cb1a | aurel32 | * with this program; if not, write to the Free Software Foundation, Inc.,
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20 | fad6cb1a | aurel32 | * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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21 | 7e7c5e4c | balrog | */
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22 | 7e7c5e4c | balrog | |
23 | 7e7c5e4c | balrog | #include "hw.h" |
24 | 7e7c5e4c | balrog | #include "qemu-timer.h" |
25 | 7e7c5e4c | balrog | #include "i2c.h" |
26 | 7e7c5e4c | balrog | #include "sysemu.h" |
27 | 7e7c5e4c | balrog | #include "console.h" |
28 | 7e7c5e4c | balrog | |
29 | 7e7c5e4c | balrog | #define VERBOSE 1 |
30 | 7e7c5e4c | balrog | |
31 | 7e7c5e4c | balrog | struct menelaus_s {
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32 | 7e7c5e4c | balrog | i2c_slave i2c; |
33 | 7e7c5e4c | balrog | qemu_irq irq; |
34 | 7e7c5e4c | balrog | |
35 | 7e7c5e4c | balrog | int firstbyte;
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36 | 7e7c5e4c | balrog | uint8_t reg; |
37 | 7e7c5e4c | balrog | |
38 | 7e7c5e4c | balrog | uint8_t vcore[5];
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39 | 7e7c5e4c | balrog | uint8_t dcdc[3];
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40 | 7e7c5e4c | balrog | uint8_t ldo[8];
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41 | 7e7c5e4c | balrog | uint8_t sleep[2];
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42 | 7e7c5e4c | balrog | uint8_t osc; |
43 | 7e7c5e4c | balrog | uint8_t detect; |
44 | 7e7c5e4c | balrog | uint16_t mask; |
45 | 7e7c5e4c | balrog | uint16_t status; |
46 | 7e7c5e4c | balrog | uint8_t dir; |
47 | 7e7c5e4c | balrog | uint8_t inputs; |
48 | 7e7c5e4c | balrog | uint8_t outputs; |
49 | 7e7c5e4c | balrog | uint8_t bbsms; |
50 | 7e7c5e4c | balrog | uint8_t pull[4];
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51 | 7e7c5e4c | balrog | uint8_t mmc_ctrl[3];
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52 | 7e7c5e4c | balrog | uint8_t mmc_debounce; |
53 | 7e7c5e4c | balrog | struct {
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54 | 7e7c5e4c | balrog | uint8_t ctrl; |
55 | 7e7c5e4c | balrog | uint16_t comp; |
56 | b0f74c87 | balrog | QEMUTimer *hz_tm; |
57 | 7e7c5e4c | balrog | int64_t next; |
58 | 7e7c5e4c | balrog | struct tm tm;
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59 | 7e7c5e4c | balrog | struct tm new;
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60 | 7e7c5e4c | balrog | struct tm alm;
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61 | aec454d2 | balrog | int sec_offset;
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62 | aec454d2 | balrog | int alm_sec;
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63 | aec454d2 | balrog | int next_comp;
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64 | 7e7c5e4c | balrog | } rtc; |
65 | 7e7c5e4c | balrog | qemu_irq handler[3];
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66 | 7e7c5e4c | balrog | qemu_irq *in; |
67 | 7e7c5e4c | balrog | int pwrbtn_state;
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68 | 7e7c5e4c | balrog | qemu_irq pwrbtn; |
69 | 7e7c5e4c | balrog | }; |
70 | 7e7c5e4c | balrog | |
71 | 7e7c5e4c | balrog | static inline void menelaus_update(struct menelaus_s *s) |
72 | 7e7c5e4c | balrog | { |
73 | 7e7c5e4c | balrog | qemu_set_irq(s->irq, s->status & ~s->mask); |
74 | 7e7c5e4c | balrog | } |
75 | 7e7c5e4c | balrog | |
76 | 7e7c5e4c | balrog | static inline void menelaus_rtc_start(struct menelaus_s *s) |
77 | 7e7c5e4c | balrog | { |
78 | 7e7c5e4c | balrog | s->rtc.next =+ qemu_get_clock(rt_clock); |
79 | b0f74c87 | balrog | qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); |
80 | 7e7c5e4c | balrog | } |
81 | 7e7c5e4c | balrog | |
82 | 7e7c5e4c | balrog | static inline void menelaus_rtc_stop(struct menelaus_s *s) |
83 | 7e7c5e4c | balrog | { |
84 | b0f74c87 | balrog | qemu_del_timer(s->rtc.hz_tm); |
85 | 7e7c5e4c | balrog | s->rtc.next =- qemu_get_clock(rt_clock); |
86 | 7e7c5e4c | balrog | if (s->rtc.next < 1) |
87 | 7e7c5e4c | balrog | s->rtc.next = 1;
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88 | 7e7c5e4c | balrog | } |
89 | 7e7c5e4c | balrog | |
90 | 7e7c5e4c | balrog | static void menelaus_rtc_update(struct menelaus_s *s) |
91 | 7e7c5e4c | balrog | { |
92 | aec454d2 | balrog | qemu_get_timedate(&s->rtc.tm, s->rtc.sec_offset); |
93 | 7e7c5e4c | balrog | } |
94 | 7e7c5e4c | balrog | |
95 | 7e7c5e4c | balrog | static void menelaus_alm_update(struct menelaus_s *s) |
96 | 7e7c5e4c | balrog | { |
97 | 7e7c5e4c | balrog | if ((s->rtc.ctrl & 3) == 3) |
98 | aec454d2 | balrog | s->rtc.alm_sec = qemu_timedate_diff(&s->rtc.alm) - s->rtc.sec_offset; |
99 | 7e7c5e4c | balrog | } |
100 | 7e7c5e4c | balrog | |
101 | 7e7c5e4c | balrog | static void menelaus_rtc_hz(void *opaque) |
102 | 7e7c5e4c | balrog | { |
103 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) opaque; |
104 | 7e7c5e4c | balrog | |
105 | aec454d2 | balrog | s->rtc.next_comp --; |
106 | aec454d2 | balrog | s->rtc.alm_sec --; |
107 | 7e7c5e4c | balrog | s->rtc.next += 1000;
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108 | b0f74c87 | balrog | qemu_mod_timer(s->rtc.hz_tm, s->rtc.next); |
109 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 3) & 3) { /* EVERY */ |
110 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
111 | 7e7c5e4c | balrog | if (((s->rtc.ctrl >> 3) & 3) == 1 && !s->rtc.tm.tm_sec) |
112 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
113 | 7e7c5e4c | balrog | else if (((s->rtc.ctrl >> 3) & 3) == 2 && !s->rtc.tm.tm_min) |
114 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
115 | 7e7c5e4c | balrog | else if (!s->rtc.tm.tm_hour) |
116 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
117 | 7e7c5e4c | balrog | } else
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118 | 7e7c5e4c | balrog | s->status |= 1 << 8; /* RTCTMR */ |
119 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 1) & 1) { /* RTC_AL_EN */ |
120 | aec454d2 | balrog | if (s->rtc.alm_sec == 0) |
121 | 7e7c5e4c | balrog | s->status |= 1 << 9; /* RTCALM */ |
122 | 7e7c5e4c | balrog | /* TODO: wake-up */
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123 | 7e7c5e4c | balrog | } |
124 | aec454d2 | balrog | if (s->rtc.next_comp <= 0) { |
125 | 7e7c5e4c | balrog | s->rtc.next -= muldiv64((int16_t) s->rtc.comp, 1000, 0x8000); |
126 | aec454d2 | balrog | s->rtc.next_comp = 3600;
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127 | 7e7c5e4c | balrog | } |
128 | 7e7c5e4c | balrog | menelaus_update(s); |
129 | 7e7c5e4c | balrog | } |
130 | 7e7c5e4c | balrog | |
131 | 8fcd3692 | blueswir1 | static void menelaus_reset(i2c_slave *i2c) |
132 | 7e7c5e4c | balrog | { |
133 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) i2c; |
134 | 7e7c5e4c | balrog | s->reg = 0x00;
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135 | 7e7c5e4c | balrog | |
136 | 7e7c5e4c | balrog | s->vcore[0] = 0x0c; /* XXX: X-loader needs 0x8c? check! */ |
137 | 7e7c5e4c | balrog | s->vcore[1] = 0x05; |
138 | 7e7c5e4c | balrog | s->vcore[2] = 0x02; |
139 | 7e7c5e4c | balrog | s->vcore[3] = 0x0c; |
140 | 7e7c5e4c | balrog | s->vcore[4] = 0x03; |
141 | 7e7c5e4c | balrog | s->dcdc[0] = 0x33; /* Depends on wiring */ |
142 | 7e7c5e4c | balrog | s->dcdc[1] = 0x03; |
143 | 7e7c5e4c | balrog | s->dcdc[2] = 0x00; |
144 | 7e7c5e4c | balrog | s->ldo[0] = 0x95; |
145 | 7e7c5e4c | balrog | s->ldo[1] = 0x7e; |
146 | 7e7c5e4c | balrog | s->ldo[2] = 0x00; |
147 | 7e7c5e4c | balrog | s->ldo[3] = 0x00; /* Depends on wiring */ |
148 | 7e7c5e4c | balrog | s->ldo[4] = 0x03; /* Depends on wiring */ |
149 | 7e7c5e4c | balrog | s->ldo[5] = 0x00; |
150 | 7e7c5e4c | balrog | s->ldo[6] = 0x00; |
151 | 7e7c5e4c | balrog | s->ldo[7] = 0x00; |
152 | 7e7c5e4c | balrog | s->sleep[0] = 0x00; |
153 | 7e7c5e4c | balrog | s->sleep[1] = 0x00; |
154 | 7e7c5e4c | balrog | s->osc = 0x01;
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155 | 7e7c5e4c | balrog | s->detect = 0x09;
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156 | 7e7c5e4c | balrog | s->mask = 0x0fff;
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157 | 7e7c5e4c | balrog | s->status = 0;
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158 | 7e7c5e4c | balrog | s->dir = 0x07;
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159 | 7e7c5e4c | balrog | s->outputs = 0x00;
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160 | 7e7c5e4c | balrog | s->bbsms = 0x00;
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161 | 7e7c5e4c | balrog | s->pull[0] = 0x00; |
162 | 7e7c5e4c | balrog | s->pull[1] = 0x00; |
163 | 7e7c5e4c | balrog | s->pull[2] = 0x00; |
164 | 7e7c5e4c | balrog | s->pull[3] = 0x00; |
165 | 7e7c5e4c | balrog | s->mmc_ctrl[0] = 0x03; |
166 | 7e7c5e4c | balrog | s->mmc_ctrl[1] = 0xc0; |
167 | 7e7c5e4c | balrog | s->mmc_ctrl[2] = 0x00; |
168 | 7e7c5e4c | balrog | s->mmc_debounce = 0x05;
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169 | 7e7c5e4c | balrog | |
170 | 7e7c5e4c | balrog | if (s->rtc.ctrl & 1) |
171 | 7e7c5e4c | balrog | menelaus_rtc_stop(s); |
172 | 7e7c5e4c | balrog | s->rtc.ctrl = 0x00;
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173 | 7e7c5e4c | balrog | s->rtc.comp = 0x0000;
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174 | 7e7c5e4c | balrog | s->rtc.next = 1000;
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175 | aec454d2 | balrog | s->rtc.sec_offset = 0;
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176 | aec454d2 | balrog | s->rtc.next_comp = 1800;
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177 | aec454d2 | balrog | s->rtc.alm_sec = 1800;
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178 | 7e7c5e4c | balrog | s->rtc.alm.tm_sec = 0x00;
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179 | 7e7c5e4c | balrog | s->rtc.alm.tm_min = 0x00;
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180 | 7e7c5e4c | balrog | s->rtc.alm.tm_hour = 0x00;
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181 | 7e7c5e4c | balrog | s->rtc.alm.tm_mday = 0x01;
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182 | 7e7c5e4c | balrog | s->rtc.alm.tm_mon = 0x00;
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183 | 7e7c5e4c | balrog | s->rtc.alm.tm_year = 2004;
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184 | 7e7c5e4c | balrog | menelaus_update(s); |
185 | 7e7c5e4c | balrog | } |
186 | 7e7c5e4c | balrog | |
187 | 7e7c5e4c | balrog | static inline uint8_t to_bcd(int val) |
188 | 7e7c5e4c | balrog | { |
189 | 7e7c5e4c | balrog | return ((val / 10) << 4) | (val % 10); |
190 | 7e7c5e4c | balrog | } |
191 | 7e7c5e4c | balrog | |
192 | 7e7c5e4c | balrog | static inline int from_bcd(uint8_t val) |
193 | 7e7c5e4c | balrog | { |
194 | 7e7c5e4c | balrog | return ((val >> 4) * 10) + (val & 0x0f); |
195 | 7e7c5e4c | balrog | } |
196 | 7e7c5e4c | balrog | |
197 | 7e7c5e4c | balrog | static void menelaus_gpio_set(void *opaque, int line, int level) |
198 | 7e7c5e4c | balrog | { |
199 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) opaque; |
200 | 7e7c5e4c | balrog | |
201 | 7e7c5e4c | balrog | /* No interrupt generated */
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202 | 7e7c5e4c | balrog | s->inputs &= ~(1 << line);
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203 | 7e7c5e4c | balrog | s->inputs |= level << line; |
204 | 7e7c5e4c | balrog | } |
205 | 7e7c5e4c | balrog | |
206 | 7e7c5e4c | balrog | static void menelaus_pwrbtn_set(void *opaque, int line, int level) |
207 | 7e7c5e4c | balrog | { |
208 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) opaque; |
209 | 7e7c5e4c | balrog | |
210 | 7e7c5e4c | balrog | if (!s->pwrbtn_state && level) {
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211 | 7e7c5e4c | balrog | s->status |= 1 << 11; /* PSHBTN */ |
212 | 7e7c5e4c | balrog | menelaus_update(s); |
213 | 7e7c5e4c | balrog | } |
214 | 7e7c5e4c | balrog | s->pwrbtn_state = level; |
215 | 7e7c5e4c | balrog | } |
216 | 7e7c5e4c | balrog | |
217 | 7e7c5e4c | balrog | #define MENELAUS_REV 0x01 |
218 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL1 0x02 |
219 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL2 0x03 |
220 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL3 0x04 |
221 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL4 0x05 |
222 | 7e7c5e4c | balrog | #define MENELAUS_VCORE_CTRL5 0x06 |
223 | 7e7c5e4c | balrog | #define MENELAUS_DCDC_CTRL1 0x07 |
224 | 7e7c5e4c | balrog | #define MENELAUS_DCDC_CTRL2 0x08 |
225 | 7e7c5e4c | balrog | #define MENELAUS_DCDC_CTRL3 0x09 |
226 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL1 0x0a |
227 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL2 0x0b |
228 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL3 0x0c |
229 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL4 0x0d |
230 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL5 0x0e |
231 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL6 0x0f |
232 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL7 0x10 |
233 | 7e7c5e4c | balrog | #define MENELAUS_LDO_CTRL8 0x11 |
234 | 7e7c5e4c | balrog | #define MENELAUS_SLEEP_CTRL1 0x12 |
235 | 7e7c5e4c | balrog | #define MENELAUS_SLEEP_CTRL2 0x13 |
236 | 7e7c5e4c | balrog | #define MENELAUS_DEVICE_OFF 0x14 |
237 | 7e7c5e4c | balrog | #define MENELAUS_OSC_CTRL 0x15 |
238 | 7e7c5e4c | balrog | #define MENELAUS_DETECT_CTRL 0x16 |
239 | 7e7c5e4c | balrog | #define MENELAUS_INT_MASK1 0x17 |
240 | 7e7c5e4c | balrog | #define MENELAUS_INT_MASK2 0x18 |
241 | 7e7c5e4c | balrog | #define MENELAUS_INT_STATUS1 0x19 |
242 | 7e7c5e4c | balrog | #define MENELAUS_INT_STATUS2 0x1a |
243 | 7e7c5e4c | balrog | #define MENELAUS_INT_ACK1 0x1b |
244 | 7e7c5e4c | balrog | #define MENELAUS_INT_ACK2 0x1c |
245 | 7e7c5e4c | balrog | #define MENELAUS_GPIO_CTRL 0x1d |
246 | 7e7c5e4c | balrog | #define MENELAUS_GPIO_IN 0x1e |
247 | 7e7c5e4c | balrog | #define MENELAUS_GPIO_OUT 0x1f |
248 | 7e7c5e4c | balrog | #define MENELAUS_BBSMS 0x20 |
249 | 7e7c5e4c | balrog | #define MENELAUS_RTC_CTRL 0x21 |
250 | 7e7c5e4c | balrog | #define MENELAUS_RTC_UPDATE 0x22 |
251 | 7e7c5e4c | balrog | #define MENELAUS_RTC_SEC 0x23 |
252 | 7e7c5e4c | balrog | #define MENELAUS_RTC_MIN 0x24 |
253 | 7e7c5e4c | balrog | #define MENELAUS_RTC_HR 0x25 |
254 | 7e7c5e4c | balrog | #define MENELAUS_RTC_DAY 0x26 |
255 | 7e7c5e4c | balrog | #define MENELAUS_RTC_MON 0x27 |
256 | 7e7c5e4c | balrog | #define MENELAUS_RTC_YR 0x28 |
257 | 7e7c5e4c | balrog | #define MENELAUS_RTC_WKDAY 0x29 |
258 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_SEC 0x2a |
259 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_MIN 0x2b |
260 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_HR 0x2c |
261 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_DAY 0x2d |
262 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_MON 0x2e |
263 | 7e7c5e4c | balrog | #define MENELAUS_RTC_AL_YR 0x2f |
264 | 7e7c5e4c | balrog | #define MENELAUS_RTC_COMP_MSB 0x30 |
265 | 7e7c5e4c | balrog | #define MENELAUS_RTC_COMP_LSB 0x31 |
266 | 7e7c5e4c | balrog | #define MENELAUS_S1_PULL_EN 0x32 |
267 | 7e7c5e4c | balrog | #define MENELAUS_S1_PULL_DIR 0x33 |
268 | 7e7c5e4c | balrog | #define MENELAUS_S2_PULL_EN 0x34 |
269 | 7e7c5e4c | balrog | #define MENELAUS_S2_PULL_DIR 0x35 |
270 | 7e7c5e4c | balrog | #define MENELAUS_MCT_CTRL1 0x36 |
271 | 7e7c5e4c | balrog | #define MENELAUS_MCT_CTRL2 0x37 |
272 | 7e7c5e4c | balrog | #define MENELAUS_MCT_CTRL3 0x38 |
273 | 7e7c5e4c | balrog | #define MENELAUS_MCT_PIN_ST 0x39 |
274 | 7e7c5e4c | balrog | #define MENELAUS_DEBOUNCE1 0x3a |
275 | 7e7c5e4c | balrog | |
276 | 7e7c5e4c | balrog | static uint8_t menelaus_read(void *opaque, uint8_t addr) |
277 | 7e7c5e4c | balrog | { |
278 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) opaque; |
279 | 7e7c5e4c | balrog | int reg = 0; |
280 | 7e7c5e4c | balrog | |
281 | 7e7c5e4c | balrog | switch (addr) {
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282 | 7e7c5e4c | balrog | case MENELAUS_REV:
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283 | 7e7c5e4c | balrog | return 0x22; |
284 | 7e7c5e4c | balrog | |
285 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL5: reg ++;
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286 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL4: reg ++;
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287 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL3: reg ++;
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288 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL2: reg ++;
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289 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL1:
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290 | 7e7c5e4c | balrog | return s->vcore[reg];
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291 | 7e7c5e4c | balrog | |
292 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL3: reg ++;
|
293 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL2: reg ++;
|
294 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL1:
|
295 | 7e7c5e4c | balrog | return s->dcdc[reg];
|
296 | 7e7c5e4c | balrog | |
297 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL8: reg ++;
|
298 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL7: reg ++;
|
299 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL6: reg ++;
|
300 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL5: reg ++;
|
301 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL4: reg ++;
|
302 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL3: reg ++;
|
303 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL2: reg ++;
|
304 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL1:
|
305 | 7e7c5e4c | balrog | return s->ldo[reg];
|
306 | 7e7c5e4c | balrog | |
307 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL2: reg ++;
|
308 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL1:
|
309 | 7e7c5e4c | balrog | return s->sleep[reg];
|
310 | 7e7c5e4c | balrog | |
311 | 7e7c5e4c | balrog | case MENELAUS_DEVICE_OFF:
|
312 | 7e7c5e4c | balrog | return 0; |
313 | 7e7c5e4c | balrog | |
314 | 7e7c5e4c | balrog | case MENELAUS_OSC_CTRL:
|
315 | 7e7c5e4c | balrog | return s->osc | (1 << 7); /* CLK32K_GOOD */ |
316 | 7e7c5e4c | balrog | |
317 | 7e7c5e4c | balrog | case MENELAUS_DETECT_CTRL:
|
318 | 7e7c5e4c | balrog | return s->detect;
|
319 | 7e7c5e4c | balrog | |
320 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK1:
|
321 | 7e7c5e4c | balrog | return (s->mask >> 0) & 0xff; |
322 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK2:
|
323 | 7e7c5e4c | balrog | return (s->mask >> 8) & 0xff; |
324 | 7e7c5e4c | balrog | |
325 | 7e7c5e4c | balrog | case MENELAUS_INT_STATUS1:
|
326 | 7e7c5e4c | balrog | return (s->status >> 0) & 0xff; |
327 | 7e7c5e4c | balrog | case MENELAUS_INT_STATUS2:
|
328 | 7e7c5e4c | balrog | return (s->status >> 8) & 0xff; |
329 | 7e7c5e4c | balrog | |
330 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK1:
|
331 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK2:
|
332 | 7e7c5e4c | balrog | return 0; |
333 | 7e7c5e4c | balrog | |
334 | 7e7c5e4c | balrog | case MENELAUS_GPIO_CTRL:
|
335 | 7e7c5e4c | balrog | return s->dir;
|
336 | 7e7c5e4c | balrog | case MENELAUS_GPIO_IN:
|
337 | 7e7c5e4c | balrog | return s->inputs | (~s->dir & s->outputs);
|
338 | 7e7c5e4c | balrog | case MENELAUS_GPIO_OUT:
|
339 | 7e7c5e4c | balrog | return s->outputs;
|
340 | 7e7c5e4c | balrog | |
341 | 7e7c5e4c | balrog | case MENELAUS_BBSMS:
|
342 | 7e7c5e4c | balrog | return s->bbsms;
|
343 | 7e7c5e4c | balrog | |
344 | 7e7c5e4c | balrog | case MENELAUS_RTC_CTRL:
|
345 | 7e7c5e4c | balrog | return s->rtc.ctrl;
|
346 | 7e7c5e4c | balrog | case MENELAUS_RTC_UPDATE:
|
347 | 7e7c5e4c | balrog | return 0x00; |
348 | 7e7c5e4c | balrog | case MENELAUS_RTC_SEC:
|
349 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
350 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_sec);
|
351 | 7e7c5e4c | balrog | case MENELAUS_RTC_MIN:
|
352 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
353 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_min);
|
354 | 7e7c5e4c | balrog | case MENELAUS_RTC_HR:
|
355 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
356 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */ |
357 | 7e7c5e4c | balrog | return to_bcd((s->rtc.tm.tm_hour % 12) + 1) | |
358 | 7e7c5e4c | balrog | (!!(s->rtc.tm.tm_hour >= 12) << 7); /* PM_nAM */ |
359 | 7e7c5e4c | balrog | else
|
360 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_hour);
|
361 | 7e7c5e4c | balrog | case MENELAUS_RTC_DAY:
|
362 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
363 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_mday);
|
364 | 7e7c5e4c | balrog | case MENELAUS_RTC_MON:
|
365 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
366 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_mon + 1); |
367 | 7e7c5e4c | balrog | case MENELAUS_RTC_YR:
|
368 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
369 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_year - 2000); |
370 | 7e7c5e4c | balrog | case MENELAUS_RTC_WKDAY:
|
371 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
372 | 7e7c5e4c | balrog | return to_bcd(s->rtc.tm.tm_wday);
|
373 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_SEC:
|
374 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_sec);
|
375 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MIN:
|
376 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_min);
|
377 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_HR:
|
378 | 7e7c5e4c | balrog | if ((s->rtc.ctrl >> 2) & 1) /* MODE12_n24 */ |
379 | 7e7c5e4c | balrog | return to_bcd((s->rtc.alm.tm_hour % 12) + 1) | |
380 | 7e7c5e4c | balrog | (!!(s->rtc.alm.tm_hour >= 12) << 7);/* AL_PM_nAM */ |
381 | 7e7c5e4c | balrog | else
|
382 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_hour);
|
383 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_DAY:
|
384 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_mday);
|
385 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MON:
|
386 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_mon + 1); |
387 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_YR:
|
388 | 7e7c5e4c | balrog | return to_bcd(s->rtc.alm.tm_year - 2000); |
389 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_MSB:
|
390 | 7e7c5e4c | balrog | return (s->rtc.comp >> 8) & 0xff; |
391 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_LSB:
|
392 | 7e7c5e4c | balrog | return (s->rtc.comp >> 0) & 0xff; |
393 | 7e7c5e4c | balrog | |
394 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_EN:
|
395 | 7e7c5e4c | balrog | return s->pull[0]; |
396 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_DIR:
|
397 | 7e7c5e4c | balrog | return s->pull[1]; |
398 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_EN:
|
399 | 7e7c5e4c | balrog | return s->pull[2]; |
400 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_DIR:
|
401 | 7e7c5e4c | balrog | return s->pull[3]; |
402 | 7e7c5e4c | balrog | |
403 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL3: reg ++;
|
404 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL2: reg ++;
|
405 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL1:
|
406 | 7e7c5e4c | balrog | return s->mmc_ctrl[reg];
|
407 | 7e7c5e4c | balrog | case MENELAUS_MCT_PIN_ST:
|
408 | 7e7c5e4c | balrog | /* TODO: return the real Card Detect */
|
409 | 7e7c5e4c | balrog | return 0; |
410 | 7e7c5e4c | balrog | case MENELAUS_DEBOUNCE1:
|
411 | 7e7c5e4c | balrog | return s->mmc_debounce;
|
412 | 7e7c5e4c | balrog | |
413 | 7e7c5e4c | balrog | default:
|
414 | 7e7c5e4c | balrog | #ifdef VERBOSE
|
415 | 7e7c5e4c | balrog | printf("%s: unknown register %02x\n", __FUNCTION__, addr);
|
416 | 7e7c5e4c | balrog | #endif
|
417 | 7e7c5e4c | balrog | break;
|
418 | 7e7c5e4c | balrog | } |
419 | 7e7c5e4c | balrog | return 0; |
420 | 7e7c5e4c | balrog | } |
421 | 7e7c5e4c | balrog | |
422 | 7e7c5e4c | balrog | static void menelaus_write(void *opaque, uint8_t addr, uint8_t value) |
423 | 7e7c5e4c | balrog | { |
424 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) opaque; |
425 | 7e7c5e4c | balrog | int line;
|
426 | 7e7c5e4c | balrog | int reg = 0; |
427 | 7e7c5e4c | balrog | struct tm tm;
|
428 | 7e7c5e4c | balrog | |
429 | 7e7c5e4c | balrog | switch (addr) {
|
430 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL1:
|
431 | 7e7c5e4c | balrog | s->vcore[0] = (value & 0xe) | MIN(value & 0x1f, 0x12); |
432 | 7e7c5e4c | balrog | break;
|
433 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL2:
|
434 | 7e7c5e4c | balrog | s->vcore[1] = value;
|
435 | 7e7c5e4c | balrog | break;
|
436 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL3:
|
437 | 7e7c5e4c | balrog | s->vcore[2] = MIN(value & 0x1f, 0x12); |
438 | 7e7c5e4c | balrog | break;
|
439 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL4:
|
440 | 7e7c5e4c | balrog | s->vcore[3] = MIN(value & 0x1f, 0x12); |
441 | 7e7c5e4c | balrog | break;
|
442 | 7e7c5e4c | balrog | case MENELAUS_VCORE_CTRL5:
|
443 | 7e7c5e4c | balrog | s->vcore[4] = value & 3; |
444 | 7e7c5e4c | balrog | /* XXX
|
445 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
446 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
447 | 7e7c5e4c | balrog | */
|
448 | 7e7c5e4c | balrog | break;
|
449 | 7e7c5e4c | balrog | |
450 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL1:
|
451 | 7e7c5e4c | balrog | s->dcdc[0] = value & 0x3f; |
452 | 7e7c5e4c | balrog | break;
|
453 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL2:
|
454 | 7e7c5e4c | balrog | s->dcdc[1] = value & 0x07; |
455 | 7e7c5e4c | balrog | /* XXX
|
456 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
457 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
458 | 7e7c5e4c | balrog | */
|
459 | 7e7c5e4c | balrog | break;
|
460 | 7e7c5e4c | balrog | case MENELAUS_DCDC_CTRL3:
|
461 | 7e7c5e4c | balrog | s->dcdc[2] = value & 0x07; |
462 | 7e7c5e4c | balrog | break;
|
463 | 7e7c5e4c | balrog | |
464 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL1:
|
465 | 7e7c5e4c | balrog | s->ldo[0] = value;
|
466 | 7e7c5e4c | balrog | break;
|
467 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL2:
|
468 | 7e7c5e4c | balrog | s->ldo[1] = value & 0x7f; |
469 | 7e7c5e4c | balrog | /* XXX
|
470 | 7e7c5e4c | balrog | * auto set to 0x7e on M_WaitOn, M_Backup
|
471 | 7e7c5e4c | balrog | */
|
472 | 7e7c5e4c | balrog | break;
|
473 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL3:
|
474 | 7e7c5e4c | balrog | s->ldo[2] = value & 3; |
475 | 7e7c5e4c | balrog | /* XXX
|
476 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
477 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
478 | 7e7c5e4c | balrog | */
|
479 | 7e7c5e4c | balrog | break;
|
480 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL4:
|
481 | 7e7c5e4c | balrog | s->ldo[3] = value & 3; |
482 | 7e7c5e4c | balrog | /* XXX
|
483 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
484 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
485 | 7e7c5e4c | balrog | */
|
486 | 7e7c5e4c | balrog | break;
|
487 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL5:
|
488 | 7e7c5e4c | balrog | s->ldo[4] = value & 3; |
489 | 7e7c5e4c | balrog | /* XXX
|
490 | 7e7c5e4c | balrog | * auto set to 3 on M_Active, nRESWARM
|
491 | 7e7c5e4c | balrog | * auto set to 0 on M_WaitOn, M_Backup
|
492 | 7e7c5e4c | balrog | */
|
493 | 7e7c5e4c | balrog | break;
|
494 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL6:
|
495 | 7e7c5e4c | balrog | s->ldo[5] = value & 3; |
496 | 7e7c5e4c | balrog | break;
|
497 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL7:
|
498 | 7e7c5e4c | balrog | s->ldo[6] = value & 3; |
499 | 7e7c5e4c | balrog | break;
|
500 | 7e7c5e4c | balrog | case MENELAUS_LDO_CTRL8:
|
501 | 7e7c5e4c | balrog | s->ldo[7] = value & 3; |
502 | 7e7c5e4c | balrog | break;
|
503 | 7e7c5e4c | balrog | |
504 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL2: reg ++;
|
505 | 7e7c5e4c | balrog | case MENELAUS_SLEEP_CTRL1:
|
506 | 7e7c5e4c | balrog | s->sleep[reg] = value; |
507 | 7e7c5e4c | balrog | break;
|
508 | 7e7c5e4c | balrog | |
509 | 7e7c5e4c | balrog | case MENELAUS_DEVICE_OFF:
|
510 | 7e7c5e4c | balrog | if (value & 1) |
511 | 7e7c5e4c | balrog | menelaus_reset(&s->i2c); |
512 | 7e7c5e4c | balrog | break;
|
513 | 7e7c5e4c | balrog | |
514 | 7e7c5e4c | balrog | case MENELAUS_OSC_CTRL:
|
515 | 7e7c5e4c | balrog | s->osc = value & 7;
|
516 | 7e7c5e4c | balrog | break;
|
517 | 7e7c5e4c | balrog | |
518 | 7e7c5e4c | balrog | case MENELAUS_DETECT_CTRL:
|
519 | 7e7c5e4c | balrog | s->detect = value & 0x7f;
|
520 | 7e7c5e4c | balrog | break;
|
521 | 7e7c5e4c | balrog | |
522 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK1:
|
523 | 7e7c5e4c | balrog | s->mask &= 0xf00;
|
524 | 7e7c5e4c | balrog | s->mask |= value << 0;
|
525 | 7e7c5e4c | balrog | menelaus_update(s); |
526 | 7e7c5e4c | balrog | break;
|
527 | 7e7c5e4c | balrog | case MENELAUS_INT_MASK2:
|
528 | 7e7c5e4c | balrog | s->mask &= 0x0ff;
|
529 | 7e7c5e4c | balrog | s->mask |= value << 8;
|
530 | 7e7c5e4c | balrog | menelaus_update(s); |
531 | 7e7c5e4c | balrog | break;
|
532 | 7e7c5e4c | balrog | |
533 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK1:
|
534 | 7e7c5e4c | balrog | s->status &= ~(((uint16_t) value) << 0);
|
535 | 7e7c5e4c | balrog | menelaus_update(s); |
536 | 7e7c5e4c | balrog | break;
|
537 | 7e7c5e4c | balrog | case MENELAUS_INT_ACK2:
|
538 | 7e7c5e4c | balrog | s->status &= ~(((uint16_t) value) << 8);
|
539 | 7e7c5e4c | balrog | menelaus_update(s); |
540 | 7e7c5e4c | balrog | break;
|
541 | 7e7c5e4c | balrog | |
542 | 7e7c5e4c | balrog | case MENELAUS_GPIO_CTRL:
|
543 | 7e7c5e4c | balrog | for (line = 0; line < 3; line ++) |
544 | 7e7c5e4c | balrog | if (((s->dir ^ value) >> line) & 1) |
545 | 7e7c5e4c | balrog | if (s->handler[line])
|
546 | 7e7c5e4c | balrog | qemu_set_irq(s->handler[line], |
547 | 7e7c5e4c | balrog | ((s->outputs & ~s->dir) >> line) & 1);
|
548 | 7e7c5e4c | balrog | s->dir = value & 0x67;
|
549 | 7e7c5e4c | balrog | break;
|
550 | 7e7c5e4c | balrog | case MENELAUS_GPIO_OUT:
|
551 | 7e7c5e4c | balrog | for (line = 0; line < 3; line ++) |
552 | 7e7c5e4c | balrog | if ((((s->outputs ^ value) & ~s->dir) >> line) & 1) |
553 | 7e7c5e4c | balrog | if (s->handler[line])
|
554 | 7e7c5e4c | balrog | qemu_set_irq(s->handler[line], (s->outputs >> line) & 1);
|
555 | 7e7c5e4c | balrog | s->outputs = value & 0x07;
|
556 | 7e7c5e4c | balrog | break;
|
557 | 7e7c5e4c | balrog | |
558 | 7e7c5e4c | balrog | case MENELAUS_BBSMS:
|
559 | 7e7c5e4c | balrog | s->bbsms = 0x0d;
|
560 | 7e7c5e4c | balrog | break;
|
561 | 7e7c5e4c | balrog | |
562 | 7e7c5e4c | balrog | case MENELAUS_RTC_CTRL:
|
563 | 7e7c5e4c | balrog | if ((s->rtc.ctrl ^ value) & 1) { /* RTC_EN */ |
564 | 7e7c5e4c | balrog | if (value & 1) |
565 | 7e7c5e4c | balrog | menelaus_rtc_start(s); |
566 | 7e7c5e4c | balrog | else
|
567 | 7e7c5e4c | balrog | menelaus_rtc_stop(s); |
568 | 7e7c5e4c | balrog | } |
569 | 7e7c5e4c | balrog | s->rtc.ctrl = value & 0x1f;
|
570 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
571 | 7e7c5e4c | balrog | break;
|
572 | 7e7c5e4c | balrog | case MENELAUS_RTC_UPDATE:
|
573 | 7e7c5e4c | balrog | menelaus_rtc_update(s); |
574 | 7e7c5e4c | balrog | memcpy(&tm, &s->rtc.tm, sizeof(tm));
|
575 | 7e7c5e4c | balrog | switch (value & 0xf) { |
576 | 7e7c5e4c | balrog | case 0: |
577 | 7e7c5e4c | balrog | break;
|
578 | 7e7c5e4c | balrog | case 1: |
579 | 7e7c5e4c | balrog | tm.tm_sec = s->rtc.new.tm_sec; |
580 | 7e7c5e4c | balrog | break;
|
581 | 7e7c5e4c | balrog | case 2: |
582 | 7e7c5e4c | balrog | tm.tm_min = s->rtc.new.tm_min; |
583 | 7e7c5e4c | balrog | break;
|
584 | 7e7c5e4c | balrog | case 3: |
585 | 7e7c5e4c | balrog | if (s->rtc.new.tm_hour > 23) |
586 | 7e7c5e4c | balrog | goto rtc_badness;
|
587 | 7e7c5e4c | balrog | tm.tm_hour = s->rtc.new.tm_hour; |
588 | 7e7c5e4c | balrog | break;
|
589 | 7e7c5e4c | balrog | case 4: |
590 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mday < 1) |
591 | 7e7c5e4c | balrog | goto rtc_badness;
|
592 | 7e7c5e4c | balrog | /* TODO check range */
|
593 | 7e7c5e4c | balrog | tm.tm_mday = s->rtc.new.tm_mday; |
594 | 7e7c5e4c | balrog | break;
|
595 | 7e7c5e4c | balrog | case 5: |
596 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11) |
597 | 7e7c5e4c | balrog | goto rtc_badness;
|
598 | 7e7c5e4c | balrog | tm.tm_mon = s->rtc.new.tm_mon; |
599 | 7e7c5e4c | balrog | break;
|
600 | 7e7c5e4c | balrog | case 6: |
601 | 7e7c5e4c | balrog | tm.tm_year = s->rtc.new.tm_year; |
602 | 7e7c5e4c | balrog | break;
|
603 | 7e7c5e4c | balrog | case 7: |
604 | 7e7c5e4c | balrog | /* TODO set .tm_mday instead */
|
605 | 7e7c5e4c | balrog | tm.tm_wday = s->rtc.new.tm_wday; |
606 | 7e7c5e4c | balrog | break;
|
607 | 7e7c5e4c | balrog | case 8: |
608 | 7e7c5e4c | balrog | if (s->rtc.new.tm_hour > 23) |
609 | 7e7c5e4c | balrog | goto rtc_badness;
|
610 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mday < 1) |
611 | 7e7c5e4c | balrog | goto rtc_badness;
|
612 | 7e7c5e4c | balrog | if (s->rtc.new.tm_mon < 0 || s->rtc.new.tm_mon > 11) |
613 | 7e7c5e4c | balrog | goto rtc_badness;
|
614 | 7e7c5e4c | balrog | tm.tm_sec = s->rtc.new.tm_sec; |
615 | 7e7c5e4c | balrog | tm.tm_min = s->rtc.new.tm_min; |
616 | 7e7c5e4c | balrog | tm.tm_hour = s->rtc.new.tm_hour; |
617 | 7e7c5e4c | balrog | tm.tm_mday = s->rtc.new.tm_mday; |
618 | 7e7c5e4c | balrog | tm.tm_mon = s->rtc.new.tm_mon; |
619 | 7e7c5e4c | balrog | tm.tm_year = s->rtc.new.tm_year; |
620 | 7e7c5e4c | balrog | break;
|
621 | 7e7c5e4c | balrog | rtc_badness:
|
622 | 7e7c5e4c | balrog | default:
|
623 | 7e7c5e4c | balrog | fprintf(stderr, "%s: bad RTC_UPDATE value %02x\n",
|
624 | 7e7c5e4c | balrog | __FUNCTION__, value); |
625 | 7e7c5e4c | balrog | s->status |= 1 << 10; /* RTCERR */ |
626 | 7e7c5e4c | balrog | menelaus_update(s); |
627 | 7e7c5e4c | balrog | } |
628 | aec454d2 | balrog | s->rtc.sec_offset = qemu_timedate_diff(&tm); |
629 | 7e7c5e4c | balrog | break;
|
630 | 7e7c5e4c | balrog | case MENELAUS_RTC_SEC:
|
631 | 7e7c5e4c | balrog | s->rtc.tm.tm_sec = from_bcd(value & 0x7f);
|
632 | 7e7c5e4c | balrog | break;
|
633 | 7e7c5e4c | balrog | case MENELAUS_RTC_MIN:
|
634 | 7e7c5e4c | balrog | s->rtc.tm.tm_min = from_bcd(value & 0x7f);
|
635 | 7e7c5e4c | balrog | break;
|
636 | 7e7c5e4c | balrog | case MENELAUS_RTC_HR:
|
637 | 7e7c5e4c | balrog | s->rtc.tm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */ |
638 | 7e7c5e4c | balrog | MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) : |
639 | 7e7c5e4c | balrog | from_bcd(value & 0x3f);
|
640 | 7e7c5e4c | balrog | break;
|
641 | 7e7c5e4c | balrog | case MENELAUS_RTC_DAY:
|
642 | 7e7c5e4c | balrog | s->rtc.tm.tm_mday = from_bcd(value); |
643 | 7e7c5e4c | balrog | break;
|
644 | 7e7c5e4c | balrog | case MENELAUS_RTC_MON:
|
645 | 7e7c5e4c | balrog | s->rtc.tm.tm_mon = MAX(1, from_bcd(value)) - 1; |
646 | 7e7c5e4c | balrog | break;
|
647 | 7e7c5e4c | balrog | case MENELAUS_RTC_YR:
|
648 | 7e7c5e4c | balrog | s->rtc.tm.tm_year = 2000 + from_bcd(value);
|
649 | 7e7c5e4c | balrog | break;
|
650 | 7e7c5e4c | balrog | case MENELAUS_RTC_WKDAY:
|
651 | 7e7c5e4c | balrog | s->rtc.tm.tm_mday = from_bcd(value); |
652 | 7e7c5e4c | balrog | break;
|
653 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_SEC:
|
654 | 7e7c5e4c | balrog | s->rtc.alm.tm_sec = from_bcd(value & 0x7f);
|
655 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
656 | 7e7c5e4c | balrog | break;
|
657 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MIN:
|
658 | 7e7c5e4c | balrog | s->rtc.alm.tm_min = from_bcd(value & 0x7f);
|
659 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
660 | 7e7c5e4c | balrog | break;
|
661 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_HR:
|
662 | 7e7c5e4c | balrog | s->rtc.alm.tm_hour = (s->rtc.ctrl & (1 << 2)) ? /* MODE12_n24 */ |
663 | 7e7c5e4c | balrog | MIN(from_bcd(value & 0x3f), 12) + ((value >> 7) ? 11 : -1) : |
664 | 7e7c5e4c | balrog | from_bcd(value & 0x3f);
|
665 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
666 | 7e7c5e4c | balrog | break;
|
667 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_DAY:
|
668 | 7e7c5e4c | balrog | s->rtc.alm.tm_mday = from_bcd(value); |
669 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
670 | 7e7c5e4c | balrog | break;
|
671 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_MON:
|
672 | 7e7c5e4c | balrog | s->rtc.alm.tm_mon = MAX(1, from_bcd(value)) - 1; |
673 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
674 | 7e7c5e4c | balrog | break;
|
675 | 7e7c5e4c | balrog | case MENELAUS_RTC_AL_YR:
|
676 | 7e7c5e4c | balrog | s->rtc.alm.tm_year = 2000 + from_bcd(value);
|
677 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
678 | 7e7c5e4c | balrog | break;
|
679 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_MSB:
|
680 | 7e7c5e4c | balrog | s->rtc.comp &= 0xff;
|
681 | 7e7c5e4c | balrog | s->rtc.comp |= value << 8;
|
682 | 7e7c5e4c | balrog | break;
|
683 | 7e7c5e4c | balrog | case MENELAUS_RTC_COMP_LSB:
|
684 | 7e7c5e4c | balrog | s->rtc.comp &= 0xff << 8; |
685 | 7e7c5e4c | balrog | s->rtc.comp |= value; |
686 | 7e7c5e4c | balrog | break;
|
687 | 7e7c5e4c | balrog | |
688 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_EN:
|
689 | 7e7c5e4c | balrog | s->pull[0] = value;
|
690 | 7e7c5e4c | balrog | break;
|
691 | 7e7c5e4c | balrog | case MENELAUS_S1_PULL_DIR:
|
692 | 7e7c5e4c | balrog | s->pull[1] = value & 0x1f; |
693 | 7e7c5e4c | balrog | break;
|
694 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_EN:
|
695 | 7e7c5e4c | balrog | s->pull[2] = value;
|
696 | 7e7c5e4c | balrog | break;
|
697 | 7e7c5e4c | balrog | case MENELAUS_S2_PULL_DIR:
|
698 | 7e7c5e4c | balrog | s->pull[3] = value & 0x1f; |
699 | 7e7c5e4c | balrog | break;
|
700 | 7e7c5e4c | balrog | |
701 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL1:
|
702 | 7e7c5e4c | balrog | s->mmc_ctrl[0] = value & 0x7f; |
703 | 7e7c5e4c | balrog | break;
|
704 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL2:
|
705 | 7e7c5e4c | balrog | s->mmc_ctrl[1] = value;
|
706 | 7e7c5e4c | balrog | /* TODO update Card Detect interrupts */
|
707 | 7e7c5e4c | balrog | break;
|
708 | 7e7c5e4c | balrog | case MENELAUS_MCT_CTRL3:
|
709 | 7e7c5e4c | balrog | s->mmc_ctrl[2] = value & 0xf; |
710 | 7e7c5e4c | balrog | break;
|
711 | 7e7c5e4c | balrog | case MENELAUS_DEBOUNCE1:
|
712 | 7e7c5e4c | balrog | s->mmc_debounce = value & 0x3f;
|
713 | 7e7c5e4c | balrog | break;
|
714 | 7e7c5e4c | balrog | |
715 | 7e7c5e4c | balrog | default:
|
716 | 7e7c5e4c | balrog | #ifdef VERBOSE
|
717 | 7e7c5e4c | balrog | printf("%s: unknown register %02x\n", __FUNCTION__, addr);
|
718 | 7e7c5e4c | balrog | #endif
|
719 | 7e7c5e4c | balrog | } |
720 | 7e7c5e4c | balrog | } |
721 | 7e7c5e4c | balrog | |
722 | 7e7c5e4c | balrog | static void menelaus_event(i2c_slave *i2c, enum i2c_event event) |
723 | 7e7c5e4c | balrog | { |
724 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) i2c; |
725 | 7e7c5e4c | balrog | |
726 | 7e7c5e4c | balrog | if (event == I2C_START_SEND)
|
727 | 7e7c5e4c | balrog | s->firstbyte = 1;
|
728 | 7e7c5e4c | balrog | } |
729 | 7e7c5e4c | balrog | |
730 | 7e7c5e4c | balrog | static int menelaus_tx(i2c_slave *i2c, uint8_t data) |
731 | 7e7c5e4c | balrog | { |
732 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) i2c; |
733 | 7e7c5e4c | balrog | /* Interpret register address byte */
|
734 | 7e7c5e4c | balrog | if (s->firstbyte) {
|
735 | 7e7c5e4c | balrog | s->reg = data; |
736 | 7e7c5e4c | balrog | s->firstbyte = 0;
|
737 | 7e7c5e4c | balrog | } else
|
738 | 7e7c5e4c | balrog | menelaus_write(s, s->reg ++, data); |
739 | 7e7c5e4c | balrog | |
740 | 7e7c5e4c | balrog | return 0; |
741 | 7e7c5e4c | balrog | } |
742 | 7e7c5e4c | balrog | |
743 | 7e7c5e4c | balrog | static int menelaus_rx(i2c_slave *i2c) |
744 | 7e7c5e4c | balrog | { |
745 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) i2c; |
746 | 7e7c5e4c | balrog | |
747 | 7e7c5e4c | balrog | return menelaus_read(s, s->reg ++);
|
748 | 7e7c5e4c | balrog | } |
749 | 7e7c5e4c | balrog | |
750 | 7e7c5e4c | balrog | static void tm_put(QEMUFile *f, struct tm *tm) { |
751 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_sec); |
752 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_min); |
753 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_hour); |
754 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_mday); |
755 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_min); |
756 | 7e7c5e4c | balrog | qemu_put_be16(f, tm->tm_year); |
757 | 7e7c5e4c | balrog | } |
758 | 7e7c5e4c | balrog | |
759 | 7e7c5e4c | balrog | static void tm_get(QEMUFile *f, struct tm *tm) { |
760 | 7e7c5e4c | balrog | tm->tm_sec = qemu_get_be16(f); |
761 | 7e7c5e4c | balrog | tm->tm_min = qemu_get_be16(f); |
762 | 7e7c5e4c | balrog | tm->tm_hour = qemu_get_be16(f); |
763 | 7e7c5e4c | balrog | tm->tm_mday = qemu_get_be16(f); |
764 | 7e7c5e4c | balrog | tm->tm_min = qemu_get_be16(f); |
765 | 7e7c5e4c | balrog | tm->tm_year = qemu_get_be16(f); |
766 | 7e7c5e4c | balrog | } |
767 | 7e7c5e4c | balrog | |
768 | 7e7c5e4c | balrog | static void menelaus_save(QEMUFile *f, void *opaque) |
769 | 7e7c5e4c | balrog | { |
770 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) opaque; |
771 | 7e7c5e4c | balrog | |
772 | 7e7c5e4c | balrog | qemu_put_be32(f, s->firstbyte); |
773 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->reg); |
774 | 7e7c5e4c | balrog | |
775 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[0]);
|
776 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[1]);
|
777 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[2]);
|
778 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[3]);
|
779 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->vcore[4]);
|
780 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->dcdc[3]);
|
781 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->dcdc[3]);
|
782 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->dcdc[3]);
|
783 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[0]);
|
784 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[1]);
|
785 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[2]);
|
786 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[3]);
|
787 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[4]);
|
788 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[5]);
|
789 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[6]);
|
790 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->ldo[7]);
|
791 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->sleep[0]);
|
792 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->sleep[1]);
|
793 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->osc); |
794 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->detect); |
795 | 7e7c5e4c | balrog | qemu_put_be16s(f, &s->mask); |
796 | 7e7c5e4c | balrog | qemu_put_be16s(f, &s->status); |
797 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->dir); |
798 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->inputs); |
799 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->outputs); |
800 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->bbsms); |
801 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[0]);
|
802 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[1]);
|
803 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[2]);
|
804 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->pull[3]);
|
805 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_ctrl[0]);
|
806 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_ctrl[1]);
|
807 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_ctrl[2]);
|
808 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->mmc_debounce); |
809 | 7e7c5e4c | balrog | qemu_put_8s(f, &s->rtc.ctrl); |
810 | 7e7c5e4c | balrog | qemu_put_be16s(f, &s->rtc.comp); |
811 | 7e7c5e4c | balrog | /* Should be <= 1000 */
|
812 | 7e7c5e4c | balrog | qemu_put_be16(f, s->rtc.next - qemu_get_clock(rt_clock)); |
813 | 7e7c5e4c | balrog | tm_put(f, &s->rtc.new); |
814 | 7e7c5e4c | balrog | tm_put(f, &s->rtc.alm); |
815 | 7e7c5e4c | balrog | qemu_put_byte(f, s->pwrbtn_state); |
816 | 7e7c5e4c | balrog | |
817 | 7e7c5e4c | balrog | i2c_slave_save(f, &s->i2c); |
818 | 7e7c5e4c | balrog | } |
819 | 7e7c5e4c | balrog | |
820 | 7e7c5e4c | balrog | static int menelaus_load(QEMUFile *f, void *opaque, int version_id) |
821 | 7e7c5e4c | balrog | { |
822 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) opaque; |
823 | 7e7c5e4c | balrog | |
824 | 7e7c5e4c | balrog | s->firstbyte = qemu_get_be32(f); |
825 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->reg); |
826 | 7e7c5e4c | balrog | |
827 | 7e7c5e4c | balrog | if (s->rtc.ctrl & 1) /* RTC_EN */ |
828 | 7e7c5e4c | balrog | menelaus_rtc_stop(s); |
829 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[0]);
|
830 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[1]);
|
831 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[2]);
|
832 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[3]);
|
833 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->vcore[4]);
|
834 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->dcdc[3]);
|
835 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->dcdc[3]);
|
836 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->dcdc[3]);
|
837 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[0]);
|
838 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[1]);
|
839 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[2]);
|
840 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[3]);
|
841 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[4]);
|
842 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[5]);
|
843 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[6]);
|
844 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->ldo[7]);
|
845 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->sleep[0]);
|
846 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->sleep[1]);
|
847 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->osc); |
848 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->detect); |
849 | 7e7c5e4c | balrog | qemu_get_be16s(f, &s->mask); |
850 | 7e7c5e4c | balrog | qemu_get_be16s(f, &s->status); |
851 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->dir); |
852 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->inputs); |
853 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->outputs); |
854 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->bbsms); |
855 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[0]);
|
856 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[1]);
|
857 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[2]);
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858 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->pull[3]);
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859 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_ctrl[0]);
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860 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_ctrl[1]);
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861 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_ctrl[2]);
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862 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->mmc_debounce); |
863 | 7e7c5e4c | balrog | qemu_get_8s(f, &s->rtc.ctrl); |
864 | 7e7c5e4c | balrog | qemu_get_be16s(f, &s->rtc.comp); |
865 | 7e7c5e4c | balrog | s->rtc.next = qemu_get_be16(f); |
866 | 7e7c5e4c | balrog | tm_get(f, &s->rtc.new); |
867 | 7e7c5e4c | balrog | tm_get(f, &s->rtc.alm); |
868 | 7e7c5e4c | balrog | s->pwrbtn_state = qemu_get_byte(f); |
869 | 7e7c5e4c | balrog | menelaus_alm_update(s); |
870 | 7e7c5e4c | balrog | menelaus_update(s); |
871 | 7e7c5e4c | balrog | if (s->rtc.ctrl & 1) /* RTC_EN */ |
872 | 7e7c5e4c | balrog | menelaus_rtc_start(s); |
873 | 7e7c5e4c | balrog | |
874 | 7e7c5e4c | balrog | i2c_slave_load(f, &s->i2c); |
875 | 7e7c5e4c | balrog | return 0; |
876 | 7e7c5e4c | balrog | } |
877 | 7e7c5e4c | balrog | |
878 | 7e7c5e4c | balrog | i2c_slave *twl92230_init(i2c_bus *bus, qemu_irq irq) |
879 | 7e7c5e4c | balrog | { |
880 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) |
881 | 7e7c5e4c | balrog | i2c_slave_init(bus, 0, sizeof(struct menelaus_s)); |
882 | 7e7c5e4c | balrog | |
883 | 7e7c5e4c | balrog | s->i2c.event = menelaus_event; |
884 | 7e7c5e4c | balrog | s->i2c.recv = menelaus_rx; |
885 | 7e7c5e4c | balrog | s->i2c.send = menelaus_tx; |
886 | 7e7c5e4c | balrog | |
887 | 7e7c5e4c | balrog | s->irq = irq; |
888 | b0f74c87 | balrog | s->rtc.hz_tm = qemu_new_timer(rt_clock, menelaus_rtc_hz, s); |
889 | 7e7c5e4c | balrog | s->in = qemu_allocate_irqs(menelaus_gpio_set, s, 3);
|
890 | 7e7c5e4c | balrog | s->pwrbtn = qemu_allocate_irqs(menelaus_pwrbtn_set, s, 1)[0]; |
891 | 7e7c5e4c | balrog | |
892 | 7e7c5e4c | balrog | menelaus_reset(&s->i2c); |
893 | 7e7c5e4c | balrog | |
894 | 18be5187 | pbrook | register_savevm("menelaus", -1, 0, menelaus_save, menelaus_load, s); |
895 | 7e7c5e4c | balrog | |
896 | 7e7c5e4c | balrog | return &s->i2c;
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897 | 7e7c5e4c | balrog | } |
898 | 7e7c5e4c | balrog | |
899 | 7e7c5e4c | balrog | qemu_irq *twl92230_gpio_in_get(i2c_slave *i2c) |
900 | 7e7c5e4c | balrog | { |
901 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) i2c; |
902 | 7e7c5e4c | balrog | |
903 | 7e7c5e4c | balrog | return s->in;
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904 | 7e7c5e4c | balrog | } |
905 | 7e7c5e4c | balrog | |
906 | 7e7c5e4c | balrog | void twl92230_gpio_out_set(i2c_slave *i2c, int line, qemu_irq handler) |
907 | 7e7c5e4c | balrog | { |
908 | 7e7c5e4c | balrog | struct menelaus_s *s = (struct menelaus_s *) i2c; |
909 | 7e7c5e4c | balrog | |
910 | 7e7c5e4c | balrog | if (line >= 3 || line < 0) { |
911 | 7e7c5e4c | balrog | fprintf(stderr, "%s: No GPO line %i\n", __FUNCTION__, line);
|
912 | 7e7c5e4c | balrog | exit(-1);
|
913 | 7e7c5e4c | balrog | } |
914 | 7e7c5e4c | balrog | s->handler[line] = handler; |
915 | 7e7c5e4c | balrog | } |