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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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int gen_new_label(void);
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static inline void tcg_gen_op1_i32(int opc, TCGv_i32 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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}
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static inline void tcg_gen_op1_i64(int opc, TCGv_i64 arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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}
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static inline void tcg_gen_op2_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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}
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static inline void tcg_gen_op2i_i32(int opc, TCGv_i32 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2i_i64(int opc, TCGv_i64 arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op2ii(int opc, TCGArg arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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}
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static inline void tcg_gen_op3_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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}
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static inline void tcg_gen_op3i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op3i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_ldst_op_i32(int opc, TCGv_i32 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_ldst_op_i64(int opc, TCGv_i64 val, TCGv_ptr base,
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                                       TCGArg offset)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_PTR(base);
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    *gen_opparam_ptr++ = offset;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i32(int opc, TCGv_i64 val, TCGv_i32 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I32(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_qemu_ldst_op_i64_i64(int opc, TCGv_i64 val, TCGv_i64 addr,
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                                                TCGArg mem_index)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(val);
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    *gen_opparam_ptr++ = GET_TCGV_I64(addr);
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    *gen_opparam_ptr++ = mem_index;
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}
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static inline void tcg_gen_op4_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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}
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static inline void tcg_gen_op4_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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}
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static inline void tcg_gen_op4i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGArg arg3, TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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}
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static inline void tcg_gen_op5_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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}
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static inline void tcg_gen_op5i_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                    TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op5i_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                    TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                   TCGv_i32 arg3, TCGv_i32 arg4, TCGv_i32 arg5,
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                                   TCGv_i32 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg6);
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}
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static inline void tcg_gen_op6_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                   TCGv_i64 arg3, TCGv_i64 arg4, TCGv_i64 arg5,
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                                   TCGv_i64 arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg5);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg6);
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}
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static inline void tcg_gen_op6ii_i32(int opc, TCGv_i32 arg1, TCGv_i32 arg2,
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                                     TCGv_i32 arg3, TCGv_i32 arg4, TCGArg arg5,
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                                     TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I32(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void tcg_gen_op6ii_i64(int opc, TCGv_i64 arg1, TCGv_i64 arg2,
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                                     TCGv_i64 arg3, TCGv_i64 arg4, TCGArg arg5,
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                                     TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg1);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg2);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg3);
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    *gen_opparam_ptr++ = GET_TCGV_I64(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_br(int label)
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{
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    tcg_gen_op1i(INDEX_op_br, label);
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}
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static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
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{
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    if (GET_TCGV_I32(ret) != GET_TCGV_I32(arg))
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        tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
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{
327 a7812ae4 pbrook
    tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
328 c896fe29 bellard
}
329 c896fe29 bellard
330 c896fe29 bellard
/* helper calls */
331 a7812ae4 pbrook
static inline void tcg_gen_helperN(void *func, int flags, int sizemask,
332 a7812ae4 pbrook
                                   TCGArg ret, int nargs, TCGArg *args)
333 a7812ae4 pbrook
{
334 a7812ae4 pbrook
    TCGv_ptr fn;
335 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
336 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, flags, sizemask, ret,
337 a7812ae4 pbrook
                  nargs, args);
338 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
339 a7812ae4 pbrook
}
340 c896fe29 bellard
341 a7812ae4 pbrook
/* FIXME: Should this be pure?  */
342 a7812ae4 pbrook
static inline void tcg_gen_helper64(void *func, TCGv_i64 ret,
343 a7812ae4 pbrook
                                    TCGv_i64 a, TCGv_i64 b)
344 c896fe29 bellard
{
345 a7812ae4 pbrook
    TCGv_ptr fn;
346 a7812ae4 pbrook
    TCGArg args[2];
347 a7812ae4 pbrook
    fn = tcg_const_ptr((tcg_target_long)func);
348 a7812ae4 pbrook
    args[0] = GET_TCGV_I64(a);
349 a7812ae4 pbrook
    args[1] = GET_TCGV_I64(b);
350 a7812ae4 pbrook
    tcg_gen_callN(&tcg_ctx, fn, 0, 7, GET_TCGV_I64(ret), 2, args);
351 a7812ae4 pbrook
    tcg_temp_free_ptr(fn);
352 f8422f52 blueswir1
}
353 f8422f52 blueswir1
354 c896fe29 bellard
/* 32 bit ops */
355 c896fe29 bellard
356 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
357 c896fe29 bellard
{
358 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
359 c896fe29 bellard
}
360 c896fe29 bellard
361 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
362 c896fe29 bellard
{
363 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
364 c896fe29 bellard
}
365 c896fe29 bellard
366 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
367 c896fe29 bellard
{
368 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
369 c896fe29 bellard
}
370 c896fe29 bellard
371 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
372 c896fe29 bellard
{
373 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
374 c896fe29 bellard
}
375 c896fe29 bellard
376 a7812ae4 pbrook
static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, tcg_target_long offset)
377 c896fe29 bellard
{
378 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
379 c896fe29 bellard
}
380 c896fe29 bellard
381 a7812ae4 pbrook
static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
382 c896fe29 bellard
{
383 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
384 c896fe29 bellard
}
385 c896fe29 bellard
386 a7812ae4 pbrook
static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
387 c896fe29 bellard
{
388 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
389 c896fe29 bellard
}
390 c896fe29 bellard
391 a7812ae4 pbrook
static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
392 c896fe29 bellard
{
393 a7812ae4 pbrook
    tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
394 c896fe29 bellard
}
395 c896fe29 bellard
396 a7812ae4 pbrook
static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
397 c896fe29 bellard
{
398 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
399 c896fe29 bellard
}
400 c896fe29 bellard
401 a7812ae4 pbrook
static inline void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
402 c896fe29 bellard
{
403 7089442c blueswir1
    /* some cases can be optimized here */
404 7089442c blueswir1
    if (arg2 == 0) {
405 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
406 7089442c blueswir1
    } else {
407 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
408 e8996ee0 bellard
        tcg_gen_add_i32(ret, arg1, t0);
409 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
410 7089442c blueswir1
    }
411 c896fe29 bellard
}
412 c896fe29 bellard
413 a7812ae4 pbrook
static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
414 c896fe29 bellard
{
415 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
416 c896fe29 bellard
}
417 c896fe29 bellard
418 a7812ae4 pbrook
static inline void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2)
419 0045734a aurel32
{
420 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg1);
421 0045734a aurel32
    tcg_gen_sub_i32(ret, t0, arg2);
422 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
423 0045734a aurel32
}
424 0045734a aurel32
425 a7812ae4 pbrook
static inline void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
426 c896fe29 bellard
{
427 7089442c blueswir1
    /* some cases can be optimized here */
428 7089442c blueswir1
    if (arg2 == 0) {
429 7089442c blueswir1
        tcg_gen_mov_i32(ret, arg1);
430 7089442c blueswir1
    } else {
431 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
432 e8996ee0 bellard
        tcg_gen_sub_i32(ret, arg1, t0);
433 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
434 7089442c blueswir1
    }
435 c896fe29 bellard
}
436 c896fe29 bellard
437 a7812ae4 pbrook
static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
438 c896fe29 bellard
{
439 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
440 c896fe29 bellard
}
441 c896fe29 bellard
442 a7812ae4 pbrook
static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
443 c896fe29 bellard
{
444 c896fe29 bellard
    /* some cases can be optimized here */
445 c896fe29 bellard
    if (arg2 == 0) {
446 c896fe29 bellard
        tcg_gen_movi_i32(ret, 0);
447 c896fe29 bellard
    } else if (arg2 == 0xffffffff) {
448 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
449 c896fe29 bellard
    } else {
450 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
451 e8996ee0 bellard
        tcg_gen_and_i32(ret, arg1, t0);
452 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
453 c896fe29 bellard
    }
454 c896fe29 bellard
}
455 c896fe29 bellard
456 a7812ae4 pbrook
static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
457 c896fe29 bellard
{
458 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
459 c896fe29 bellard
}
460 c896fe29 bellard
461 a7812ae4 pbrook
static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
462 c896fe29 bellard
{
463 c896fe29 bellard
    /* some cases can be optimized here */
464 c896fe29 bellard
    if (arg2 == 0xffffffff) {
465 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
466 c896fe29 bellard
    } else if (arg2 == 0) {
467 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
468 c896fe29 bellard
    } else {
469 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
470 e8996ee0 bellard
        tcg_gen_or_i32(ret, arg1, t0);
471 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
472 c896fe29 bellard
    }
473 c896fe29 bellard
}
474 c896fe29 bellard
475 a7812ae4 pbrook
static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
476 c896fe29 bellard
{
477 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
478 c896fe29 bellard
}
479 c896fe29 bellard
480 a7812ae4 pbrook
static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
481 c896fe29 bellard
{
482 c896fe29 bellard
    /* some cases can be optimized here */
483 c896fe29 bellard
    if (arg2 == 0) {
484 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
485 c896fe29 bellard
    } else {
486 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
487 e8996ee0 bellard
        tcg_gen_xor_i32(ret, arg1, t0);
488 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
489 c896fe29 bellard
    }
490 c896fe29 bellard
}
491 c896fe29 bellard
492 a7812ae4 pbrook
static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
493 c896fe29 bellard
{
494 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
495 c896fe29 bellard
}
496 c896fe29 bellard
497 a7812ae4 pbrook
static inline void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
498 c896fe29 bellard
{
499 34151a20 bellard
    if (arg2 == 0) {
500 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
501 34151a20 bellard
    } else {
502 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
503 e8996ee0 bellard
        tcg_gen_shl_i32(ret, arg1, t0);
504 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
505 34151a20 bellard
    }
506 c896fe29 bellard
}
507 c896fe29 bellard
508 a7812ae4 pbrook
static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
509 c896fe29 bellard
{
510 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
511 c896fe29 bellard
}
512 c896fe29 bellard
513 a7812ae4 pbrook
static inline void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
514 c896fe29 bellard
{
515 34151a20 bellard
    if (arg2 == 0) {
516 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
517 34151a20 bellard
    } else {
518 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
519 e8996ee0 bellard
        tcg_gen_shr_i32(ret, arg1, t0);
520 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
521 34151a20 bellard
    }
522 c896fe29 bellard
}
523 c896fe29 bellard
524 a7812ae4 pbrook
static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
525 c896fe29 bellard
{
526 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
527 c896fe29 bellard
}
528 c896fe29 bellard
529 a7812ae4 pbrook
static inline void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
530 c896fe29 bellard
{
531 34151a20 bellard
    if (arg2 == 0) {
532 34151a20 bellard
        tcg_gen_mov_i32(ret, arg1);
533 34151a20 bellard
    } else {
534 a7812ae4 pbrook
        TCGv_i32 t0 = tcg_const_i32(arg2);
535 e8996ee0 bellard
        tcg_gen_sar_i32(ret, arg1, t0);
536 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
537 34151a20 bellard
    }
538 c896fe29 bellard
}
539 c896fe29 bellard
540 a7812ae4 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv_i32 arg1, TCGv_i32 arg2,
541 c896fe29 bellard
                                      int label_index)
542 c896fe29 bellard
{
543 a7812ae4 pbrook
    tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
544 c896fe29 bellard
}
545 c896fe29 bellard
546 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i32(int cond, TCGv_i32 arg1, int32_t arg2,
547 cb63669a pbrook
                                       int label_index)
548 cb63669a pbrook
{
549 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
550 cb63669a pbrook
    tcg_gen_brcond_i32(cond, arg1, t0, label_index);
551 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
552 cb63669a pbrook
}
553 cb63669a pbrook
554 a7812ae4 pbrook
static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
555 c896fe29 bellard
{
556 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
557 c896fe29 bellard
}
558 c896fe29 bellard
559 a7812ae4 pbrook
static inline void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
560 f730fd27 ths
{
561 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(arg2);
562 e8996ee0 bellard
    tcg_gen_mul_i32(ret, arg1, t0);
563 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
564 f730fd27 ths
}
565 f730fd27 ths
566 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
567 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
568 c896fe29 bellard
{
569 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_div_i32, ret, arg1, arg2);
570 c896fe29 bellard
}
571 c896fe29 bellard
572 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
573 c896fe29 bellard
{
574 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_rem_i32, ret, arg1, arg2);
575 c896fe29 bellard
}
576 c896fe29 bellard
577 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
578 c896fe29 bellard
{
579 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_divu_i32, ret, arg1, arg2);
580 c896fe29 bellard
}
581 c896fe29 bellard
582 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
583 c896fe29 bellard
{
584 a7812ae4 pbrook
    tcg_gen_op3_i32(INDEX_op_remu_i32, ret, arg1, arg2);
585 c896fe29 bellard
}
586 c896fe29 bellard
#else
587 a7812ae4 pbrook
static inline void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
588 c896fe29 bellard
{
589 a7812ae4 pbrook
    TCGv_i32 t0;
590 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
591 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
592 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
593 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
594 c896fe29 bellard
}
595 c896fe29 bellard
596 a7812ae4 pbrook
static inline void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
597 c896fe29 bellard
{
598 a7812ae4 pbrook
    TCGv_i32 t0;
599 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
600 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
601 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
602 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
603 c896fe29 bellard
}
604 c896fe29 bellard
605 a7812ae4 pbrook
static inline void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
606 c896fe29 bellard
{
607 a7812ae4 pbrook
    TCGv_i32 t0;
608 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
609 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
610 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
611 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
612 c896fe29 bellard
}
613 c896fe29 bellard
614 a7812ae4 pbrook
static inline void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
615 c896fe29 bellard
{
616 a7812ae4 pbrook
    TCGv_i32 t0;
617 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
618 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
619 a7812ae4 pbrook
    tcg_gen_op5_i32(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
620 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
621 c896fe29 bellard
}
622 c896fe29 bellard
#endif
623 c896fe29 bellard
624 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
625 c896fe29 bellard
626 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
627 c896fe29 bellard
{
628 a7812ae4 pbrook
    if (GET_TCGV_I64(ret) != GET_TCGV_I64(arg)) {
629 a7812ae4 pbrook
        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
630 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
631 4d07272d blueswir1
    }
632 c896fe29 bellard
}
633 c896fe29 bellard
634 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
635 c896fe29 bellard
{
636 a7812ae4 pbrook
    tcg_gen_movi_i32(TCGV_LOW(ret), arg);
637 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
638 c896fe29 bellard
}
639 c896fe29 bellard
640 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
641 a7812ae4 pbrook
                                    tcg_target_long offset)
642 c896fe29 bellard
{
643 a7812ae4 pbrook
    tcg_gen_ld8u_i32(TCGV_LOW(ret), arg2, offset);
644 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
645 c896fe29 bellard
}
646 c896fe29 bellard
647 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
648 a7812ae4 pbrook
                                    tcg_target_long offset)
649 c896fe29 bellard
{
650 a7812ae4 pbrook
    tcg_gen_ld8s_i32(TCGV_LOW(ret), arg2, offset);
651 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), 31);
652 c896fe29 bellard
}
653 c896fe29 bellard
654 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
655 a7812ae4 pbrook
                                     tcg_target_long offset)
656 c896fe29 bellard
{
657 a7812ae4 pbrook
    tcg_gen_ld16u_i32(TCGV_LOW(ret), TCGV_LOW(arg2), offset);
658 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
659 c896fe29 bellard
}
660 c896fe29 bellard
661 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
662 a7812ae4 pbrook
                                     tcg_target_long offset)
663 c896fe29 bellard
{
664 a7812ae4 pbrook
    tcg_gen_ld16s_i32(TCGV_LOW(ret), arg2, offset);
665 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
666 c896fe29 bellard
}
667 c896fe29 bellard
668 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
669 a7812ae4 pbrook
                                     tcg_target_long offset)
670 c896fe29 bellard
{
671 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
672 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
673 c896fe29 bellard
}
674 c896fe29 bellard
675 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
676 a7812ae4 pbrook
                                     tcg_target_long offset)
677 c896fe29 bellard
{
678 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
679 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
680 c896fe29 bellard
}
681 c896fe29 bellard
682 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
683 a7812ae4 pbrook
                                  tcg_target_long offset)
684 c896fe29 bellard
{
685 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
686 c896fe29 bellard
       same temporary */
687 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
688 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
689 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset + 4);
690 c896fe29 bellard
#else
691 a7812ae4 pbrook
    tcg_gen_ld_i32(TCGV_LOW(ret), arg2, offset);
692 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
693 c896fe29 bellard
#endif
694 c896fe29 bellard
}
695 c896fe29 bellard
696 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
697 a7812ae4 pbrook
                                   tcg_target_long offset)
698 c896fe29 bellard
{
699 a7812ae4 pbrook
    tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
700 c896fe29 bellard
}
701 c896fe29 bellard
702 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
703 a7812ae4 pbrook
                                    tcg_target_long offset)
704 c896fe29 bellard
{
705 a7812ae4 pbrook
    tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
706 c896fe29 bellard
}
707 c896fe29 bellard
708 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
709 a7812ae4 pbrook
                                    tcg_target_long offset)
710 c896fe29 bellard
{
711 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
712 c896fe29 bellard
}
713 c896fe29 bellard
714 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
715 a7812ae4 pbrook
                                  tcg_target_long offset)
716 c896fe29 bellard
{
717 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
718 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
719 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset + 4);
720 c896fe29 bellard
#else
721 a7812ae4 pbrook
    tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
722 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
723 c896fe29 bellard
#endif
724 c896fe29 bellard
}
725 c896fe29 bellard
726 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
727 c896fe29 bellard
{
728 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_add2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
729 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
730 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
731 c896fe29 bellard
}
732 c896fe29 bellard
733 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
734 c896fe29 bellard
{
735 a7812ae4 pbrook
    tcg_gen_op6_i32(INDEX_op_sub2_i32, TCGV_LOW(ret), TCGV_HIGH(ret),
736 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
737 a7812ae4 pbrook
                    TCGV_HIGH(arg2));
738 c896fe29 bellard
}
739 c896fe29 bellard
740 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
741 c896fe29 bellard
{
742 a7812ae4 pbrook
    tcg_gen_and_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
743 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
744 c896fe29 bellard
}
745 c896fe29 bellard
746 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
747 c896fe29 bellard
{
748 a7812ae4 pbrook
    tcg_gen_andi_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
749 ac56dd48 pbrook
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
750 c896fe29 bellard
}
751 c896fe29 bellard
752 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
753 c896fe29 bellard
{
754 a7812ae4 pbrook
    tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
755 ac56dd48 pbrook
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
756 c896fe29 bellard
}
757 c896fe29 bellard
758 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
759 c896fe29 bellard
{
760 a7812ae4 pbrook
    tcg_gen_ori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
761 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
762 c896fe29 bellard
}
763 c896fe29 bellard
764 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
765 c896fe29 bellard
{
766 a7812ae4 pbrook
    tcg_gen_xor_i32(TCGV_LOW(ret), TCGV_LOW(arg1), TCGV_LOW(arg2));
767 ac56dd48 pbrook
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
768 c896fe29 bellard
}
769 c896fe29 bellard
770 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
771 c896fe29 bellard
{
772 a7812ae4 pbrook
    tcg_gen_xori_i32(TCGV_LOW(ret), TCGV_LOW(arg1), arg2);
773 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
774 c896fe29 bellard
}
775 c896fe29 bellard
776 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
777 c896fe29 bellard
   specific code (x86) */
778 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
779 c896fe29 bellard
{
780 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shl_i64, ret, arg1, arg2);
781 c896fe29 bellard
}
782 c896fe29 bellard
783 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
784 c896fe29 bellard
{
785 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
786 c896fe29 bellard
}
787 c896fe29 bellard
788 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
789 c896fe29 bellard
{
790 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_shr_i64, ret, arg1, arg2);
791 c896fe29 bellard
}
792 c896fe29 bellard
793 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
794 c896fe29 bellard
{
795 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
796 c896fe29 bellard
}
797 c896fe29 bellard
798 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
799 c896fe29 bellard
{
800 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_sar_i64, ret, arg1, arg2);
801 c896fe29 bellard
}
802 c896fe29 bellard
803 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
804 c896fe29 bellard
{
805 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
806 c896fe29 bellard
}
807 c896fe29 bellard
808 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
809 c896fe29 bellard
                                      int label_index)
810 c896fe29 bellard
{
811 a7812ae4 pbrook
    tcg_gen_op6ii_i32(INDEX_op_brcond2_i32,
812 a7812ae4 pbrook
                      TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2),
813 a7812ae4 pbrook
                      TCGV_HIGH(arg2), cond, label_index);
814 c896fe29 bellard
}
815 c896fe29 bellard
816 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
817 c896fe29 bellard
{
818 a7812ae4 pbrook
    TCGv_i64 t0;
819 a7812ae4 pbrook
    TCGv_i32 t1;
820 c896fe29 bellard
821 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
822 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
823 a7812ae4 pbrook
824 a7812ae4 pbrook
    tcg_gen_op4_i32(INDEX_op_mulu2_i32, TCGV_LOW(t0), TCGV_HIGH(t0),
825 a7812ae4 pbrook
                    TCGV_LOW(arg1), TCGV_LOW(arg2));
826 a7812ae4 pbrook
827 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_LOW(arg1), TCGV_HIGH(arg2));
828 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
829 a7812ae4 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), TCGV_LOW(arg2));
830 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
831 a7812ae4 pbrook
832 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
833 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
834 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
835 c896fe29 bellard
}
836 c896fe29 bellard
837 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
838 c896fe29 bellard
{
839 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_div_i64, ret, arg1, arg2);
840 c896fe29 bellard
}
841 c896fe29 bellard
842 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
843 c896fe29 bellard
{
844 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_rem_i64, ret, arg1, arg2);
845 c896fe29 bellard
}
846 c896fe29 bellard
847 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
848 c896fe29 bellard
{
849 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_divu_i64, ret, arg1, arg2);
850 c896fe29 bellard
}
851 c896fe29 bellard
852 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
853 c896fe29 bellard
{
854 a7812ae4 pbrook
    tcg_gen_helper64(tcg_helper_remu_i64, ret, arg1, arg2);
855 c896fe29 bellard
}
856 c896fe29 bellard
857 c896fe29 bellard
#else
858 c896fe29 bellard
859 a7812ae4 pbrook
static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
860 c896fe29 bellard
{
861 a7812ae4 pbrook
    if (GET_TCGV_I64(ret) != GET_TCGV_I64(arg))
862 a7812ae4 pbrook
        tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
863 c896fe29 bellard
}
864 c896fe29 bellard
865 a7812ae4 pbrook
static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
866 c896fe29 bellard
{
867 a7812ae4 pbrook
    tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
868 c896fe29 bellard
}
869 c896fe29 bellard
870 a7812ae4 pbrook
static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_i64 arg2,
871 ac56dd48 pbrook
                                    tcg_target_long offset)
872 c896fe29 bellard
{
873 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
874 c896fe29 bellard
}
875 c896fe29 bellard
876 a7812ae4 pbrook
static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_i64 arg2,
877 ac56dd48 pbrook
                                    tcg_target_long offset)
878 c896fe29 bellard
{
879 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
880 c896fe29 bellard
}
881 c896fe29 bellard
882 a7812ae4 pbrook
static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_i64 arg2,
883 ac56dd48 pbrook
                                     tcg_target_long offset)
884 c896fe29 bellard
{
885 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
886 c896fe29 bellard
}
887 c896fe29 bellard
888 a7812ae4 pbrook
static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_i64 arg2,
889 ac56dd48 pbrook
                                     tcg_target_long offset)
890 c896fe29 bellard
{
891 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
892 c896fe29 bellard
}
893 c896fe29 bellard
894 a7812ae4 pbrook
static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_i64 arg2,
895 ac56dd48 pbrook
                                     tcg_target_long offset)
896 c896fe29 bellard
{
897 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
898 c896fe29 bellard
}
899 c896fe29 bellard
900 a7812ae4 pbrook
static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_i64 arg2,
901 ac56dd48 pbrook
                                     tcg_target_long offset)
902 c896fe29 bellard
{
903 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
904 c896fe29 bellard
}
905 c896fe29 bellard
906 a7812ae4 pbrook
static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_i64 arg2, tcg_target_long offset)
907 c896fe29 bellard
{
908 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
909 c896fe29 bellard
}
910 c896fe29 bellard
911 a7812ae4 pbrook
static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_i64 arg2,
912 ac56dd48 pbrook
                                   tcg_target_long offset)
913 c896fe29 bellard
{
914 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
915 c896fe29 bellard
}
916 c896fe29 bellard
917 a7812ae4 pbrook
static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_i64 arg2,
918 ac56dd48 pbrook
                                    tcg_target_long offset)
919 c896fe29 bellard
{
920 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
921 c896fe29 bellard
}
922 c896fe29 bellard
923 a7812ae4 pbrook
static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_i64 arg2,
924 ac56dd48 pbrook
                                    tcg_target_long offset)
925 c896fe29 bellard
{
926 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
927 c896fe29 bellard
}
928 c896fe29 bellard
929 a7812ae4 pbrook
static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_i64 arg2, tcg_target_long offset)
930 c896fe29 bellard
{
931 a7812ae4 pbrook
    tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
932 c896fe29 bellard
}
933 c896fe29 bellard
934 a7812ae4 pbrook
static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
935 c896fe29 bellard
{
936 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
937 c896fe29 bellard
}
938 c896fe29 bellard
939 a7812ae4 pbrook
static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
940 c896fe29 bellard
{
941 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
942 c896fe29 bellard
}
943 c896fe29 bellard
944 a7812ae4 pbrook
static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
945 c896fe29 bellard
{
946 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
947 c896fe29 bellard
}
948 c896fe29 bellard
949 a7812ae4 pbrook
static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
950 c896fe29 bellard
{
951 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
952 e8996ee0 bellard
    tcg_gen_and_i64(ret, arg1, t0);
953 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
954 c896fe29 bellard
}
955 c896fe29 bellard
956 a7812ae4 pbrook
static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
957 c896fe29 bellard
{
958 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
959 c896fe29 bellard
}
960 c896fe29 bellard
961 a7812ae4 pbrook
static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
962 c896fe29 bellard
{
963 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
964 e8996ee0 bellard
    tcg_gen_or_i64(ret, arg1, t0);
965 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
966 c896fe29 bellard
}
967 c896fe29 bellard
968 a7812ae4 pbrook
static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
969 c896fe29 bellard
{
970 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
971 c896fe29 bellard
}
972 c896fe29 bellard
973 a7812ae4 pbrook
static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
974 c896fe29 bellard
{
975 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
976 e8996ee0 bellard
    tcg_gen_xor_i64(ret, arg1, t0);
977 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
978 c896fe29 bellard
}
979 c896fe29 bellard
980 a7812ae4 pbrook
static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
981 c896fe29 bellard
{
982 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
983 c896fe29 bellard
}
984 c896fe29 bellard
985 a7812ae4 pbrook
static inline void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
986 c896fe29 bellard
{
987 34151a20 bellard
    if (arg2 == 0) {
988 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
989 34151a20 bellard
    } else {
990 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
991 e8996ee0 bellard
        tcg_gen_shl_i64(ret, arg1, t0);
992 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
993 34151a20 bellard
    }
994 c896fe29 bellard
}
995 c896fe29 bellard
996 a7812ae4 pbrook
static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
997 c896fe29 bellard
{
998 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
999 c896fe29 bellard
}
1000 c896fe29 bellard
1001 a7812ae4 pbrook
static inline void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1002 c896fe29 bellard
{
1003 34151a20 bellard
    if (arg2 == 0) {
1004 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1005 34151a20 bellard
    } else {
1006 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1007 e8996ee0 bellard
        tcg_gen_shr_i64(ret, arg1, t0);
1008 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1009 34151a20 bellard
    }
1010 c896fe29 bellard
}
1011 c896fe29 bellard
1012 a7812ae4 pbrook
static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1013 c896fe29 bellard
{
1014 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
1015 c896fe29 bellard
}
1016 c896fe29 bellard
1017 a7812ae4 pbrook
static inline void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1018 c896fe29 bellard
{
1019 34151a20 bellard
    if (arg2 == 0) {
1020 34151a20 bellard
        tcg_gen_mov_i64(ret, arg1);
1021 34151a20 bellard
    } else {
1022 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1023 e8996ee0 bellard
        tcg_gen_sar_i64(ret, arg1, t0);
1024 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1025 34151a20 bellard
    }
1026 c896fe29 bellard
}
1027 c896fe29 bellard
1028 a7812ae4 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv_i64 arg1, TCGv_i64 arg2,
1029 c896fe29 bellard
                                      int label_index)
1030 c896fe29 bellard
{
1031 a7812ae4 pbrook
    tcg_gen_op4ii_i64(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
1032 c896fe29 bellard
}
1033 c896fe29 bellard
1034 a7812ae4 pbrook
static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1035 c896fe29 bellard
{
1036 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
1037 c896fe29 bellard
}
1038 c896fe29 bellard
1039 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
1040 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1041 c896fe29 bellard
{
1042 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_div_i64, ret, arg1, arg2);
1043 c896fe29 bellard
}
1044 c896fe29 bellard
1045 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1046 c896fe29 bellard
{
1047 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_rem_i64, ret, arg1, arg2);
1048 c896fe29 bellard
}
1049 c896fe29 bellard
1050 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1051 c896fe29 bellard
{
1052 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_divu_i64, ret, arg1, arg2);
1053 c896fe29 bellard
}
1054 c896fe29 bellard
1055 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1056 c896fe29 bellard
{
1057 a7812ae4 pbrook
    tcg_gen_op3_i64(INDEX_op_remu_i64, ret, arg1, arg2);
1058 c896fe29 bellard
}
1059 c896fe29 bellard
#else
1060 a7812ae4 pbrook
static inline void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1061 c896fe29 bellard
{
1062 a7812ae4 pbrook
    TCGv_i64 t0;
1063 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1064 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1065 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
1066 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1067 c896fe29 bellard
}
1068 c896fe29 bellard
1069 a7812ae4 pbrook
static inline void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1070 c896fe29 bellard
{
1071 a7812ae4 pbrook
    TCGv_i64 t0;
1072 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1073 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
1074 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
1075 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1076 c896fe29 bellard
}
1077 c896fe29 bellard
1078 a7812ae4 pbrook
static inline void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1079 c896fe29 bellard
{
1080 a7812ae4 pbrook
    TCGv_i64 t0;
1081 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1082 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1083 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
1084 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1085 c896fe29 bellard
}
1086 c896fe29 bellard
1087 a7812ae4 pbrook
static inline void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1088 c896fe29 bellard
{
1089 a7812ae4 pbrook
    TCGv_i64 t0;
1090 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1091 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
1092 a7812ae4 pbrook
    tcg_gen_op5_i64(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
1093 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1094 c896fe29 bellard
}
1095 c896fe29 bellard
#endif
1096 c896fe29 bellard
1097 c896fe29 bellard
#endif
1098 c896fe29 bellard
1099 a7812ae4 pbrook
static inline void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1100 6359706f aurel32
{
1101 6359706f aurel32
    /* some cases can be optimized here */
1102 6359706f aurel32
    if (arg2 == 0) {
1103 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1104 6359706f aurel32
    } else {
1105 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1106 6359706f aurel32
        tcg_gen_add_i64(ret, arg1, t0);
1107 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1108 6359706f aurel32
    }
1109 6359706f aurel32
}
1110 6359706f aurel32
1111 a7812ae4 pbrook
static inline void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2)
1112 0045734a aurel32
{
1113 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg1);
1114 0045734a aurel32
    tcg_gen_sub_i64(ret, t0, arg2);
1115 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1116 0045734a aurel32
}
1117 0045734a aurel32
1118 a7812ae4 pbrook
static inline void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1119 6359706f aurel32
{
1120 6359706f aurel32
    /* some cases can be optimized here */
1121 6359706f aurel32
    if (arg2 == 0) {
1122 6359706f aurel32
        tcg_gen_mov_i64(ret, arg1);
1123 6359706f aurel32
    } else {
1124 a7812ae4 pbrook
        TCGv_i64 t0 = tcg_const_i64(arg2);
1125 6359706f aurel32
        tcg_gen_sub_i64(ret, arg1, t0);
1126 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1127 6359706f aurel32
    }
1128 6359706f aurel32
}
1129 a7812ae4 pbrook
static inline void tcg_gen_brcondi_i64(int cond, TCGv_i64 arg1, int64_t arg2,
1130 f02bb954 aurel32
                                       int label_index)
1131 f02bb954 aurel32
{
1132 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1133 f02bb954 aurel32
    tcg_gen_brcond_i64(cond, arg1, t0, label_index);
1134 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1135 f02bb954 aurel32
}
1136 f02bb954 aurel32
1137 a7812ae4 pbrook
static inline void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1138 f02bb954 aurel32
{
1139 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(arg2);
1140 f02bb954 aurel32
    tcg_gen_mul_i64(ret, arg1, t0);
1141 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1142 f02bb954 aurel32
}
1143 f02bb954 aurel32
1144 6359706f aurel32
1145 c896fe29 bellard
/***************************************/
1146 c896fe29 bellard
/* optional operations */
1147 c896fe29 bellard
1148 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg)
1149 c896fe29 bellard
{
1150 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
1151 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext8s_i32, ret, arg);
1152 c896fe29 bellard
#else
1153 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
1154 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
1155 c896fe29 bellard
#endif
1156 c896fe29 bellard
}
1157 c896fe29 bellard
1158 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg)
1159 c896fe29 bellard
{
1160 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
1161 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_ext16s_i32, ret, arg);
1162 c896fe29 bellard
#else
1163 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
1164 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
1165 c896fe29 bellard
#endif
1166 c896fe29 bellard
}
1167 c896fe29 bellard
1168 86831435 pbrook
/* These are currently just for convenience.
1169 86831435 pbrook
   We assume a target will recognise these automatically .  */
1170 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg)
1171 86831435 pbrook
{
1172 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
1173 86831435 pbrook
}
1174 86831435 pbrook
1175 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg)
1176 86831435 pbrook
{
1177 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
1178 86831435 pbrook
}
1179 86831435 pbrook
1180 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
1181 a7812ae4 pbrook
static inline void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg)
1182 c896fe29 bellard
{
1183 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
1184 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_bswap16_i32, ret, arg);
1185 c896fe29 bellard
#else
1186 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1187 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1188 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1189 c896fe29 bellard
    
1190 c896fe29 bellard
    tcg_gen_shri_i32(t0, arg, 8);
1191 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x000000ff);
1192 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1193 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1194 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1195 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1196 c896fe29 bellard
#endif
1197 c896fe29 bellard
}
1198 c896fe29 bellard
1199 a7812ae4 pbrook
static inline void tcg_gen_bswap_i32(TCGv_i32 ret, TCGv_i32 arg)
1200 c896fe29 bellard
{
1201 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i32
1202 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_bswap_i32, ret, arg);
1203 c896fe29 bellard
#else
1204 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1205 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1206 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1207 c896fe29 bellard
    
1208 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1209 c896fe29 bellard
    
1210 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1211 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1212 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1213 c896fe29 bellard
    
1214 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1215 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1216 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1217 c896fe29 bellard
    
1218 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1219 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1220 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1221 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1222 c896fe29 bellard
#endif
1223 c896fe29 bellard
}
1224 c896fe29 bellard
1225 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1226 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1227 c896fe29 bellard
{
1228 a7812ae4 pbrook
    tcg_gen_ext8s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1229 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1230 c896fe29 bellard
}
1231 c896fe29 bellard
1232 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1233 c896fe29 bellard
{
1234 a7812ae4 pbrook
    tcg_gen_ext16s_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1235 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1236 c896fe29 bellard
}
1237 c896fe29 bellard
1238 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1239 c896fe29 bellard
{
1240 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1241 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1242 c896fe29 bellard
}
1243 c896fe29 bellard
1244 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1245 86831435 pbrook
{
1246 a7812ae4 pbrook
    tcg_gen_ext8u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1247 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1248 86831435 pbrook
}
1249 86831435 pbrook
1250 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1251 86831435 pbrook
{
1252 a7812ae4 pbrook
    tcg_gen_ext16u_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1253 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1254 86831435 pbrook
}
1255 86831435 pbrook
1256 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1257 86831435 pbrook
{
1258 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg));
1259 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1260 86831435 pbrook
}
1261 86831435 pbrook
1262 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1263 c896fe29 bellard
{
1264 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, TCGV_LOW(arg));
1265 c896fe29 bellard
}
1266 c896fe29 bellard
1267 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1268 c896fe29 bellard
{
1269 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1270 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1271 c896fe29 bellard
}
1272 c896fe29 bellard
1273 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1274 c896fe29 bellard
{
1275 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), arg);
1276 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1277 c896fe29 bellard
}
1278 c896fe29 bellard
1279 a7812ae4 pbrook
static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg)
1280 c896fe29 bellard
{
1281 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1282 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1283 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1284 c896fe29 bellard
1285 a7812ae4 pbrook
    tcg_gen_bswap_i32(t0, TCGV_LOW(arg));
1286 ac56dd48 pbrook
    tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
1287 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(ret), t1);
1288 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1289 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1290 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1291 c896fe29 bellard
}
1292 c896fe29 bellard
#else
1293 c896fe29 bellard
1294 a7812ae4 pbrook
static inline void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg)
1295 c896fe29 bellard
{
1296 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1297 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext8s_i64, ret, arg);
1298 c896fe29 bellard
#else
1299 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1300 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1301 c896fe29 bellard
#endif
1302 c896fe29 bellard
}
1303 c896fe29 bellard
1304 a7812ae4 pbrook
static inline void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg)
1305 c896fe29 bellard
{
1306 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1307 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext16s_i64, ret, arg);
1308 c896fe29 bellard
#else
1309 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1310 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1311 c896fe29 bellard
#endif
1312 c896fe29 bellard
}
1313 c896fe29 bellard
1314 a7812ae4 pbrook
static inline void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
1315 c896fe29 bellard
{
1316 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1317 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_ext32s_i64, ret, arg);
1318 c896fe29 bellard
#else
1319 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1320 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1321 c896fe29 bellard
#endif
1322 c896fe29 bellard
}
1323 c896fe29 bellard
1324 a7812ae4 pbrook
static inline void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg)
1325 86831435 pbrook
{
1326 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1327 86831435 pbrook
}
1328 86831435 pbrook
1329 a7812ae4 pbrook
static inline void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg)
1330 86831435 pbrook
{
1331 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1332 86831435 pbrook
}
1333 86831435 pbrook
1334 a7812ae4 pbrook
static inline void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg)
1335 86831435 pbrook
{
1336 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1337 86831435 pbrook
}
1338 86831435 pbrook
1339 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1340 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1341 a7812ae4 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv_i32 ret, TCGv_i64 arg)
1342 c896fe29 bellard
{
1343 a7812ae4 pbrook
    tcg_gen_mov_i32(ret, MAKE_TCGV_I32(GET_TCGV_I64(arg)));
1344 c896fe29 bellard
}
1345 c896fe29 bellard
1346 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1347 c896fe29 bellard
   registers */
1348 a7812ae4 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1349 c896fe29 bellard
{
1350 a7812ae4 pbrook
    tcg_gen_andi_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)), 0xffffffffu);
1351 c896fe29 bellard
}
1352 c896fe29 bellard
1353 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1354 c896fe29 bellard
   registers */
1355 a7812ae4 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg)
1356 c896fe29 bellard
{
1357 a7812ae4 pbrook
    tcg_gen_ext32s_i64(ret, MAKE_TCGV_I64(GET_TCGV_I32(arg)));
1358 c896fe29 bellard
}
1359 c896fe29 bellard
1360 a7812ae4 pbrook
static inline void tcg_gen_bswap_i64(TCGv_i64 ret, TCGv_i64 arg)
1361 c896fe29 bellard
{
1362 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i64
1363 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_bswap_i64, ret, arg);
1364 c896fe29 bellard
#else
1365 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1366 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1367 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1368 c896fe29 bellard
    
1369 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1370 c896fe29 bellard
    
1371 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1372 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1373 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1374 c896fe29 bellard
    
1375 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1376 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1377 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1378 c896fe29 bellard
1379 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1380 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1381 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1382 c896fe29 bellard
1383 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1384 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1385 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1386 c896fe29 bellard
    
1387 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1388 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1389 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1390 c896fe29 bellard
1391 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1392 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1393 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1394 c896fe29 bellard
1395 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1396 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1397 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1398 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1399 c896fe29 bellard
#endif
1400 c896fe29 bellard
}
1401 c896fe29 bellard
1402 c896fe29 bellard
#endif
1403 c896fe29 bellard
1404 a7812ae4 pbrook
static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
1405 390efc54 pbrook
{
1406 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1407 a7812ae4 pbrook
    tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
1408 390efc54 pbrook
#else
1409 a7812ae4 pbrook
    TCGv_i32 t0 = tcg_const_i32(0);
1410 e8996ee0 bellard
    tcg_gen_sub_i32(ret, t0, arg);
1411 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1412 390efc54 pbrook
#endif
1413 390efc54 pbrook
}
1414 390efc54 pbrook
1415 a7812ae4 pbrook
static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
1416 390efc54 pbrook
{
1417 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1418 a7812ae4 pbrook
    tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
1419 390efc54 pbrook
#else
1420 a7812ae4 pbrook
    TCGv_i64 t0 = tcg_const_i64(0);
1421 e8996ee0 bellard
    tcg_gen_sub_i64(ret, t0, arg);
1422 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1423 390efc54 pbrook
#endif
1424 390efc54 pbrook
}
1425 390efc54 pbrook
1426 a7812ae4 pbrook
static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
1427 0b6ce4cf bellard
{
1428 e8996ee0 bellard
    tcg_gen_xori_i32(ret, arg, -1);
1429 0b6ce4cf bellard
}
1430 0b6ce4cf bellard
1431 a7812ae4 pbrook
static inline void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg)
1432 0b6ce4cf bellard
{
1433 e8996ee0 bellard
    tcg_gen_xori_i64(ret, arg, -1);
1434 0b6ce4cf bellard
}
1435 5ff9d6a4 bellard
1436 a7812ae4 pbrook
static inline void tcg_gen_discard_i32(TCGv_i32 arg)
1437 5ff9d6a4 bellard
{
1438 a7812ae4 pbrook
    tcg_gen_op1_i32(INDEX_op_discard, arg);
1439 5ff9d6a4 bellard
}
1440 5ff9d6a4 bellard
1441 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1442 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1443 5ff9d6a4 bellard
{
1444 a7812ae4 pbrook
    tcg_gen_discard_i32(TCGV_LOW(arg));
1445 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1446 5ff9d6a4 bellard
}
1447 5ff9d6a4 bellard
#else
1448 a7812ae4 pbrook
static inline void tcg_gen_discard_i64(TCGv_i64 arg)
1449 5ff9d6a4 bellard
{
1450 a7812ae4 pbrook
    tcg_gen_op1_i64(INDEX_op_discard, arg);
1451 5ff9d6a4 bellard
}
1452 5ff9d6a4 bellard
#endif
1453 5ff9d6a4 bellard
1454 a7812ae4 pbrook
static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high)
1455 36aa55dc pbrook
{
1456 36aa55dc pbrook
#if TCG_TARGET_REG_BITS == 32
1457 a7812ae4 pbrook
    tcg_gen_mov_i32(TCGV_LOW(dest), low);
1458 36aa55dc pbrook
    tcg_gen_mov_i32(TCGV_HIGH(dest), high);
1459 36aa55dc pbrook
#else
1460 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1461 36aa55dc pbrook
    /* This extension is only needed for type correctness.
1462 36aa55dc pbrook
       We may be able to do better given target specific information.  */
1463 36aa55dc pbrook
    tcg_gen_extu_i32_i64(tmp, high);
1464 36aa55dc pbrook
    tcg_gen_shli_i64(tmp, tmp, 32);
1465 36aa55dc pbrook
    tcg_gen_extu_i32_i64(dest, low);
1466 36aa55dc pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1467 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1468 36aa55dc pbrook
#endif
1469 36aa55dc pbrook
}
1470 36aa55dc pbrook
1471 a7812ae4 pbrook
static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high)
1472 945ca823 blueswir1
{
1473 945ca823 blueswir1
#if TCG_TARGET_REG_BITS == 32
1474 a7812ae4 pbrook
    tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high));
1475 945ca823 blueswir1
#else
1476 a7812ae4 pbrook
    TCGv_i64 tmp = tcg_temp_new_i64();
1477 88422e2e pbrook
    tcg_gen_ext32u_i64(dest, low);
1478 945ca823 blueswir1
    tcg_gen_shli_i64(tmp, high, 32);
1479 88422e2e pbrook
    tcg_gen_or_i64(dest, dest, tmp);
1480 a7812ae4 pbrook
    tcg_temp_free_i64(tmp);
1481 945ca823 blueswir1
#endif
1482 945ca823 blueswir1
}
1483 945ca823 blueswir1
1484 a7812ae4 pbrook
static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1485 f24cb33e aurel32
{
1486 a7812ae4 pbrook
    TCGv_i32 t0;
1487 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1488 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1489 f24cb33e aurel32
    tcg_gen_and_i32(ret, arg1, t0);
1490 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1491 f24cb33e aurel32
}
1492 f24cb33e aurel32
1493 a7812ae4 pbrook
static inline void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1494 f24cb33e aurel32
{
1495 a7812ae4 pbrook
    TCGv_i64 t0;
1496 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1497 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1498 f24cb33e aurel32
    tcg_gen_and_i64(ret, arg1, t0);
1499 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1500 f24cb33e aurel32
}
1501 f24cb33e aurel32
1502 a7812ae4 pbrook
static inline void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1503 f24cb33e aurel32
{
1504 a7812ae4 pbrook
    TCGv_i32 t0;
1505 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1506 f24cb33e aurel32
    tcg_gen_xor_i32(t0, arg1, arg2);
1507 f24cb33e aurel32
    tcg_gen_not_i32(ret, t0);
1508 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1509 f24cb33e aurel32
}
1510 f24cb33e aurel32
1511 a7812ae4 pbrook
static inline void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1512 f24cb33e aurel32
{
1513 a7812ae4 pbrook
    TCGv_i64 t0;
1514 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1515 f24cb33e aurel32
    tcg_gen_xor_i64(t0, arg1, arg2);
1516 f24cb33e aurel32
    tcg_gen_not_i64(ret, t0);
1517 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1518 f24cb33e aurel32
}
1519 f24cb33e aurel32
1520 a7812ae4 pbrook
static inline void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1521 f24cb33e aurel32
{
1522 a7812ae4 pbrook
    TCGv_i32 t0;
1523 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1524 f24cb33e aurel32
    tcg_gen_and_i32(t0, arg1, arg2);
1525 f24cb33e aurel32
    tcg_gen_not_i32(ret, t0);
1526 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1527 f24cb33e aurel32
}
1528 f24cb33e aurel32
1529 a7812ae4 pbrook
static inline void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1530 f24cb33e aurel32
{
1531 a7812ae4 pbrook
    TCGv_i64 t0;
1532 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1533 f24cb33e aurel32
    tcg_gen_and_i64(t0, arg1, arg2);
1534 f24cb33e aurel32
    tcg_gen_not_i64(ret, t0);
1535 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1536 f24cb33e aurel32
}
1537 f24cb33e aurel32
1538 a7812ae4 pbrook
static inline void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1539 f24cb33e aurel32
{
1540 a7812ae4 pbrook
    TCGv_i32 t0;
1541 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1542 f24cb33e aurel32
    tcg_gen_or_i32(t0, arg1, arg2);
1543 f24cb33e aurel32
    tcg_gen_not_i32(ret, t0);
1544 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1545 f24cb33e aurel32
}
1546 f24cb33e aurel32
1547 a7812ae4 pbrook
static inline void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1548 f24cb33e aurel32
{
1549 a7812ae4 pbrook
    TCGv_i64 t0;
1550 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1551 f24cb33e aurel32
    tcg_gen_or_i64(t0, arg1, arg2);
1552 f24cb33e aurel32
    tcg_gen_not_i64(ret, t0);
1553 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1554 f24cb33e aurel32
}
1555 f24cb33e aurel32
1556 a7812ae4 pbrook
static inline void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1557 f24cb33e aurel32
{
1558 a7812ae4 pbrook
    TCGv_i32 t0;
1559 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1560 f24cb33e aurel32
    tcg_gen_not_i32(t0, arg2);
1561 f24cb33e aurel32
    tcg_gen_or_i32(ret, arg1, t0);
1562 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1563 f24cb33e aurel32
}
1564 f24cb33e aurel32
1565 a7812ae4 pbrook
static inline void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1566 f24cb33e aurel32
{
1567 a7812ae4 pbrook
    TCGv_i64 t0;
1568 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1569 f24cb33e aurel32
    tcg_gen_not_i64(t0, arg2);
1570 f24cb33e aurel32
    tcg_gen_or_i64(ret, arg1, t0);
1571 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1572 f24cb33e aurel32
}
1573 f24cb33e aurel32
1574 a7812ae4 pbrook
static inline void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1575 15824571 aurel32
{
1576 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1577 15824571 aurel32
1578 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1579 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1580 15824571 aurel32
    tcg_gen_shl_i32(t0, arg1, arg2);
1581 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1582 15824571 aurel32
    tcg_gen_shr_i32(t1, arg1, t1);
1583 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1584 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1585 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1586 15824571 aurel32
}
1587 15824571 aurel32
1588 a7812ae4 pbrook
static inline void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1589 15824571 aurel32
{
1590 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1591 15824571 aurel32
1592 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1593 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1594 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1595 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1596 15824571 aurel32
    tcg_gen_shr_i64(t1, arg1, t1);
1597 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1598 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1599 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1600 15824571 aurel32
}
1601 15824571 aurel32
1602 a7812ae4 pbrook
static inline void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1603 15824571 aurel32
{
1604 15824571 aurel32
    /* some cases can be optimized here */
1605 15824571 aurel32
    if (arg2 == 0) {
1606 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1607 15824571 aurel32
    } else {
1608 a7812ae4 pbrook
        TCGv_i32 t0, t1;
1609 a7812ae4 pbrook
        t0 = tcg_temp_new_i32();
1610 a7812ae4 pbrook
        t1 = tcg_temp_new_i32();
1611 15824571 aurel32
        tcg_gen_shli_i32(t0, arg1, arg2);
1612 15824571 aurel32
        tcg_gen_shri_i32(t1, arg1, 32 - arg2);
1613 15824571 aurel32
        tcg_gen_or_i32(ret, t0, t1);
1614 a7812ae4 pbrook
        tcg_temp_free_i32(t0);
1615 a7812ae4 pbrook
        tcg_temp_free_i32(t1);
1616 15824571 aurel32
    }
1617 15824571 aurel32
}
1618 15824571 aurel32
1619 a7812ae4 pbrook
static inline void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1620 15824571 aurel32
{
1621 15824571 aurel32
    /* some cases can be optimized here */
1622 15824571 aurel32
    if (arg2 == 0) {
1623 15824571 aurel32
        tcg_gen_mov_i64(ret, arg1);
1624 15824571 aurel32
    } else {
1625 a7812ae4 pbrook
        TCGv_i64 t0, t1;
1626 a7812ae4 pbrook
        t0 = tcg_temp_new_i64();
1627 a7812ae4 pbrook
        t1 = tcg_temp_new_i64();
1628 15824571 aurel32
        tcg_gen_shli_i64(t0, arg1, arg2);
1629 15824571 aurel32
        tcg_gen_shri_i64(t1, arg1, 64 - arg2);
1630 15824571 aurel32
        tcg_gen_or_i64(ret, t0, t1);
1631 a7812ae4 pbrook
        tcg_temp_free_i64(t0);
1632 a7812ae4 pbrook
        tcg_temp_free_i64(t1);
1633 15824571 aurel32
    }
1634 15824571 aurel32
}
1635 15824571 aurel32
1636 a7812ae4 pbrook
static inline void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
1637 15824571 aurel32
{
1638 a7812ae4 pbrook
    TCGv_i32 t0, t1;
1639 15824571 aurel32
1640 a7812ae4 pbrook
    t0 = tcg_temp_new_i32();
1641 a7812ae4 pbrook
    t1 = tcg_temp_new_i32();
1642 15824571 aurel32
    tcg_gen_shr_i32(t0, arg1, arg2);
1643 15824571 aurel32
    tcg_gen_subfi_i32(t1, 32, arg2);
1644 15824571 aurel32
    tcg_gen_shl_i32(t1, arg1, t1);
1645 15824571 aurel32
    tcg_gen_or_i32(ret, t0, t1);
1646 a7812ae4 pbrook
    tcg_temp_free_i32(t0);
1647 a7812ae4 pbrook
    tcg_temp_free_i32(t1);
1648 15824571 aurel32
}
1649 15824571 aurel32
1650 a7812ae4 pbrook
static inline void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
1651 15824571 aurel32
{
1652 a7812ae4 pbrook
    TCGv_i64 t0, t1;
1653 15824571 aurel32
1654 a7812ae4 pbrook
    t0 = tcg_temp_new_i64();
1655 a7812ae4 pbrook
    t1 = tcg_temp_new_i64();
1656 15824571 aurel32
    tcg_gen_shl_i64(t0, arg1, arg2);
1657 15824571 aurel32
    tcg_gen_subfi_i64(t1, 64, arg2);
1658 15824571 aurel32
    tcg_gen_shl_i64(t1, arg1, t1);
1659 15824571 aurel32
    tcg_gen_or_i64(ret, t0, t1);
1660 a7812ae4 pbrook
    tcg_temp_free_i64(t0);
1661 a7812ae4 pbrook
    tcg_temp_free_i64(t1);
1662 15824571 aurel32
}
1663 15824571 aurel32
1664 a7812ae4 pbrook
static inline void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
1665 15824571 aurel32
{
1666 15824571 aurel32
    /* some cases can be optimized here */
1667 15824571 aurel32
    if (arg2 == 0) {
1668 15824571 aurel32
        tcg_gen_mov_i32(ret, arg1);
1669 15824571 aurel32
    } else {
1670 15824571 aurel32
        tcg_gen_rotli_i32(ret, arg1, 32 - arg2);
1671 15824571 aurel32
    }
1672 15824571 aurel32
}
1673 15824571 aurel32
1674 a7812ae4 pbrook
static inline void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
1675 15824571 aurel32
{
1676 15824571 aurel32
    /* some cases can be optimized here */
1677 15824571 aurel32
    if (arg2 == 0) {
1678 de3526b2 pbrook
        tcg_gen_mov_i64(ret, arg1);
1679 15824571 aurel32
    } else {
1680 15824571 aurel32
        tcg_gen_rotli_i64(ret, arg1, 64 - arg2);
1681 15824571 aurel32
    }
1682 15824571 aurel32
}
1683 15824571 aurel32
1684 c896fe29 bellard
/***************************************/
1685 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1686 c896fe29 bellard
   type. */
1687 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1688 c896fe29 bellard
#error must include QEMU headers
1689 c896fe29 bellard
#endif
1690 c896fe29 bellard
1691 a7812ae4 pbrook
#if TARGET_LONG_BITS == 32
1692 a7812ae4 pbrook
#define TCGv TCGv_i32
1693 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i32()
1694 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i32
1695 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i32
1696 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i32()
1697 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i32
1698 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i32
1699 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i32
1700 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
1701 a7812ae4 pbrook
#define TCGV_EQUAL(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
1702 a7812ae4 pbrook
#else
1703 a7812ae4 pbrook
#define TCGv TCGv_i64
1704 a7812ae4 pbrook
#define tcg_temp_new() tcg_temp_new_i64()
1705 a7812ae4 pbrook
#define tcg_global_reg_new tcg_global_reg_new_i64
1706 a7812ae4 pbrook
#define tcg_global_mem_new tcg_global_mem_new_i64
1707 df9247b2 aurel32
#define tcg_temp_local_new() tcg_temp_local_new_i64()
1708 a7812ae4 pbrook
#define tcg_temp_free tcg_temp_free_i64
1709 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op tcg_gen_op3i_i64
1710 a7812ae4 pbrook
#define tcg_gen_qemu_ldst_op_i64 tcg_gen_qemu_ldst_op_i64_i64
1711 a7812ae4 pbrook
#define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
1712 a7812ae4 pbrook
#define TCGV_EQUAL(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
1713 a7812ae4 pbrook
#endif
1714 a7812ae4 pbrook
1715 7e4597d7 bellard
/* debug info: write the PC of the corresponding QEMU CPU instruction */
1716 7e4597d7 bellard
static inline void tcg_gen_debug_insn_start(uint64_t pc)
1717 7e4597d7 bellard
{
1718 7e4597d7 bellard
    /* XXX: must really use a 32 bit size for TCGArg in all cases */
1719 7e4597d7 bellard
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
1720 bcb0126f pbrook
    tcg_gen_op2ii(INDEX_op_debug_insn_start, 
1721 bcb0126f pbrook
                  (uint32_t)(pc), (uint32_t)(pc >> 32));
1722 7e4597d7 bellard
#else
1723 7e4597d7 bellard
    tcg_gen_op1i(INDEX_op_debug_insn_start, pc);
1724 7e4597d7 bellard
#endif
1725 7e4597d7 bellard
}
1726 7e4597d7 bellard
1727 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1728 c896fe29 bellard
{
1729 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1730 c896fe29 bellard
}
1731 c896fe29 bellard
1732 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1733 c896fe29 bellard
{
1734 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1735 c896fe29 bellard
}
1736 c896fe29 bellard
1737 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1738 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1739 c896fe29 bellard
{
1740 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1741 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1742 c896fe29 bellard
#else
1743 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8u, TCGV_LOW(ret), TCGV_LOW(addr),
1744 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1745 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1746 c896fe29 bellard
#endif
1747 c896fe29 bellard
}
1748 c896fe29 bellard
1749 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1750 c896fe29 bellard
{
1751 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1752 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1753 c896fe29 bellard
#else
1754 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld8s, TCGV_LOW(ret), TCGV_LOW(addr),
1755 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1756 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1757 c896fe29 bellard
#endif
1758 c896fe29 bellard
}
1759 c896fe29 bellard
1760 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1761 c896fe29 bellard
{
1762 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1763 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1764 c896fe29 bellard
#else
1765 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16u, TCGV_LOW(ret), TCGV_LOW(addr),
1766 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1767 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1768 c896fe29 bellard
#endif
1769 c896fe29 bellard
}
1770 c896fe29 bellard
1771 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1772 c896fe29 bellard
{
1773 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1774 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1775 c896fe29 bellard
#else
1776 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld16s, TCGV_LOW(ret), TCGV_LOW(addr),
1777 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1778 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1779 c896fe29 bellard
#endif
1780 c896fe29 bellard
}
1781 c896fe29 bellard
1782 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1783 c896fe29 bellard
{
1784 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1785 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1786 c896fe29 bellard
#else
1787 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1788 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1789 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1790 c896fe29 bellard
#endif
1791 c896fe29 bellard
}
1792 c896fe29 bellard
1793 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1794 c896fe29 bellard
{
1795 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1796 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1797 c896fe29 bellard
#else
1798 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld32u, TCGV_LOW(ret), TCGV_LOW(addr),
1799 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1800 a7812ae4 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), TCGV_LOW(ret), 31);
1801 c896fe29 bellard
#endif
1802 c896fe29 bellard
}
1803 c896fe29 bellard
1804 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1805 c896fe29 bellard
{
1806 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1807 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret), addr, mem_index);
1808 c896fe29 bellard
#else
1809 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_ld64, TCGV_LOW(ret), TCGV_HIGH(ret),
1810 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1811 c896fe29 bellard
#endif
1812 c896fe29 bellard
}
1813 c896fe29 bellard
1814 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1815 c896fe29 bellard
{
1816 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1817 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st8, arg, addr, mem_index);
1818 c896fe29 bellard
#else
1819 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st8, TCGV_LOW(arg), TCGV_LOW(addr),
1820 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1821 c896fe29 bellard
#endif
1822 c896fe29 bellard
}
1823 c896fe29 bellard
1824 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1825 c896fe29 bellard
{
1826 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1827 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st16, arg, addr, mem_index);
1828 c896fe29 bellard
#else
1829 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st16, TCGV_LOW(arg), TCGV_LOW(addr),
1830 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1831 c896fe29 bellard
#endif
1832 c896fe29 bellard
}
1833 c896fe29 bellard
1834 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1835 c896fe29 bellard
{
1836 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1837 a7812ae4 pbrook
    tcg_gen_op3i_i32(INDEX_op_qemu_st32, arg, addr, mem_index);
1838 c896fe29 bellard
#else
1839 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st32, TCGV_LOW(arg), TCGV_LOW(addr),
1840 a7812ae4 pbrook
                     TCGV_HIGH(addr), mem_index);
1841 c896fe29 bellard
#endif
1842 c896fe29 bellard
}
1843 c896fe29 bellard
1844 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1845 c896fe29 bellard
{
1846 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1847 a7812ae4 pbrook
    tcg_gen_op4i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg), addr,
1848 a7812ae4 pbrook
                     mem_index);
1849 c896fe29 bellard
#else
1850 a7812ae4 pbrook
    tcg_gen_op5i_i32(INDEX_op_qemu_st64, TCGV_LOW(arg), TCGV_HIGH(arg),
1851 a7812ae4 pbrook
                     TCGV_LOW(addr), TCGV_HIGH(addr), mem_index);
1852 c896fe29 bellard
#endif
1853 c896fe29 bellard
}
1854 c896fe29 bellard
1855 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
1856 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
1857 f8422f52 blueswir1
1858 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1859 c896fe29 bellard
1860 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1861 c896fe29 bellard
{
1862 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1863 c896fe29 bellard
}
1864 c896fe29 bellard
1865 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1866 c896fe29 bellard
{
1867 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1868 c896fe29 bellard
}
1869 c896fe29 bellard
1870 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1871 c896fe29 bellard
{
1872 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1873 c896fe29 bellard
}
1874 c896fe29 bellard
1875 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1876 c896fe29 bellard
{
1877 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1878 c896fe29 bellard
}
1879 c896fe29 bellard
1880 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1881 c896fe29 bellard
{
1882 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1883 c896fe29 bellard
}
1884 c896fe29 bellard
1885 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1886 c896fe29 bellard
{
1887 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1888 c896fe29 bellard
}
1889 c896fe29 bellard
1890 a7812ae4 pbrook
static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
1891 c896fe29 bellard
{
1892 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_ld64, ret, addr, mem_index);
1893 c896fe29 bellard
}
1894 c896fe29 bellard
1895 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1896 c896fe29 bellard
{
1897 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st8, arg, addr, mem_index);
1898 c896fe29 bellard
}
1899 c896fe29 bellard
1900 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1901 c896fe29 bellard
{
1902 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st16, arg, addr, mem_index);
1903 c896fe29 bellard
}
1904 c896fe29 bellard
1905 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1906 c896fe29 bellard
{
1907 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op(INDEX_op_qemu_st32, arg, addr, mem_index);
1908 c896fe29 bellard
}
1909 c896fe29 bellard
1910 a7812ae4 pbrook
static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
1911 c896fe29 bellard
{
1912 a7812ae4 pbrook
    tcg_gen_qemu_ldst_op_i64(INDEX_op_qemu_st64, arg, addr, mem_index);
1913 c896fe29 bellard
}
1914 c896fe29 bellard
1915 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
1916 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
1917 f8422f52 blueswir1
1918 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
1919 f8422f52 blueswir1
1920 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
1921 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
1922 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
1923 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
1924 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1925 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1926 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1927 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1928 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1929 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1930 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
1931 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
1932 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
1933 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
1934 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
1935 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
1936 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
1937 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
1938 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
1939 10460c8a pbrook
#define tcg_gen_subfi_tl tcg_gen_subfi_i64
1940 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
1941 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
1942 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
1943 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
1944 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
1945 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
1946 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
1947 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i64
1948 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
1949 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
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#define tcg_gen_shr_tl tcg_gen_shr_i64
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#define tcg_gen_shri_tl tcg_gen_shri_i64
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#define tcg_gen_sar_tl tcg_gen_sar_i64
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#define tcg_gen_sari_tl tcg_gen_sari_i64
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#define tcg_gen_brcond_tl tcg_gen_brcond_i64
1955 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
1956 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
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#define tcg_gen_muli_tl tcg_gen_muli_i64
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#define tcg_gen_discard_tl tcg_gen_discard_i64
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#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
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#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
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#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
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#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
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#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
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#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
1965 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
1966 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
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#define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
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#define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
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#define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
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#define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
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#define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
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#define tcg_gen_andc_tl tcg_gen_andc_i64
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#define tcg_gen_eqv_tl tcg_gen_eqv_i64
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#define tcg_gen_nand_tl tcg_gen_nand_i64
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#define tcg_gen_nor_tl tcg_gen_nor_i64
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#define tcg_gen_orc_tl tcg_gen_orc_i64
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#define tcg_gen_rotl_tl tcg_gen_rotl_i64
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#define tcg_gen_rotli_tl tcg_gen_rotli_i64
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#define tcg_gen_rotr_tl tcg_gen_rotr_i64
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#define tcg_gen_rotri_tl tcg_gen_rotri_i64
1981 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
1982 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i64
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#else
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#define TCG_TYPE_TL TCG_TYPE_I32
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#define tcg_gen_movi_tl tcg_gen_movi_i32
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#define tcg_gen_mov_tl tcg_gen_mov_i32
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#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
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#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
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#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
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#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
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#define tcg_gen_ld32u_tl tcg_gen_ld_i32
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#define tcg_gen_ld32s_tl tcg_gen_ld_i32
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#define tcg_gen_ld_tl tcg_gen_ld_i32
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#define tcg_gen_st8_tl tcg_gen_st8_i32
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#define tcg_gen_st16_tl tcg_gen_st16_i32
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#define tcg_gen_st32_tl tcg_gen_st_i32
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#define tcg_gen_st_tl tcg_gen_st_i32
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#define tcg_gen_add_tl tcg_gen_add_i32
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#define tcg_gen_addi_tl tcg_gen_addi_i32
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#define tcg_gen_sub_tl tcg_gen_sub_i32
2001 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
2002 0045734a aurel32
#define tcg_gen_subfi_tl tcg_gen_subfi_i32
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#define tcg_gen_subi_tl tcg_gen_subi_i32
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#define tcg_gen_and_tl tcg_gen_and_i32
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#define tcg_gen_andi_tl tcg_gen_andi_i32
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#define tcg_gen_or_tl tcg_gen_or_i32
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#define tcg_gen_ori_tl tcg_gen_ori_i32
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#define tcg_gen_xor_tl tcg_gen_xor_i32
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#define tcg_gen_xori_tl tcg_gen_xori_i32
2010 0b6ce4cf bellard
#define tcg_gen_not_tl tcg_gen_not_i32
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#define tcg_gen_shl_tl tcg_gen_shl_i32
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#define tcg_gen_shli_tl tcg_gen_shli_i32
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#define tcg_gen_shr_tl tcg_gen_shr_i32
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#define tcg_gen_shri_tl tcg_gen_shri_i32
2015 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
2016 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
2017 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
2018 cb63669a pbrook
#define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
2019 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
2020 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
2021 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
2022 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
2023 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
2024 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
2025 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
2026 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
2027 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
2028 0b6ce4cf bellard
#define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
2029 0b6ce4cf bellard
#define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
2030 0b6ce4cf bellard
#define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
2031 0b6ce4cf bellard
#define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
2032 0b6ce4cf bellard
#define tcg_gen_ext32u_tl tcg_gen_mov_i32
2033 0b6ce4cf bellard
#define tcg_gen_ext32s_tl tcg_gen_mov_i32
2034 945ca823 blueswir1
#define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
2035 f24cb33e aurel32
#define tcg_gen_andc_tl tcg_gen_andc_i32
2036 f24cb33e aurel32
#define tcg_gen_eqv_tl tcg_gen_eqv_i32
2037 f24cb33e aurel32
#define tcg_gen_nand_tl tcg_gen_nand_i32
2038 f24cb33e aurel32
#define tcg_gen_nor_tl tcg_gen_nor_i32
2039 f24cb33e aurel32
#define tcg_gen_orc_tl tcg_gen_orc_i32
2040 15824571 aurel32
#define tcg_gen_rotl_tl tcg_gen_rotl_i32
2041 15824571 aurel32
#define tcg_gen_rotli_tl tcg_gen_rotli_i32
2042 15824571 aurel32
#define tcg_gen_rotr_tl tcg_gen_rotr_i32
2043 15824571 aurel32
#define tcg_gen_rotri_tl tcg_gen_rotri_i32
2044 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
2045 bdffd4a9 aurel32
#define tcg_const_local_tl tcg_const_local_i32
2046 f8422f52 blueswir1
#endif
2047 6ddbc6e4 pbrook
2048 6ddbc6e4 pbrook
#if TCG_TARGET_REG_BITS == 32
2049 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i32
2050 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i32
2051 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_mov_i32
2052 6ddbc6e4 pbrook
#else /* TCG_TARGET_REG_BITS == 32 */
2053 48d38ca5 ths
#define tcg_gen_add_ptr tcg_gen_add_i64
2054 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i64
2055 48d38ca5 ths
#define tcg_gen_ext_i32_ptr tcg_gen_ext_i32_i64
2056 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */