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1 | 574bbf7b | bellard | /*
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2 | 574bbf7b | bellard | * APIC support
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3 | 5fafdf24 | ths | *
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4 | 574bbf7b | bellard | * Copyright (c) 2004-2005 Fabrice Bellard
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5 | 574bbf7b | bellard | *
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6 | 574bbf7b | bellard | * This library is free software; you can redistribute it and/or
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7 | 574bbf7b | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | 574bbf7b | bellard | * License as published by the Free Software Foundation; either
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9 | 574bbf7b | bellard | * version 2 of the License, or (at your option) any later version.
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10 | 574bbf7b | bellard | *
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11 | 574bbf7b | bellard | * This library is distributed in the hope that it will be useful,
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12 | 574bbf7b | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 574bbf7b | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 574bbf7b | bellard | * Lesser General Public License for more details.
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15 | 574bbf7b | bellard | *
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16 | 574bbf7b | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 574bbf7b | bellard | * License along with this library; if not, write to the Free Software
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18 | 574bbf7b | bellard | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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19 | 574bbf7b | bellard | */
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20 | 87ecb68b | pbrook | #include "hw.h" |
21 | 87ecb68b | pbrook | #include "pc.h" |
22 | 87ecb68b | pbrook | #include "qemu-timer.h" |
23 | bb7e7293 | aurel32 | #include "host-utils.h" |
24 | 574bbf7b | bellard | |
25 | 574bbf7b | bellard | //#define DEBUG_APIC
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26 | d592d303 | bellard | //#define DEBUG_IOAPIC
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27 | 574bbf7b | bellard | |
28 | 574bbf7b | bellard | /* APIC Local Vector Table */
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29 | 574bbf7b | bellard | #define APIC_LVT_TIMER 0 |
30 | 574bbf7b | bellard | #define APIC_LVT_THERMAL 1 |
31 | 574bbf7b | bellard | #define APIC_LVT_PERFORM 2 |
32 | 574bbf7b | bellard | #define APIC_LVT_LINT0 3 |
33 | 574bbf7b | bellard | #define APIC_LVT_LINT1 4 |
34 | 574bbf7b | bellard | #define APIC_LVT_ERROR 5 |
35 | 574bbf7b | bellard | #define APIC_LVT_NB 6 |
36 | 574bbf7b | bellard | |
37 | 574bbf7b | bellard | /* APIC delivery modes */
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38 | 574bbf7b | bellard | #define APIC_DM_FIXED 0 |
39 | 574bbf7b | bellard | #define APIC_DM_LOWPRI 1 |
40 | 574bbf7b | bellard | #define APIC_DM_SMI 2 |
41 | 574bbf7b | bellard | #define APIC_DM_NMI 4 |
42 | 574bbf7b | bellard | #define APIC_DM_INIT 5 |
43 | 574bbf7b | bellard | #define APIC_DM_SIPI 6 |
44 | 574bbf7b | bellard | #define APIC_DM_EXTINT 7 |
45 | 574bbf7b | bellard | |
46 | d592d303 | bellard | /* APIC destination mode */
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47 | d592d303 | bellard | #define APIC_DESTMODE_FLAT 0xf |
48 | d592d303 | bellard | #define APIC_DESTMODE_CLUSTER 1 |
49 | d592d303 | bellard | |
50 | 574bbf7b | bellard | #define APIC_TRIGGER_EDGE 0 |
51 | 574bbf7b | bellard | #define APIC_TRIGGER_LEVEL 1 |
52 | 574bbf7b | bellard | |
53 | 574bbf7b | bellard | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
54 | 574bbf7b | bellard | #define APIC_LVT_MASKED (1<<16) |
55 | 574bbf7b | bellard | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
56 | 574bbf7b | bellard | #define APIC_LVT_REMOTE_IRR (1<<14) |
57 | 574bbf7b | bellard | #define APIC_INPUT_POLARITY (1<<13) |
58 | 574bbf7b | bellard | #define APIC_SEND_PENDING (1<<12) |
59 | 574bbf7b | bellard | |
60 | d592d303 | bellard | #define IOAPIC_NUM_PINS 0x18 |
61 | d592d303 | bellard | |
62 | 574bbf7b | bellard | #define ESR_ILLEGAL_ADDRESS (1 << 7) |
63 | 574bbf7b | bellard | |
64 | 574bbf7b | bellard | #define APIC_SV_ENABLE (1 << 8) |
65 | 574bbf7b | bellard | |
66 | d3e9db93 | bellard | #define MAX_APICS 255 |
67 | d3e9db93 | bellard | #define MAX_APIC_WORDS 8 |
68 | d3e9db93 | bellard | |
69 | 574bbf7b | bellard | typedef struct APICState { |
70 | 574bbf7b | bellard | CPUState *cpu_env; |
71 | 574bbf7b | bellard | uint32_t apicbase; |
72 | 574bbf7b | bellard | uint8_t id; |
73 | d592d303 | bellard | uint8_t arb_id; |
74 | 574bbf7b | bellard | uint8_t tpr; |
75 | 574bbf7b | bellard | uint32_t spurious_vec; |
76 | d592d303 | bellard | uint8_t log_dest; |
77 | d592d303 | bellard | uint8_t dest_mode; |
78 | 574bbf7b | bellard | uint32_t isr[8]; /* in service register */ |
79 | 574bbf7b | bellard | uint32_t tmr[8]; /* trigger mode register */ |
80 | 574bbf7b | bellard | uint32_t irr[8]; /* interrupt request register */ |
81 | 574bbf7b | bellard | uint32_t lvt[APIC_LVT_NB]; |
82 | 574bbf7b | bellard | uint32_t esr; /* error register */
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83 | 574bbf7b | bellard | uint32_t icr[2];
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84 | 574bbf7b | bellard | |
85 | 574bbf7b | bellard | uint32_t divide_conf; |
86 | 574bbf7b | bellard | int count_shift;
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87 | 574bbf7b | bellard | uint32_t initial_count; |
88 | 574bbf7b | bellard | int64_t initial_count_load_time, next_time; |
89 | 574bbf7b | bellard | QEMUTimer *timer; |
90 | 574bbf7b | bellard | } APICState; |
91 | 574bbf7b | bellard | |
92 | d592d303 | bellard | struct IOAPICState {
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93 | d592d303 | bellard | uint8_t id; |
94 | d592d303 | bellard | uint8_t ioregsel; |
95 | d592d303 | bellard | |
96 | d592d303 | bellard | uint32_t irr; |
97 | d592d303 | bellard | uint64_t ioredtbl[IOAPIC_NUM_PINS]; |
98 | d592d303 | bellard | }; |
99 | d592d303 | bellard | |
100 | 574bbf7b | bellard | static int apic_io_memory; |
101 | d3e9db93 | bellard | static APICState *local_apics[MAX_APICS + 1]; |
102 | d592d303 | bellard | static int last_apic_id = 0; |
103 | d592d303 | bellard | |
104 | d592d303 | bellard | static void apic_init_ipi(APICState *s); |
105 | d592d303 | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode); |
106 | d592d303 | bellard | static void apic_update_irq(APICState *s); |
107 | d592d303 | bellard | |
108 | e95f5491 | aurel32 | /* Find first bit starting from msb */
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109 | d3e9db93 | bellard | static int fls_bit(uint32_t value) |
110 | d3e9db93 | bellard | { |
111 | bb7e7293 | aurel32 | return 31 - clz32(value); |
112 | d3e9db93 | bellard | } |
113 | d3e9db93 | bellard | |
114 | e95f5491 | aurel32 | /* Find first bit starting from lsb */
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115 | d3e9db93 | bellard | static int ffs_bit(uint32_t value) |
116 | d3e9db93 | bellard | { |
117 | bb7e7293 | aurel32 | return ctz32(value);
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118 | d3e9db93 | bellard | } |
119 | d3e9db93 | bellard | |
120 | d3e9db93 | bellard | static inline void set_bit(uint32_t *tab, int index) |
121 | d3e9db93 | bellard | { |
122 | d3e9db93 | bellard | int i, mask;
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123 | d3e9db93 | bellard | i = index >> 5;
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124 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
125 | d3e9db93 | bellard | tab[i] |= mask; |
126 | d3e9db93 | bellard | } |
127 | d3e9db93 | bellard | |
128 | d3e9db93 | bellard | static inline void reset_bit(uint32_t *tab, int index) |
129 | d3e9db93 | bellard | { |
130 | d3e9db93 | bellard | int i, mask;
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131 | d3e9db93 | bellard | i = index >> 5;
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132 | d3e9db93 | bellard | mask = 1 << (index & 0x1f); |
133 | d3e9db93 | bellard | tab[i] &= ~mask; |
134 | d3e9db93 | bellard | } |
135 | d3e9db93 | bellard | |
136 | 1a7de94a | aurel32 | static void apic_local_deliver(CPUState *env, int vector) |
137 | a5b38b51 | aurel32 | { |
138 | a5b38b51 | aurel32 | APICState *s = env->apic_state; |
139 | a5b38b51 | aurel32 | uint32_t lvt = s->lvt[vector]; |
140 | a5b38b51 | aurel32 | int trigger_mode;
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141 | a5b38b51 | aurel32 | |
142 | a5b38b51 | aurel32 | if (lvt & APIC_LVT_MASKED)
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143 | a5b38b51 | aurel32 | return;
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144 | a5b38b51 | aurel32 | |
145 | a5b38b51 | aurel32 | switch ((lvt >> 8) & 7) { |
146 | a5b38b51 | aurel32 | case APIC_DM_SMI:
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147 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_SMI); |
148 | a5b38b51 | aurel32 | break;
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149 | a5b38b51 | aurel32 | |
150 | a5b38b51 | aurel32 | case APIC_DM_NMI:
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151 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_NMI); |
152 | a5b38b51 | aurel32 | break;
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153 | a5b38b51 | aurel32 | |
154 | a5b38b51 | aurel32 | case APIC_DM_EXTINT:
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155 | a5b38b51 | aurel32 | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
156 | a5b38b51 | aurel32 | break;
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157 | a5b38b51 | aurel32 | |
158 | a5b38b51 | aurel32 | case APIC_DM_FIXED:
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159 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_EDGE; |
160 | a5b38b51 | aurel32 | if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
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161 | a5b38b51 | aurel32 | (lvt & APIC_LVT_LEVEL_TRIGGER)) |
162 | a5b38b51 | aurel32 | trigger_mode = APIC_TRIGGER_LEVEL; |
163 | a5b38b51 | aurel32 | apic_set_irq(s, lvt & 0xff, trigger_mode);
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164 | a5b38b51 | aurel32 | } |
165 | a5b38b51 | aurel32 | } |
166 | a5b38b51 | aurel32 | |
167 | 1a7de94a | aurel32 | void apic_deliver_pic_intr(CPUState *env, int level) |
168 | 1a7de94a | aurel32 | { |
169 | 1a7de94a | aurel32 | if (level)
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170 | 1a7de94a | aurel32 | apic_local_deliver(env, APIC_LVT_LINT0); |
171 | 1a7de94a | aurel32 | else {
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172 | 1a7de94a | aurel32 | APICState *s = env->apic_state; |
173 | 1a7de94a | aurel32 | uint32_t lvt = s->lvt[APIC_LVT_LINT0]; |
174 | 1a7de94a | aurel32 | |
175 | 1a7de94a | aurel32 | switch ((lvt >> 8) & 7) { |
176 | 1a7de94a | aurel32 | case APIC_DM_FIXED:
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177 | 1a7de94a | aurel32 | if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
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178 | 1a7de94a | aurel32 | break;
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179 | 1a7de94a | aurel32 | reset_bit(s->irr, lvt & 0xff);
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180 | 1a7de94a | aurel32 | /* fall through */
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181 | 1a7de94a | aurel32 | case APIC_DM_EXTINT:
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182 | 1a7de94a | aurel32 | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
183 | 1a7de94a | aurel32 | break;
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184 | 1a7de94a | aurel32 | } |
185 | 1a7de94a | aurel32 | } |
186 | 1a7de94a | aurel32 | } |
187 | 1a7de94a | aurel32 | |
188 | d3e9db93 | bellard | #define foreach_apic(apic, deliver_bitmask, code) \
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189 | d3e9db93 | bellard | {\ |
190 | d3e9db93 | bellard | int __i, __j, __mask;\
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191 | d3e9db93 | bellard | for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ |
192 | d3e9db93 | bellard | __mask = deliver_bitmask[__i];\ |
193 | d3e9db93 | bellard | if (__mask) {\
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194 | d3e9db93 | bellard | for(__j = 0; __j < 32; __j++) {\ |
195 | d3e9db93 | bellard | if (__mask & (1 << __j)) {\ |
196 | d3e9db93 | bellard | apic = local_apics[__i * 32 + __j];\
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197 | d3e9db93 | bellard | if (apic) {\
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198 | d3e9db93 | bellard | code;\ |
199 | d3e9db93 | bellard | }\ |
200 | d3e9db93 | bellard | }\ |
201 | d3e9db93 | bellard | }\ |
202 | d3e9db93 | bellard | }\ |
203 | d3e9db93 | bellard | }\ |
204 | d3e9db93 | bellard | } |
205 | d3e9db93 | bellard | |
206 | 5fafdf24 | ths | static void apic_bus_deliver(const uint32_t *deliver_bitmask, |
207 | d3e9db93 | bellard | uint8_t delivery_mode, |
208 | d592d303 | bellard | uint8_t vector_num, uint8_t polarity, |
209 | d592d303 | bellard | uint8_t trigger_mode) |
210 | d592d303 | bellard | { |
211 | d592d303 | bellard | APICState *apic_iter; |
212 | d592d303 | bellard | |
213 | d592d303 | bellard | switch (delivery_mode) {
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214 | d592d303 | bellard | case APIC_DM_LOWPRI:
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215 | 8dd69b8f | bellard | /* XXX: search for focus processor, arbitration */
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216 | d3e9db93 | bellard | { |
217 | d3e9db93 | bellard | int i, d;
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218 | d3e9db93 | bellard | d = -1;
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219 | d3e9db93 | bellard | for(i = 0; i < MAX_APIC_WORDS; i++) { |
220 | d3e9db93 | bellard | if (deliver_bitmask[i]) {
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221 | d3e9db93 | bellard | d = i * 32 + ffs_bit(deliver_bitmask[i]);
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222 | d3e9db93 | bellard | break;
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223 | d3e9db93 | bellard | } |
224 | d3e9db93 | bellard | } |
225 | d3e9db93 | bellard | if (d >= 0) { |
226 | d3e9db93 | bellard | apic_iter = local_apics[d]; |
227 | d3e9db93 | bellard | if (apic_iter) {
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228 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode); |
229 | d3e9db93 | bellard | } |
230 | d3e9db93 | bellard | } |
231 | 8dd69b8f | bellard | } |
232 | d3e9db93 | bellard | return;
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233 | 8dd69b8f | bellard | |
234 | d592d303 | bellard | case APIC_DM_FIXED:
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235 | d592d303 | bellard | break;
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236 | d592d303 | bellard | |
237 | d592d303 | bellard | case APIC_DM_SMI:
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238 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
239 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); |
240 | e2eb9d3e | aurel32 | return;
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241 | e2eb9d3e | aurel32 | |
242 | d592d303 | bellard | case APIC_DM_NMI:
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243 | e2eb9d3e | aurel32 | foreach_apic(apic_iter, deliver_bitmask, |
244 | e2eb9d3e | aurel32 | cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); |
245 | e2eb9d3e | aurel32 | return;
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246 | d592d303 | bellard | |
247 | d592d303 | bellard | case APIC_DM_INIT:
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248 | d592d303 | bellard | /* normal INIT IPI sent to processors */
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249 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
250 | d3e9db93 | bellard | apic_init_ipi(apic_iter) ); |
251 | d592d303 | bellard | return;
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252 | 3b46e624 | ths | |
253 | d592d303 | bellard | case APIC_DM_EXTINT:
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254 | b1fc0348 | bellard | /* handled in I/O APIC code */
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255 | d592d303 | bellard | break;
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256 | d592d303 | bellard | |
257 | d592d303 | bellard | default:
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258 | d592d303 | bellard | return;
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259 | d592d303 | bellard | } |
260 | d592d303 | bellard | |
261 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
262 | d3e9db93 | bellard | apic_set_irq(apic_iter, vector_num, trigger_mode) ); |
263 | d592d303 | bellard | } |
264 | 574bbf7b | bellard | |
265 | 574bbf7b | bellard | void cpu_set_apic_base(CPUState *env, uint64_t val)
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266 | 574bbf7b | bellard | { |
267 | 574bbf7b | bellard | APICState *s = env->apic_state; |
268 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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269 | 26a76461 | bellard | printf("cpu_set_apic_base: %016" PRIx64 "\n", val); |
270 | 574bbf7b | bellard | #endif
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271 | 5fafdf24 | ths | s->apicbase = (val & 0xfffff000) |
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272 | 574bbf7b | bellard | (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE)); |
273 | 574bbf7b | bellard | /* if disabled, cannot be enabled again */
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274 | 574bbf7b | bellard | if (!(val & MSR_IA32_APICBASE_ENABLE)) {
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275 | 574bbf7b | bellard | s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; |
276 | 574bbf7b | bellard | env->cpuid_features &= ~CPUID_APIC; |
277 | 574bbf7b | bellard | s->spurious_vec &= ~APIC_SV_ENABLE; |
278 | 574bbf7b | bellard | } |
279 | 574bbf7b | bellard | } |
280 | 574bbf7b | bellard | |
281 | 574bbf7b | bellard | uint64_t cpu_get_apic_base(CPUState *env) |
282 | 574bbf7b | bellard | { |
283 | 574bbf7b | bellard | APICState *s = env->apic_state; |
284 | 574bbf7b | bellard | #ifdef DEBUG_APIC
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285 | 26a76461 | bellard | printf("cpu_get_apic_base: %016" PRIx64 "\n", (uint64_t)s->apicbase); |
286 | 574bbf7b | bellard | #endif
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287 | 574bbf7b | bellard | return s->apicbase;
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288 | 574bbf7b | bellard | } |
289 | 574bbf7b | bellard | |
290 | 9230e66e | bellard | void cpu_set_apic_tpr(CPUX86State *env, uint8_t val)
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291 | 9230e66e | bellard | { |
292 | 9230e66e | bellard | APICState *s = env->apic_state; |
293 | 9230e66e | bellard | s->tpr = (val & 0x0f) << 4; |
294 | d592d303 | bellard | apic_update_irq(s); |
295 | 9230e66e | bellard | } |
296 | 9230e66e | bellard | |
297 | 9230e66e | bellard | uint8_t cpu_get_apic_tpr(CPUX86State *env) |
298 | 9230e66e | bellard | { |
299 | 9230e66e | bellard | APICState *s = env->apic_state; |
300 | 9230e66e | bellard | return s->tpr >> 4; |
301 | 9230e66e | bellard | } |
302 | 9230e66e | bellard | |
303 | d592d303 | bellard | /* return -1 if no bit is set */
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304 | d592d303 | bellard | static int get_highest_priority_int(uint32_t *tab) |
305 | d592d303 | bellard | { |
306 | d592d303 | bellard | int i;
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307 | d592d303 | bellard | for(i = 7; i >= 0; i--) { |
308 | d592d303 | bellard | if (tab[i] != 0) { |
309 | d592d303 | bellard | return i * 32 + fls_bit(tab[i]); |
310 | d592d303 | bellard | } |
311 | d592d303 | bellard | } |
312 | d592d303 | bellard | return -1; |
313 | d592d303 | bellard | } |
314 | d592d303 | bellard | |
315 | 574bbf7b | bellard | static int apic_get_ppr(APICState *s) |
316 | 574bbf7b | bellard | { |
317 | 574bbf7b | bellard | int tpr, isrv, ppr;
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318 | 574bbf7b | bellard | |
319 | 574bbf7b | bellard | tpr = (s->tpr >> 4);
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320 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
321 | 574bbf7b | bellard | if (isrv < 0) |
322 | 574bbf7b | bellard | isrv = 0;
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323 | 574bbf7b | bellard | isrv >>= 4;
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324 | 574bbf7b | bellard | if (tpr >= isrv)
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325 | 574bbf7b | bellard | ppr = s->tpr; |
326 | 574bbf7b | bellard | else
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327 | 574bbf7b | bellard | ppr = isrv << 4;
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328 | 574bbf7b | bellard | return ppr;
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329 | 574bbf7b | bellard | } |
330 | 574bbf7b | bellard | |
331 | d592d303 | bellard | static int apic_get_arb_pri(APICState *s) |
332 | d592d303 | bellard | { |
333 | d592d303 | bellard | /* XXX: arbitration */
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334 | d592d303 | bellard | return 0; |
335 | d592d303 | bellard | } |
336 | d592d303 | bellard | |
337 | 574bbf7b | bellard | /* signal the CPU if an irq is pending */
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338 | 574bbf7b | bellard | static void apic_update_irq(APICState *s) |
339 | 574bbf7b | bellard | { |
340 | d592d303 | bellard | int irrv, ppr;
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341 | d592d303 | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
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342 | d592d303 | bellard | return;
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343 | 574bbf7b | bellard | irrv = get_highest_priority_int(s->irr); |
344 | 574bbf7b | bellard | if (irrv < 0) |
345 | 574bbf7b | bellard | return;
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346 | d592d303 | bellard | ppr = apic_get_ppr(s); |
347 | d592d303 | bellard | if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) |
348 | 574bbf7b | bellard | return;
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349 | 574bbf7b | bellard | cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); |
350 | 574bbf7b | bellard | } |
351 | 574bbf7b | bellard | |
352 | 574bbf7b | bellard | static void apic_set_irq(APICState *s, int vector_num, int trigger_mode) |
353 | 574bbf7b | bellard | { |
354 | 574bbf7b | bellard | set_bit(s->irr, vector_num); |
355 | 574bbf7b | bellard | if (trigger_mode)
|
356 | 574bbf7b | bellard | set_bit(s->tmr, vector_num); |
357 | 574bbf7b | bellard | else
|
358 | 574bbf7b | bellard | reset_bit(s->tmr, vector_num); |
359 | 574bbf7b | bellard | apic_update_irq(s); |
360 | 574bbf7b | bellard | } |
361 | 574bbf7b | bellard | |
362 | 574bbf7b | bellard | static void apic_eoi(APICState *s) |
363 | 574bbf7b | bellard | { |
364 | 574bbf7b | bellard | int isrv;
|
365 | 574bbf7b | bellard | isrv = get_highest_priority_int(s->isr); |
366 | 574bbf7b | bellard | if (isrv < 0) |
367 | 574bbf7b | bellard | return;
|
368 | 574bbf7b | bellard | reset_bit(s->isr, isrv); |
369 | d592d303 | bellard | /* XXX: send the EOI packet to the APIC bus to allow the I/O APIC to
|
370 | d592d303 | bellard | set the remote IRR bit for level triggered interrupts. */
|
371 | 574bbf7b | bellard | apic_update_irq(s); |
372 | 574bbf7b | bellard | } |
373 | 574bbf7b | bellard | |
374 | d3e9db93 | bellard | static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, |
375 | d3e9db93 | bellard | uint8_t dest, uint8_t dest_mode) |
376 | d592d303 | bellard | { |
377 | d592d303 | bellard | APICState *apic_iter; |
378 | d3e9db93 | bellard | int i;
|
379 | d592d303 | bellard | |
380 | d592d303 | bellard | if (dest_mode == 0) { |
381 | d3e9db93 | bellard | if (dest == 0xff) { |
382 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t)); |
383 | d3e9db93 | bellard | } else {
|
384 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
385 | d3e9db93 | bellard | set_bit(deliver_bitmask, dest); |
386 | d3e9db93 | bellard | } |
387 | d592d303 | bellard | } else {
|
388 | d592d303 | bellard | /* XXX: cluster mode */
|
389 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t)); |
390 | d3e9db93 | bellard | for(i = 0; i < MAX_APICS; i++) { |
391 | d3e9db93 | bellard | apic_iter = local_apics[i]; |
392 | d3e9db93 | bellard | if (apic_iter) {
|
393 | d3e9db93 | bellard | if (apic_iter->dest_mode == 0xf) { |
394 | d3e9db93 | bellard | if (dest & apic_iter->log_dest)
|
395 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
396 | d3e9db93 | bellard | } else if (apic_iter->dest_mode == 0x0) { |
397 | d3e9db93 | bellard | if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) && |
398 | d3e9db93 | bellard | (dest & apic_iter->log_dest & 0x0f)) {
|
399 | d3e9db93 | bellard | set_bit(deliver_bitmask, i); |
400 | d3e9db93 | bellard | } |
401 | d3e9db93 | bellard | } |
402 | d3e9db93 | bellard | } |
403 | d592d303 | bellard | } |
404 | d592d303 | bellard | } |
405 | d592d303 | bellard | } |
406 | d592d303 | bellard | |
407 | d592d303 | bellard | |
408 | d592d303 | bellard | static void apic_init_ipi(APICState *s) |
409 | d592d303 | bellard | { |
410 | d592d303 | bellard | int i;
|
411 | d592d303 | bellard | |
412 | d592d303 | bellard | s->tpr = 0;
|
413 | d592d303 | bellard | s->spurious_vec = 0xff;
|
414 | d592d303 | bellard | s->log_dest = 0;
|
415 | e0fd8781 | bellard | s->dest_mode = 0xf;
|
416 | d592d303 | bellard | memset(s->isr, 0, sizeof(s->isr)); |
417 | d592d303 | bellard | memset(s->tmr, 0, sizeof(s->tmr)); |
418 | d592d303 | bellard | memset(s->irr, 0, sizeof(s->irr)); |
419 | b4511723 | bellard | for(i = 0; i < APIC_LVT_NB; i++) |
420 | b4511723 | bellard | s->lvt[i] = 1 << 16; /* mask LVT */ |
421 | d592d303 | bellard | s->esr = 0;
|
422 | d592d303 | bellard | memset(s->icr, 0, sizeof(s->icr)); |
423 | d592d303 | bellard | s->divide_conf = 0;
|
424 | d592d303 | bellard | s->count_shift = 0;
|
425 | d592d303 | bellard | s->initial_count = 0;
|
426 | d592d303 | bellard | s->initial_count_load_time = 0;
|
427 | d592d303 | bellard | s->next_time = 0;
|
428 | 3003b8bb | aurel32 | |
429 | 3003b8bb | aurel32 | cpu_reset(s->cpu_env); |
430 | 3003b8bb | aurel32 | |
431 | 3003b8bb | aurel32 | if (!(s->apicbase & MSR_IA32_APICBASE_BSP))
|
432 | 3003b8bb | aurel32 | s->cpu_env->halted = 1;
|
433 | d592d303 | bellard | } |
434 | d592d303 | bellard | |
435 | e0fd8781 | bellard | /* send a SIPI message to the CPU to start it */
|
436 | e0fd8781 | bellard | static void apic_startup(APICState *s, int vector_num) |
437 | e0fd8781 | bellard | { |
438 | e0fd8781 | bellard | CPUState *env = s->cpu_env; |
439 | ce5232c5 | bellard | if (!env->halted)
|
440 | e0fd8781 | bellard | return;
|
441 | e0fd8781 | bellard | env->eip = 0;
|
442 | 5fafdf24 | ths | cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12, |
443 | e0fd8781 | bellard | 0xffff, 0); |
444 | ce5232c5 | bellard | env->halted = 0;
|
445 | e0fd8781 | bellard | } |
446 | e0fd8781 | bellard | |
447 | d592d303 | bellard | static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode, |
448 | d592d303 | bellard | uint8_t delivery_mode, uint8_t vector_num, |
449 | d592d303 | bellard | uint8_t polarity, uint8_t trigger_mode) |
450 | d592d303 | bellard | { |
451 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
452 | d592d303 | bellard | int dest_shorthand = (s->icr[0] >> 18) & 3; |
453 | d592d303 | bellard | APICState *apic_iter; |
454 | d592d303 | bellard | |
455 | e0fd8781 | bellard | switch (dest_shorthand) {
|
456 | d3e9db93 | bellard | case 0: |
457 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
458 | d3e9db93 | bellard | break;
|
459 | d3e9db93 | bellard | case 1: |
460 | d3e9db93 | bellard | memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask)); |
461 | d3e9db93 | bellard | set_bit(deliver_bitmask, s->id); |
462 | d3e9db93 | bellard | break;
|
463 | d3e9db93 | bellard | case 2: |
464 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
465 | d3e9db93 | bellard | break;
|
466 | d3e9db93 | bellard | case 3: |
467 | d3e9db93 | bellard | memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask)); |
468 | d3e9db93 | bellard | reset_bit(deliver_bitmask, s->id); |
469 | d3e9db93 | bellard | break;
|
470 | e0fd8781 | bellard | } |
471 | e0fd8781 | bellard | |
472 | d592d303 | bellard | switch (delivery_mode) {
|
473 | d592d303 | bellard | case APIC_DM_INIT:
|
474 | d592d303 | bellard | { |
475 | d592d303 | bellard | int trig_mode = (s->icr[0] >> 15) & 1; |
476 | d592d303 | bellard | int level = (s->icr[0] >> 14) & 1; |
477 | d592d303 | bellard | if (level == 0 && trig_mode == 1) { |
478 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
479 | d3e9db93 | bellard | apic_iter->arb_id = apic_iter->id ); |
480 | d592d303 | bellard | return;
|
481 | d592d303 | bellard | } |
482 | d592d303 | bellard | } |
483 | d592d303 | bellard | break;
|
484 | d592d303 | bellard | |
485 | d592d303 | bellard | case APIC_DM_SIPI:
|
486 | 5fafdf24 | ths | foreach_apic(apic_iter, deliver_bitmask, |
487 | d3e9db93 | bellard | apic_startup(apic_iter, vector_num) ); |
488 | d592d303 | bellard | return;
|
489 | d592d303 | bellard | } |
490 | d592d303 | bellard | |
491 | d592d303 | bellard | apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity, |
492 | d592d303 | bellard | trigger_mode); |
493 | d592d303 | bellard | } |
494 | d592d303 | bellard | |
495 | 574bbf7b | bellard | int apic_get_interrupt(CPUState *env)
|
496 | 574bbf7b | bellard | { |
497 | 574bbf7b | bellard | APICState *s = env->apic_state; |
498 | 574bbf7b | bellard | int intno;
|
499 | 574bbf7b | bellard | |
500 | 574bbf7b | bellard | /* if the APIC is installed or enabled, we let the 8259 handle the
|
501 | 574bbf7b | bellard | IRQs */
|
502 | 574bbf7b | bellard | if (!s)
|
503 | 574bbf7b | bellard | return -1; |
504 | 574bbf7b | bellard | if (!(s->spurious_vec & APIC_SV_ENABLE))
|
505 | 574bbf7b | bellard | return -1; |
506 | 3b46e624 | ths | |
507 | 574bbf7b | bellard | /* XXX: spurious IRQ handling */
|
508 | 574bbf7b | bellard | intno = get_highest_priority_int(s->irr); |
509 | 574bbf7b | bellard | if (intno < 0) |
510 | 574bbf7b | bellard | return -1; |
511 | d592d303 | bellard | if (s->tpr && intno <= s->tpr)
|
512 | d592d303 | bellard | return s->spurious_vec & 0xff; |
513 | b4511723 | bellard | reset_bit(s->irr, intno); |
514 | 574bbf7b | bellard | set_bit(s->isr, intno); |
515 | 574bbf7b | bellard | apic_update_irq(s); |
516 | 574bbf7b | bellard | return intno;
|
517 | 574bbf7b | bellard | } |
518 | 574bbf7b | bellard | |
519 | 0e21e12b | ths | int apic_accept_pic_intr(CPUState *env)
|
520 | 0e21e12b | ths | { |
521 | 0e21e12b | ths | APICState *s = env->apic_state; |
522 | 0e21e12b | ths | uint32_t lvt0; |
523 | 0e21e12b | ths | |
524 | 0e21e12b | ths | if (!s)
|
525 | 0e21e12b | ths | return -1; |
526 | 0e21e12b | ths | |
527 | 0e21e12b | ths | lvt0 = s->lvt[APIC_LVT_LINT0]; |
528 | 0e21e12b | ths | |
529 | a5b38b51 | aurel32 | if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 || |
530 | a5b38b51 | aurel32 | (lvt0 & APIC_LVT_MASKED) == 0)
|
531 | 0e21e12b | ths | return 1; |
532 | 0e21e12b | ths | |
533 | 0e21e12b | ths | return 0; |
534 | 0e21e12b | ths | } |
535 | 0e21e12b | ths | |
536 | 574bbf7b | bellard | static uint32_t apic_get_current_count(APICState *s)
|
537 | 574bbf7b | bellard | { |
538 | 574bbf7b | bellard | int64_t d; |
539 | 574bbf7b | bellard | uint32_t val; |
540 | 5fafdf24 | ths | d = (qemu_get_clock(vm_clock) - s->initial_count_load_time) >> |
541 | 574bbf7b | bellard | s->count_shift; |
542 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
543 | 574bbf7b | bellard | /* periodic */
|
544 | d592d303 | bellard | val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
|
545 | 574bbf7b | bellard | } else {
|
546 | 574bbf7b | bellard | if (d >= s->initial_count)
|
547 | 574bbf7b | bellard | val = 0;
|
548 | 574bbf7b | bellard | else
|
549 | 574bbf7b | bellard | val = s->initial_count - d; |
550 | 574bbf7b | bellard | } |
551 | 574bbf7b | bellard | return val;
|
552 | 574bbf7b | bellard | } |
553 | 574bbf7b | bellard | |
554 | 574bbf7b | bellard | static void apic_timer_update(APICState *s, int64_t current_time) |
555 | 574bbf7b | bellard | { |
556 | 574bbf7b | bellard | int64_t next_time, d; |
557 | 3b46e624 | ths | |
558 | 574bbf7b | bellard | if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
|
559 | 5fafdf24 | ths | d = (current_time - s->initial_count_load_time) >> |
560 | 574bbf7b | bellard | s->count_shift; |
561 | 574bbf7b | bellard | if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
|
562 | 681f8c29 | aliguori | if (!s->initial_count)
|
563 | 681f8c29 | aliguori | goto no_timer;
|
564 | d592d303 | bellard | d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1); |
565 | 574bbf7b | bellard | } else {
|
566 | 574bbf7b | bellard | if (d >= s->initial_count)
|
567 | 574bbf7b | bellard | goto no_timer;
|
568 | d592d303 | bellard | d = (uint64_t)s->initial_count + 1;
|
569 | 574bbf7b | bellard | } |
570 | 574bbf7b | bellard | next_time = s->initial_count_load_time + (d << s->count_shift); |
571 | 574bbf7b | bellard | qemu_mod_timer(s->timer, next_time); |
572 | 574bbf7b | bellard | s->next_time = next_time; |
573 | 574bbf7b | bellard | } else {
|
574 | 574bbf7b | bellard | no_timer:
|
575 | 574bbf7b | bellard | qemu_del_timer(s->timer); |
576 | 574bbf7b | bellard | } |
577 | 574bbf7b | bellard | } |
578 | 574bbf7b | bellard | |
579 | 574bbf7b | bellard | static void apic_timer(void *opaque) |
580 | 574bbf7b | bellard | { |
581 | 574bbf7b | bellard | APICState *s = opaque; |
582 | 574bbf7b | bellard | |
583 | a5b38b51 | aurel32 | apic_local_deliver(s->cpu_env, APIC_LVT_TIMER); |
584 | 574bbf7b | bellard | apic_timer_update(s, s->next_time); |
585 | 574bbf7b | bellard | } |
586 | 574bbf7b | bellard | |
587 | 574bbf7b | bellard | static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr) |
588 | 574bbf7b | bellard | { |
589 | 574bbf7b | bellard | return 0; |
590 | 574bbf7b | bellard | } |
591 | 574bbf7b | bellard | |
592 | 574bbf7b | bellard | static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr) |
593 | 574bbf7b | bellard | { |
594 | 574bbf7b | bellard | return 0; |
595 | 574bbf7b | bellard | } |
596 | 574bbf7b | bellard | |
597 | 574bbf7b | bellard | static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
598 | 574bbf7b | bellard | { |
599 | 574bbf7b | bellard | } |
600 | 574bbf7b | bellard | |
601 | 574bbf7b | bellard | static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
602 | 574bbf7b | bellard | { |
603 | 574bbf7b | bellard | } |
604 | 574bbf7b | bellard | |
605 | 574bbf7b | bellard | static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr) |
606 | 574bbf7b | bellard | { |
607 | 574bbf7b | bellard | CPUState *env; |
608 | 574bbf7b | bellard | APICState *s; |
609 | 574bbf7b | bellard | uint32_t val; |
610 | 574bbf7b | bellard | int index;
|
611 | 574bbf7b | bellard | |
612 | 574bbf7b | bellard | env = cpu_single_env; |
613 | 574bbf7b | bellard | if (!env)
|
614 | 574bbf7b | bellard | return 0; |
615 | 574bbf7b | bellard | s = env->apic_state; |
616 | 574bbf7b | bellard | |
617 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
618 | 574bbf7b | bellard | switch(index) {
|
619 | 574bbf7b | bellard | case 0x02: /* id */ |
620 | 574bbf7b | bellard | val = s->id << 24;
|
621 | 574bbf7b | bellard | break;
|
622 | 574bbf7b | bellard | case 0x03: /* version */ |
623 | 574bbf7b | bellard | val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */ |
624 | 574bbf7b | bellard | break;
|
625 | 574bbf7b | bellard | case 0x08: |
626 | 574bbf7b | bellard | val = s->tpr; |
627 | 574bbf7b | bellard | break;
|
628 | d592d303 | bellard | case 0x09: |
629 | d592d303 | bellard | val = apic_get_arb_pri(s); |
630 | d592d303 | bellard | break;
|
631 | 574bbf7b | bellard | case 0x0a: |
632 | 574bbf7b | bellard | /* ppr */
|
633 | 574bbf7b | bellard | val = apic_get_ppr(s); |
634 | 574bbf7b | bellard | break;
|
635 | b237db36 | aurel32 | case 0x0b: |
636 | b237db36 | aurel32 | val = 0;
|
637 | b237db36 | aurel32 | break;
|
638 | d592d303 | bellard | case 0x0d: |
639 | d592d303 | bellard | val = s->log_dest << 24;
|
640 | d592d303 | bellard | break;
|
641 | d592d303 | bellard | case 0x0e: |
642 | d592d303 | bellard | val = s->dest_mode << 28;
|
643 | d592d303 | bellard | break;
|
644 | 574bbf7b | bellard | case 0x0f: |
645 | 574bbf7b | bellard | val = s->spurious_vec; |
646 | 574bbf7b | bellard | break;
|
647 | 574bbf7b | bellard | case 0x10 ... 0x17: |
648 | 574bbf7b | bellard | val = s->isr[index & 7];
|
649 | 574bbf7b | bellard | break;
|
650 | 574bbf7b | bellard | case 0x18 ... 0x1f: |
651 | 574bbf7b | bellard | val = s->tmr[index & 7];
|
652 | 574bbf7b | bellard | break;
|
653 | 574bbf7b | bellard | case 0x20 ... 0x27: |
654 | 574bbf7b | bellard | val = s->irr[index & 7];
|
655 | 574bbf7b | bellard | break;
|
656 | 574bbf7b | bellard | case 0x28: |
657 | 574bbf7b | bellard | val = s->esr; |
658 | 574bbf7b | bellard | break;
|
659 | 574bbf7b | bellard | case 0x30: |
660 | 574bbf7b | bellard | case 0x31: |
661 | 574bbf7b | bellard | val = s->icr[index & 1];
|
662 | 574bbf7b | bellard | break;
|
663 | e0fd8781 | bellard | case 0x32 ... 0x37: |
664 | e0fd8781 | bellard | val = s->lvt[index - 0x32];
|
665 | e0fd8781 | bellard | break;
|
666 | 574bbf7b | bellard | case 0x38: |
667 | 574bbf7b | bellard | val = s->initial_count; |
668 | 574bbf7b | bellard | break;
|
669 | 574bbf7b | bellard | case 0x39: |
670 | 574bbf7b | bellard | val = apic_get_current_count(s); |
671 | 574bbf7b | bellard | break;
|
672 | 574bbf7b | bellard | case 0x3e: |
673 | 574bbf7b | bellard | val = s->divide_conf; |
674 | 574bbf7b | bellard | break;
|
675 | 574bbf7b | bellard | default:
|
676 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
677 | 574bbf7b | bellard | val = 0;
|
678 | 574bbf7b | bellard | break;
|
679 | 574bbf7b | bellard | } |
680 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
681 | 574bbf7b | bellard | printf("APIC read: %08x = %08x\n", (uint32_t)addr, val);
|
682 | 574bbf7b | bellard | #endif
|
683 | 574bbf7b | bellard | return val;
|
684 | 574bbf7b | bellard | } |
685 | 574bbf7b | bellard | |
686 | 574bbf7b | bellard | static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
687 | 574bbf7b | bellard | { |
688 | 574bbf7b | bellard | CPUState *env; |
689 | 574bbf7b | bellard | APICState *s; |
690 | 574bbf7b | bellard | int index;
|
691 | 574bbf7b | bellard | |
692 | 574bbf7b | bellard | env = cpu_single_env; |
693 | 574bbf7b | bellard | if (!env)
|
694 | 574bbf7b | bellard | return;
|
695 | 574bbf7b | bellard | s = env->apic_state; |
696 | 574bbf7b | bellard | |
697 | 574bbf7b | bellard | #ifdef DEBUG_APIC
|
698 | 574bbf7b | bellard | printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
|
699 | 574bbf7b | bellard | #endif
|
700 | 574bbf7b | bellard | |
701 | 574bbf7b | bellard | index = (addr >> 4) & 0xff; |
702 | 574bbf7b | bellard | switch(index) {
|
703 | 574bbf7b | bellard | case 0x02: |
704 | 574bbf7b | bellard | s->id = (val >> 24);
|
705 | 574bbf7b | bellard | break;
|
706 | e0fd8781 | bellard | case 0x03: |
707 | e0fd8781 | bellard | break;
|
708 | 574bbf7b | bellard | case 0x08: |
709 | 574bbf7b | bellard | s->tpr = val; |
710 | d592d303 | bellard | apic_update_irq(s); |
711 | 574bbf7b | bellard | break;
|
712 | e0fd8781 | bellard | case 0x09: |
713 | e0fd8781 | bellard | case 0x0a: |
714 | e0fd8781 | bellard | break;
|
715 | 574bbf7b | bellard | case 0x0b: /* EOI */ |
716 | 574bbf7b | bellard | apic_eoi(s); |
717 | 574bbf7b | bellard | break;
|
718 | d592d303 | bellard | case 0x0d: |
719 | d592d303 | bellard | s->log_dest = val >> 24;
|
720 | d592d303 | bellard | break;
|
721 | d592d303 | bellard | case 0x0e: |
722 | d592d303 | bellard | s->dest_mode = val >> 28;
|
723 | d592d303 | bellard | break;
|
724 | 574bbf7b | bellard | case 0x0f: |
725 | 574bbf7b | bellard | s->spurious_vec = val & 0x1ff;
|
726 | d592d303 | bellard | apic_update_irq(s); |
727 | 574bbf7b | bellard | break;
|
728 | e0fd8781 | bellard | case 0x10 ... 0x17: |
729 | e0fd8781 | bellard | case 0x18 ... 0x1f: |
730 | e0fd8781 | bellard | case 0x20 ... 0x27: |
731 | e0fd8781 | bellard | case 0x28: |
732 | e0fd8781 | bellard | break;
|
733 | 574bbf7b | bellard | case 0x30: |
734 | d592d303 | bellard | s->icr[0] = val;
|
735 | d592d303 | bellard | apic_deliver(s, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1, |
736 | d592d303 | bellard | (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff), |
737 | d592d303 | bellard | (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1); |
738 | d592d303 | bellard | break;
|
739 | 574bbf7b | bellard | case 0x31: |
740 | d592d303 | bellard | s->icr[1] = val;
|
741 | 574bbf7b | bellard | break;
|
742 | 574bbf7b | bellard | case 0x32 ... 0x37: |
743 | 574bbf7b | bellard | { |
744 | 574bbf7b | bellard | int n = index - 0x32; |
745 | 574bbf7b | bellard | s->lvt[n] = val; |
746 | 574bbf7b | bellard | if (n == APIC_LVT_TIMER)
|
747 | 574bbf7b | bellard | apic_timer_update(s, qemu_get_clock(vm_clock)); |
748 | 574bbf7b | bellard | } |
749 | 574bbf7b | bellard | break;
|
750 | 574bbf7b | bellard | case 0x38: |
751 | 574bbf7b | bellard | s->initial_count = val; |
752 | 574bbf7b | bellard | s->initial_count_load_time = qemu_get_clock(vm_clock); |
753 | 574bbf7b | bellard | apic_timer_update(s, s->initial_count_load_time); |
754 | 574bbf7b | bellard | break;
|
755 | e0fd8781 | bellard | case 0x39: |
756 | e0fd8781 | bellard | break;
|
757 | 574bbf7b | bellard | case 0x3e: |
758 | 574bbf7b | bellard | { |
759 | 574bbf7b | bellard | int v;
|
760 | 574bbf7b | bellard | s->divide_conf = val & 0xb;
|
761 | 574bbf7b | bellard | v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4); |
762 | 574bbf7b | bellard | s->count_shift = (v + 1) & 7; |
763 | 574bbf7b | bellard | } |
764 | 574bbf7b | bellard | break;
|
765 | 574bbf7b | bellard | default:
|
766 | 574bbf7b | bellard | s->esr |= ESR_ILLEGAL_ADDRESS; |
767 | 574bbf7b | bellard | break;
|
768 | 574bbf7b | bellard | } |
769 | 574bbf7b | bellard | } |
770 | 574bbf7b | bellard | |
771 | d592d303 | bellard | static void apic_save(QEMUFile *f, void *opaque) |
772 | d592d303 | bellard | { |
773 | d592d303 | bellard | APICState *s = opaque; |
774 | d592d303 | bellard | int i;
|
775 | d592d303 | bellard | |
776 | d592d303 | bellard | qemu_put_be32s(f, &s->apicbase); |
777 | d592d303 | bellard | qemu_put_8s(f, &s->id); |
778 | d592d303 | bellard | qemu_put_8s(f, &s->arb_id); |
779 | d592d303 | bellard | qemu_put_8s(f, &s->tpr); |
780 | d592d303 | bellard | qemu_put_be32s(f, &s->spurious_vec); |
781 | d592d303 | bellard | qemu_put_8s(f, &s->log_dest); |
782 | d592d303 | bellard | qemu_put_8s(f, &s->dest_mode); |
783 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
784 | d592d303 | bellard | qemu_put_be32s(f, &s->isr[i]); |
785 | d592d303 | bellard | qemu_put_be32s(f, &s->tmr[i]); |
786 | d592d303 | bellard | qemu_put_be32s(f, &s->irr[i]); |
787 | d592d303 | bellard | } |
788 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
789 | d592d303 | bellard | qemu_put_be32s(f, &s->lvt[i]); |
790 | d592d303 | bellard | } |
791 | d592d303 | bellard | qemu_put_be32s(f, &s->esr); |
792 | d592d303 | bellard | qemu_put_be32s(f, &s->icr[0]);
|
793 | d592d303 | bellard | qemu_put_be32s(f, &s->icr[1]);
|
794 | d592d303 | bellard | qemu_put_be32s(f, &s->divide_conf); |
795 | bee8d684 | ths | qemu_put_be32(f, s->count_shift); |
796 | d592d303 | bellard | qemu_put_be32s(f, &s->initial_count); |
797 | bee8d684 | ths | qemu_put_be64(f, s->initial_count_load_time); |
798 | bee8d684 | ths | qemu_put_be64(f, s->next_time); |
799 | e6cf6a8c | bellard | |
800 | e6cf6a8c | bellard | qemu_put_timer(f, s->timer); |
801 | d592d303 | bellard | } |
802 | d592d303 | bellard | |
803 | d592d303 | bellard | static int apic_load(QEMUFile *f, void *opaque, int version_id) |
804 | d592d303 | bellard | { |
805 | d592d303 | bellard | APICState *s = opaque; |
806 | d592d303 | bellard | int i;
|
807 | d592d303 | bellard | |
808 | e6cf6a8c | bellard | if (version_id > 2) |
809 | d592d303 | bellard | return -EINVAL;
|
810 | d592d303 | bellard | |
811 | d592d303 | bellard | /* XXX: what if the base changes? (registered memory regions) */
|
812 | d592d303 | bellard | qemu_get_be32s(f, &s->apicbase); |
813 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
814 | d592d303 | bellard | qemu_get_8s(f, &s->arb_id); |
815 | d592d303 | bellard | qemu_get_8s(f, &s->tpr); |
816 | d592d303 | bellard | qemu_get_be32s(f, &s->spurious_vec); |
817 | d592d303 | bellard | qemu_get_8s(f, &s->log_dest); |
818 | d592d303 | bellard | qemu_get_8s(f, &s->dest_mode); |
819 | d592d303 | bellard | for (i = 0; i < 8; i++) { |
820 | d592d303 | bellard | qemu_get_be32s(f, &s->isr[i]); |
821 | d592d303 | bellard | qemu_get_be32s(f, &s->tmr[i]); |
822 | d592d303 | bellard | qemu_get_be32s(f, &s->irr[i]); |
823 | d592d303 | bellard | } |
824 | d592d303 | bellard | for (i = 0; i < APIC_LVT_NB; i++) { |
825 | d592d303 | bellard | qemu_get_be32s(f, &s->lvt[i]); |
826 | d592d303 | bellard | } |
827 | d592d303 | bellard | qemu_get_be32s(f, &s->esr); |
828 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[0]);
|
829 | d592d303 | bellard | qemu_get_be32s(f, &s->icr[1]);
|
830 | d592d303 | bellard | qemu_get_be32s(f, &s->divide_conf); |
831 | bee8d684 | ths | s->count_shift=qemu_get_be32(f); |
832 | d592d303 | bellard | qemu_get_be32s(f, &s->initial_count); |
833 | bee8d684 | ths | s->initial_count_load_time=qemu_get_be64(f); |
834 | bee8d684 | ths | s->next_time=qemu_get_be64(f); |
835 | e6cf6a8c | bellard | |
836 | e6cf6a8c | bellard | if (version_id >= 2) |
837 | e6cf6a8c | bellard | qemu_get_timer(f, s->timer); |
838 | d592d303 | bellard | return 0; |
839 | d592d303 | bellard | } |
840 | 574bbf7b | bellard | |
841 | d592d303 | bellard | static void apic_reset(void *opaque) |
842 | d592d303 | bellard | { |
843 | d592d303 | bellard | APICState *s = opaque; |
844 | fec5fa02 | aurel32 | |
845 | fec5fa02 | aurel32 | s->apicbase = 0xfee00000 |
|
846 | fec5fa02 | aurel32 | (s->id ? 0 : MSR_IA32_APICBASE_BSP) | MSR_IA32_APICBASE_ENABLE;
|
847 | fec5fa02 | aurel32 | |
848 | d592d303 | bellard | apic_init_ipi(s); |
849 | 0e21e12b | ths | |
850 | a5b38b51 | aurel32 | if (s->id == 0) { |
851 | a5b38b51 | aurel32 | /*
|
852 | a5b38b51 | aurel32 | * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
|
853 | a5b38b51 | aurel32 | * time typically by BIOS, so PIC interrupt can be delivered to the
|
854 | a5b38b51 | aurel32 | * processor when local APIC is enabled.
|
855 | a5b38b51 | aurel32 | */
|
856 | a5b38b51 | aurel32 | s->lvt[APIC_LVT_LINT0] = 0x700;
|
857 | a5b38b51 | aurel32 | } |
858 | d592d303 | bellard | } |
859 | 574bbf7b | bellard | |
860 | 574bbf7b | bellard | static CPUReadMemoryFunc *apic_mem_read[3] = { |
861 | 574bbf7b | bellard | apic_mem_readb, |
862 | 574bbf7b | bellard | apic_mem_readw, |
863 | 574bbf7b | bellard | apic_mem_readl, |
864 | 574bbf7b | bellard | }; |
865 | 574bbf7b | bellard | |
866 | 574bbf7b | bellard | static CPUWriteMemoryFunc *apic_mem_write[3] = { |
867 | 574bbf7b | bellard | apic_mem_writeb, |
868 | 574bbf7b | bellard | apic_mem_writew, |
869 | 574bbf7b | bellard | apic_mem_writel, |
870 | 574bbf7b | bellard | }; |
871 | 574bbf7b | bellard | |
872 | 574bbf7b | bellard | int apic_init(CPUState *env)
|
873 | 574bbf7b | bellard | { |
874 | 574bbf7b | bellard | APICState *s; |
875 | 574bbf7b | bellard | |
876 | d3e9db93 | bellard | if (last_apic_id >= MAX_APICS)
|
877 | d3e9db93 | bellard | return -1; |
878 | d592d303 | bellard | s = qemu_mallocz(sizeof(APICState));
|
879 | 574bbf7b | bellard | if (!s)
|
880 | 574bbf7b | bellard | return -1; |
881 | 574bbf7b | bellard | env->apic_state = s; |
882 | d592d303 | bellard | s->id = last_apic_id++; |
883 | eae7629b | ths | env->cpuid_apic_id = s->id; |
884 | 574bbf7b | bellard | s->cpu_env = env; |
885 | 574bbf7b | bellard | |
886 | a5b38b51 | aurel32 | apic_reset(s); |
887 | 0e21e12b | ths | |
888 | d592d303 | bellard | /* XXX: mapping more APICs at the same memory location */
|
889 | 574bbf7b | bellard | if (apic_io_memory == 0) { |
890 | 574bbf7b | bellard | /* NOTE: the APIC is directly connected to the CPU - it is not
|
891 | 574bbf7b | bellard | on the global memory bus. */
|
892 | 5fafdf24 | ths | apic_io_memory = cpu_register_io_memory(0, apic_mem_read,
|
893 | 574bbf7b | bellard | apic_mem_write, NULL);
|
894 | d592d303 | bellard | cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000, |
895 | d592d303 | bellard | apic_io_memory); |
896 | 574bbf7b | bellard | } |
897 | 574bbf7b | bellard | s->timer = qemu_new_timer(vm_clock, apic_timer, s); |
898 | d592d303 | bellard | |
899 | be0164f2 | ths | register_savevm("apic", s->id, 2, apic_save, apic_load, s); |
900 | d592d303 | bellard | qemu_register_reset(apic_reset, s); |
901 | 3b46e624 | ths | |
902 | d3e9db93 | bellard | local_apics[s->id] = s; |
903 | d592d303 | bellard | return 0; |
904 | d592d303 | bellard | } |
905 | d592d303 | bellard | |
906 | d592d303 | bellard | static void ioapic_service(IOAPICState *s) |
907 | d592d303 | bellard | { |
908 | b1fc0348 | bellard | uint8_t i; |
909 | b1fc0348 | bellard | uint8_t trig_mode; |
910 | d592d303 | bellard | uint8_t vector; |
911 | b1fc0348 | bellard | uint8_t delivery_mode; |
912 | d592d303 | bellard | uint32_t mask; |
913 | d592d303 | bellard | uint64_t entry; |
914 | d592d303 | bellard | uint8_t dest; |
915 | d592d303 | bellard | uint8_t dest_mode; |
916 | b1fc0348 | bellard | uint8_t polarity; |
917 | d3e9db93 | bellard | uint32_t deliver_bitmask[MAX_APIC_WORDS]; |
918 | d592d303 | bellard | |
919 | b1fc0348 | bellard | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
920 | b1fc0348 | bellard | mask = 1 << i;
|
921 | d592d303 | bellard | if (s->irr & mask) {
|
922 | b1fc0348 | bellard | entry = s->ioredtbl[i]; |
923 | d592d303 | bellard | if (!(entry & APIC_LVT_MASKED)) {
|
924 | b1fc0348 | bellard | trig_mode = ((entry >> 15) & 1); |
925 | d592d303 | bellard | dest = entry >> 56;
|
926 | d592d303 | bellard | dest_mode = (entry >> 11) & 1; |
927 | b1fc0348 | bellard | delivery_mode = (entry >> 8) & 7; |
928 | b1fc0348 | bellard | polarity = (entry >> 13) & 1; |
929 | b1fc0348 | bellard | if (trig_mode == APIC_TRIGGER_EDGE)
|
930 | b1fc0348 | bellard | s->irr &= ~mask; |
931 | b1fc0348 | bellard | if (delivery_mode == APIC_DM_EXTINT)
|
932 | b1fc0348 | bellard | vector = pic_read_irq(isa_pic); |
933 | b1fc0348 | bellard | else
|
934 | b1fc0348 | bellard | vector = entry & 0xff;
|
935 | 3b46e624 | ths | |
936 | d3e9db93 | bellard | apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode); |
937 | 5fafdf24 | ths | apic_bus_deliver(deliver_bitmask, delivery_mode, |
938 | d3e9db93 | bellard | vector, polarity, trig_mode); |
939 | d592d303 | bellard | } |
940 | d592d303 | bellard | } |
941 | d592d303 | bellard | } |
942 | d592d303 | bellard | } |
943 | d592d303 | bellard | |
944 | d592d303 | bellard | void ioapic_set_irq(void *opaque, int vector, int level) |
945 | d592d303 | bellard | { |
946 | d592d303 | bellard | IOAPICState *s = opaque; |
947 | d592d303 | bellard | |
948 | d592d303 | bellard | if (vector >= 0 && vector < IOAPIC_NUM_PINS) { |
949 | d592d303 | bellard | uint32_t mask = 1 << vector;
|
950 | d592d303 | bellard | uint64_t entry = s->ioredtbl[vector]; |
951 | d592d303 | bellard | |
952 | d592d303 | bellard | if ((entry >> 15) & 1) { |
953 | d592d303 | bellard | /* level triggered */
|
954 | d592d303 | bellard | if (level) {
|
955 | d592d303 | bellard | s->irr |= mask; |
956 | d592d303 | bellard | ioapic_service(s); |
957 | d592d303 | bellard | } else {
|
958 | d592d303 | bellard | s->irr &= ~mask; |
959 | d592d303 | bellard | } |
960 | d592d303 | bellard | } else {
|
961 | d592d303 | bellard | /* edge triggered */
|
962 | d592d303 | bellard | if (level) {
|
963 | d592d303 | bellard | s->irr |= mask; |
964 | d592d303 | bellard | ioapic_service(s); |
965 | d592d303 | bellard | } |
966 | d592d303 | bellard | } |
967 | d592d303 | bellard | } |
968 | d592d303 | bellard | } |
969 | d592d303 | bellard | |
970 | d592d303 | bellard | static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr) |
971 | d592d303 | bellard | { |
972 | d592d303 | bellard | IOAPICState *s = opaque; |
973 | d592d303 | bellard | int index;
|
974 | d592d303 | bellard | uint32_t val = 0;
|
975 | d592d303 | bellard | |
976 | d592d303 | bellard | addr &= 0xff;
|
977 | d592d303 | bellard | if (addr == 0x00) { |
978 | d592d303 | bellard | val = s->ioregsel; |
979 | d592d303 | bellard | } else if (addr == 0x10) { |
980 | d592d303 | bellard | switch (s->ioregsel) {
|
981 | d592d303 | bellard | case 0x00: |
982 | d592d303 | bellard | val = s->id << 24;
|
983 | d592d303 | bellard | break;
|
984 | d592d303 | bellard | case 0x01: |
985 | d592d303 | bellard | val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */ |
986 | d592d303 | bellard | break;
|
987 | d592d303 | bellard | case 0x02: |
988 | d592d303 | bellard | val = 0;
|
989 | d592d303 | bellard | break;
|
990 | d592d303 | bellard | default:
|
991 | d592d303 | bellard | index = (s->ioregsel - 0x10) >> 1; |
992 | d592d303 | bellard | if (index >= 0 && index < IOAPIC_NUM_PINS) { |
993 | d592d303 | bellard | if (s->ioregsel & 1) |
994 | d592d303 | bellard | val = s->ioredtbl[index] >> 32;
|
995 | d592d303 | bellard | else
|
996 | d592d303 | bellard | val = s->ioredtbl[index] & 0xffffffff;
|
997 | d592d303 | bellard | } |
998 | d592d303 | bellard | } |
999 | d592d303 | bellard | #ifdef DEBUG_IOAPIC
|
1000 | d592d303 | bellard | printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
|
1001 | d592d303 | bellard | #endif
|
1002 | d592d303 | bellard | } |
1003 | d592d303 | bellard | return val;
|
1004 | d592d303 | bellard | } |
1005 | d592d303 | bellard | |
1006 | d592d303 | bellard | static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
1007 | d592d303 | bellard | { |
1008 | d592d303 | bellard | IOAPICState *s = opaque; |
1009 | d592d303 | bellard | int index;
|
1010 | d592d303 | bellard | |
1011 | d592d303 | bellard | addr &= 0xff;
|
1012 | d592d303 | bellard | if (addr == 0x00) { |
1013 | d592d303 | bellard | s->ioregsel = val; |
1014 | d592d303 | bellard | return;
|
1015 | d592d303 | bellard | } else if (addr == 0x10) { |
1016 | d592d303 | bellard | #ifdef DEBUG_IOAPIC
|
1017 | d592d303 | bellard | printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
|
1018 | d592d303 | bellard | #endif
|
1019 | d592d303 | bellard | switch (s->ioregsel) {
|
1020 | d592d303 | bellard | case 0x00: |
1021 | d592d303 | bellard | s->id = (val >> 24) & 0xff; |
1022 | d592d303 | bellard | return;
|
1023 | d592d303 | bellard | case 0x01: |
1024 | d592d303 | bellard | case 0x02: |
1025 | d592d303 | bellard | return;
|
1026 | d592d303 | bellard | default:
|
1027 | d592d303 | bellard | index = (s->ioregsel - 0x10) >> 1; |
1028 | d592d303 | bellard | if (index >= 0 && index < IOAPIC_NUM_PINS) { |
1029 | d592d303 | bellard | if (s->ioregsel & 1) { |
1030 | d592d303 | bellard | s->ioredtbl[index] &= 0xffffffff;
|
1031 | d592d303 | bellard | s->ioredtbl[index] |= (uint64_t)val << 32;
|
1032 | d592d303 | bellard | } else {
|
1033 | d592d303 | bellard | s->ioredtbl[index] &= ~0xffffffffULL;
|
1034 | d592d303 | bellard | s->ioredtbl[index] |= val; |
1035 | d592d303 | bellard | } |
1036 | d592d303 | bellard | ioapic_service(s); |
1037 | d592d303 | bellard | } |
1038 | d592d303 | bellard | } |
1039 | d592d303 | bellard | } |
1040 | d592d303 | bellard | } |
1041 | d592d303 | bellard | |
1042 | d592d303 | bellard | static void ioapic_save(QEMUFile *f, void *opaque) |
1043 | d592d303 | bellard | { |
1044 | d592d303 | bellard | IOAPICState *s = opaque; |
1045 | d592d303 | bellard | int i;
|
1046 | d592d303 | bellard | |
1047 | d592d303 | bellard | qemu_put_8s(f, &s->id); |
1048 | d592d303 | bellard | qemu_put_8s(f, &s->ioregsel); |
1049 | d592d303 | bellard | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
1050 | d592d303 | bellard | qemu_put_be64s(f, &s->ioredtbl[i]); |
1051 | d592d303 | bellard | } |
1052 | d592d303 | bellard | } |
1053 | d592d303 | bellard | |
1054 | d592d303 | bellard | static int ioapic_load(QEMUFile *f, void *opaque, int version_id) |
1055 | d592d303 | bellard | { |
1056 | d592d303 | bellard | IOAPICState *s = opaque; |
1057 | d592d303 | bellard | int i;
|
1058 | d592d303 | bellard | |
1059 | d592d303 | bellard | if (version_id != 1) |
1060 | d592d303 | bellard | return -EINVAL;
|
1061 | d592d303 | bellard | |
1062 | d592d303 | bellard | qemu_get_8s(f, &s->id); |
1063 | d592d303 | bellard | qemu_get_8s(f, &s->ioregsel); |
1064 | d592d303 | bellard | for (i = 0; i < IOAPIC_NUM_PINS; i++) { |
1065 | d592d303 | bellard | qemu_get_be64s(f, &s->ioredtbl[i]); |
1066 | d592d303 | bellard | } |
1067 | 574bbf7b | bellard | return 0; |
1068 | 574bbf7b | bellard | } |
1069 | d592d303 | bellard | |
1070 | d592d303 | bellard | static void ioapic_reset(void *opaque) |
1071 | d592d303 | bellard | { |
1072 | d592d303 | bellard | IOAPICState *s = opaque; |
1073 | d592d303 | bellard | int i;
|
1074 | d592d303 | bellard | |
1075 | d592d303 | bellard | memset(s, 0, sizeof(*s)); |
1076 | d592d303 | bellard | for(i = 0; i < IOAPIC_NUM_PINS; i++) |
1077 | d592d303 | bellard | s->ioredtbl[i] = 1 << 16; /* mask LVT */ |
1078 | d592d303 | bellard | } |
1079 | d592d303 | bellard | |
1080 | d592d303 | bellard | static CPUReadMemoryFunc *ioapic_mem_read[3] = { |
1081 | d592d303 | bellard | ioapic_mem_readl, |
1082 | d592d303 | bellard | ioapic_mem_readl, |
1083 | d592d303 | bellard | ioapic_mem_readl, |
1084 | d592d303 | bellard | }; |
1085 | d592d303 | bellard | |
1086 | d592d303 | bellard | static CPUWriteMemoryFunc *ioapic_mem_write[3] = { |
1087 | d592d303 | bellard | ioapic_mem_writel, |
1088 | d592d303 | bellard | ioapic_mem_writel, |
1089 | d592d303 | bellard | ioapic_mem_writel, |
1090 | d592d303 | bellard | }; |
1091 | d592d303 | bellard | |
1092 | d592d303 | bellard | IOAPICState *ioapic_init(void)
|
1093 | d592d303 | bellard | { |
1094 | d592d303 | bellard | IOAPICState *s; |
1095 | d592d303 | bellard | int io_memory;
|
1096 | d592d303 | bellard | |
1097 | b1fc0348 | bellard | s = qemu_mallocz(sizeof(IOAPICState));
|
1098 | d592d303 | bellard | if (!s)
|
1099 | d592d303 | bellard | return NULL; |
1100 | d592d303 | bellard | ioapic_reset(s); |
1101 | d592d303 | bellard | s->id = last_apic_id++; |
1102 | d592d303 | bellard | |
1103 | 5fafdf24 | ths | io_memory = cpu_register_io_memory(0, ioapic_mem_read,
|
1104 | d592d303 | bellard | ioapic_mem_write, s); |
1105 | d592d303 | bellard | cpu_register_physical_memory(0xfec00000, 0x1000, io_memory); |
1106 | d592d303 | bellard | |
1107 | d592d303 | bellard | register_savevm("ioapic", 0, 1, ioapic_save, ioapic_load, s); |
1108 | d592d303 | bellard | qemu_register_reset(ioapic_reset, s); |
1109 | 3b46e624 | ths | |
1110 | d592d303 | bellard | return s;
|
1111 | d592d303 | bellard | } |