Activity
From 12/10/2013 to 01/08/2014
01/08/2014
- 09:07 pm Revision 52a1f6a3: target-arm: A64: Add floating-point<->fixed-point instructions
- This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM A... - 09:07 pm Revision c436d406: target-arm: A64: Add floating-point<->integer conversion instructions
- Add support for the AArch64 floating-point <-> integer conversion
instructions to disas_fpintconv. In the process we ... - 09:07 pm Revision d9b0848d: target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
- This patch adds support for those instructions in the "Floating-point
data-processing (1 source)" group which are si... - 09:07 pm Revision 8900aad2: target-arm: A64: Add support for FCVT between half, single and double
- Add support for FCVT between half, single and double precision.
Signed-off-by: Peter Maydell <peter.maydell@linaro.o... - 09:07 pm Revision 3c85c37f: softfloat: Fix factor 2 error for scalbn on denormal inputs
- If the input to float*_scalbn() is denormal then it represents
a number 0.[mantissabits] * 2^(1-exponentbias) (and th... - 09:07 pm Revision 04050c5c: arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER
- TRIGGER can really mean mean anything (e.g. was it triggered, is it
level-triggered, is it edge-triggered, etc.). Re... - 09:07 pm Revision 9df90ad0: hw: arm_gic: Introduce gic_set_priority function
- To make the code slightly cleaner to look at and make the save/restore
code easier to understand, introduce this func... - 09:07 pm Revision 38970efa: softfloat: Fix exception flag handling for float32_to_float16()
- Our float32 to float16 conversion routine was generating the correct
numerical answers, but not always setting the ri... - 09:07 pm Revision f581bf54: softfloat: Add float to 16bit integer conversions.
- ARMv8 requires support for converting 32 and 64bit floating point
values to signed and unsigned 16bit integers.
Sign... - 09:07 pm Revision 8afbdaba: softfloat: Add 16 bit integer to float conversions
- Add the float to 16 bit integer conversion routines. These can be
trivially implemented in terms of the int32_to_floa... - 09:07 pm Revision c4850f9e: softfloat: Make the int-to-float functions take exact-width types
- Currently the int-to-float functions take types which are specified
as "at least X bits wide", rather than "exactly X... - 09:07 pm Revision fb3ea83a: softfloat: Fix float64_to_uint64
- The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed,... - 09:07 pm Revision 34e1c27b: softfloat: Only raise Invalid when conversions to int are out of range
- We implement a number of float-to-integer conversions using conversion
to an integer type with a wider range and then... - 09:07 pm Revision 7b1aa025: target-arm: fix build with gcc 4.8.2
- commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aar... - 09:07 pm Revision 2f18bbf9: softfloat: Add float32_to_uint64()
- This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit ... - 09:07 pm Revision 0a87a310: softfloat: Fix float64_to_uint64_round_to_zero
- The float64_to_uint64_round_to_zero routine is incorrect.
For example, the following test pattern:
46697351FF4A... - 09:07 pm Revision 5e7f654f: softfloat: Fix float64_to_uint32
- The float64_to_uint32 has several flaws:
- for numbers between 2**32 and 2**64, the inexact exception flag
may g... - 09:07 pm Revision fd728f2f: softfloat: Fix float64_to_uint32_round_to_zero
- The float64_to_uint32_round_to_zero routine is incorrect.
For example, the following test pattern:
425F81378DC0... - 09:07 pm Revision 879d096b: softfloat: Provide complete set of accessors for fp state
- Tidy up the get/set accessors for the fp state to add missing ones
and make them all inline in softfloat.h rather tha... - 09:07 pm Revision c4a1c5e7: softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
- In preparation for adding conversions between float16 and float64,
factor out code currently done inline in the float... - 09:07 pm Revision 14c9a07e: softfloat: Add float16 <=> float64 conversion functions
- Add the conversion functions float16_to_float64() and
float64_to_float16(), which will be needed for the ARM
A64 inst... - 09:07 pm Revision dc355b76: softfloat: Refactor code handling various rounding modes
- Refactor the code in various functions which calculates rounding
increments given the current rounding mode, so that ... - 09:07 pm Revision f9288a76: softfloat: Add support for ties-away rounding
- IEEE754-2008 specifies a new rounding mode:
"roundTiesToAway: the floating-point number nearest to the infinitely
pr... - 09:07 pm Revision 8ed697e8: target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
- Make the VFP_CONV_FIX helpers a little more flexible in
preparation for the A64 uses. This requires two changes:
* u... - 09:07 pm Revision 16d5b3ca: target-arm: Rename A32 VFP conversion helpers
- The VFP conversion helpers for A32 round to zero as this is the only
rounding mode supported. Rename these helpers to... - 09:07 pm Revision 3c6a074a: target-arm: A64: Add extra VFP fixed point conversion helpers
- Define the full set of floating point to fixed point conversion
helpers required to support AArch64.
Signed-off-by: ... - 09:07 pm Revision abe66f70: target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
- The VFP fixed point conversion helpers first call float_scalbn and
then convert the result to an integer. This scalbn... - 09:07 pm Revision 13a7f79d: default-configs: Add config for aarch64-linux-user
- Add a config for aarch64-linux-user, thereby enabling it as
a valid target.
Signed-off-by: Peter Maydell <peter.mayd... - 09:07 pm Revision f6d8a314: target-arm: A64: Add support for dumping AArch64 VFP register state
- When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer stat... - 09:07 pm Revision e2f90565: target-arm: A64: Fix vector register access on bigendian hosts
- The A64 128 bit vector registers are stored as a pair of
uint64_t values in the register array. This means that if
we... - 09:07 pm Revision f71a2ae5: target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
- Use the VFP_BINOP macro to provide helpers for min, max, minnum
and maxnum, rather than hand-rolling them. (The float... - 09:07 pm Revision ec73d2e0: target-arm: A64: Add "Floating-point data-processing (2 source)" insns
- This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.
Signed-off-by: ... - 09:07 pm Revision 6a30667f: target-arm: A64: Add "Floating-point data-processing (3 source)" insns
- This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.
Signed-off-by: ... - 09:07 pm Revision 6163f868: target-arm: A64: Add fmov (scalar, immediate) instruction
- This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alex... - 09:07 pm Revision da7dafe7: target-arm: A64: Add support for floating point compare
- Add decoding support for C3.6.22 Floating-point compare.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>... - 09:07 pm Revision 513f1d76: target-arm: A64: Add support for floating point conditional compare
- This adds decoding support for C3.6.23 FP Conditional Compare.
Signed-off-by: Claudio Fontana <claudio.fontana@linar... - 09:07 pm Revision 5640ff62: target-arm: A64: Add support for floating point cond select
- This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro... - 09:07 pm Revision 4d3da0f3: target-arm: Give the FPSCR rounding modes names
- When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statemen... - 09:07 pm Revision 059ca2bf: char/cadence_uart: Mark struct fields as public/private
- As per current QOM conventions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: a1e31bd6... - 09:07 pm Revision 589bfb68: char/cadence_uart: Add missing uart_update_state
- This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the in... - 09:07 pm Revision 823dd487: char/cadence_uart: Fix reset.
- Don't reset the uart as an init step. Register the reset function as a
proper reset fn instead.
Signed-off-by: Peter... - 09:07 pm Revision 1e77c91e: char/cadence_uart: s/r_fifo/rx_fifo
- Rename this field to match the many other uses of "rx". Xilinx
docmentation (UG585) also refers to this as "RxFIFO".
... - 09:07 pm Revision 676f4c09: char/cadence_uart: Simplify status generation
- The status register bits are always pure functions of other device
state. Move the generation of these bits to the up... - 09:07 pm Revision 11a239a5: char/cadence_uart: Define Missing SR/ISR fields
- Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares suppor... - 09:07 pm Revision 2152e08a: char/cadence_uart: Remove TX timer & add TX FIFO state
- This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the ... - 09:07 pm Revision 7fcd57e8: arm/xilinx_zynq: Always instantiate the GEMs
- Don't conditionalise GEM instantiation on networking attachments. The
device should always be present even if not att... - 09:07 pm Revision 86baecc3: char/cadence_uart: Use the TX fifo for transmission
- Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.
Sig... - 09:07 pm Revision 1e5d8cac: char/cadence_uart: Delete redundant rx rst logic
- uart_rx_reset() called immediately above already does this. Remove.
Signed-off-by: Peter Crosthwaite <peter.crosthwa... - 09:07 pm Revision 38acd64b: char/cadence_uart: Implement Tx flow control
- If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char ... - 09:07 pm Revision a4f0cec6: target-arm: use c13_context field for CONTEXTIDR
- Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov <s.fedor... - 09:07 pm Revision afb2530f: target-arm: remove raw_read|write duplication
- There is an inline duplication of the raw_read and raw_write function
bodies. Fix by just calling raw_read/raw_write ... - 09:07 pm Revision d0ac820f: char/cadence_uart: Fix can_receive logic
- The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo ... - 09:07 pm Revision 643dbb07: target-arm: A64: add support for add/sub with carry
- This patch adds support for C3.5.3 Add/subtract (with carry):
instructions ADC, ADCS, SBC, SBCS.
Signed-off-by: Clau... - 09:07 pm Revision 750813cf: target-arm: A64: add support for conditional compare insns
- this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)
Signed-off-by: Claudio... - 09:07 pm Revision 32b64e86: target-arm: aarch64: add support for ld lit
- Adds support for Load Register (literal), both normal
and SIMD/FP forms.
Signed-off-by: Alexander Graf <agraf@suse.d... - 09:07 pm Revision 03d05e2d: target-arm: Widen exclusive-access support struct fields to 64 bits
- In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct... - 09:07 pm Revision fa2ef212: target-arm: A64: support for ld/st/cl exclusive
- This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive loa... - 09:07 pm Revision 1b69f006: linux-user: AArch64: define TARGET_CLONE_BACKWARDS
- The AArch64 linux-user support was written before but merged after
commit 4ce6243dc621 which cleaned up the handling ... - 09:07 pm Revision e0ee138b: linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext
- Use the helpers provided for getting the correct FPSR and FPCR
values for the signal context.
Signed-off-by: Will Ne... - 09:07 pm Revision 08aef910: .travis.yml: Add aarch64-* targets
- Now the AArch64 targets are in mainline we can include them in our
Travis test matrix.
Signed-off-by: Alex Bennée <a...
01/07/2014
- 10:39 pm Revision 78261634: target-i386: Tidy ljmp
- Remove an unnecessary move opcode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Hend... - 10:39 pm Revision 74bdfbda: target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v
- And make the destination argument explicit.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Ric... - 10:38 pm Revision 830a19a4: target-i386: Tidy some size computation
- Clean up relics of multiple size domains: - MO_16 + 1 => - 1 + 1 => 0.
Reviewed-by: Peter Maydell <peter.maydell@lin... - 10:36 pm Revision 33b7891b: target-i386: Remove gen_op_mov_reg_A0
- Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson ... - 10:36 pm Revision c56baccf: target-i386: Remove gen_op_mov_TN_reg
- Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson ... - 10:32 pm Revision fd5185ec: target-i386: Remove gen_op_addl_T0_T1
- Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson ... - 10:32 pm Revision 68773f84: target-i386: Remove gen_op_mov_reg_T1
- Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson ... - 10:30 pm Revision 480a762d: target-i386: Remove gen_op_mov_reg_T0
- Replace with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson ... - 10:16 pm Revision fac0aff9: target-i386: Tidy cpu_regs initialization
- Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net> - 09:40 pm Revision 7effd625: target-i386: Tidy addr16 code in gen_lea_modrm
- Unlike the addr32, there was no bug. But we can use the same
technique to reduce the number of TCG ops.
Reviewed-by... - 09:40 pm Revision 432baffe: target-i386: Combine gen_push_T* into gen_push_v
- Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated.
Add forgotten zero-extension i... - 09:40 pm Revision 8e31d234: target_i386: Clean up gen_pop_T0
- Reduce ifdefs, share more code between paths, reduce the number of TCG
ops generated. Avoid re-computing the size of... - 09:40 pm Revision ab4e4aec: target-i386: Change dflag to TCGMemOp
- Changing the domain to TCGMemOp makes it easier to interoperate
with other portions of the rest of the translator.
W... - 09:38 pm Revision 6f17675a: target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp
- Change the domain of the parameter and update all callers.
Which lets us defer completely to gen_op_mov_reg_v.
Revie... - 09:38 pm Revision 1d71ddb1: target-i386: Change aflag to TCGMemOp
- Changing the domain to TCGMemOp makes it easier to interoperate
with other portions of the rest of the translator.
R... - 09:37 pm Revision d3f4bbe3: target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp
- These functions used the aflags/dflags domain, which is log2-1
of the byte size. Confusingly, they used enumeration ... - 09:37 pm Revision c92aa1ad: target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp
- Change the domain of the parameter and update all callers.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Sig... - 09:37 pm Revision d67dc9e6: target-i386: Use TCGMemOp for 'ot' variables
- The 'ot' variables (operand type?) hold the log2(byte size) of
the operand being manipulated. This is the same as th... - 09:36 pm Revision 2b98a7d7: target-i386: Remove gen_op_movl_T0_T1
- Replace it with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henders... - 09:36 pm Revision a7e5c7de: target-i386: Remove gen_op_andl_A0_ffff
- Replace it with tcg_gen_ext16u_tl, and in two cases merge with a
previous move from cpu_regs.
Reviewed-by: Peter May... - 09:36 pm Revision d5601ad0: target-i386: Tidy extend + store
- We can now use tcg_gen_qemu_st_i32 directly to avoid the extension.
Reviewed-by: Peter Maydell <peter.maydell@linaro... - 09:36 pm Revision a7fbcbe5: target-i386: Tidy extend + move
- For the known MO_32/MO_64 cases, we don't need to extend a 32-bit temp
into a 64-bit temp before storing into the har... - 09:36 pm Revision 97212c88: target-i386: Remove gen_op_movl_T0_0
- Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richar... - 09:36 pm Revision 1b90d56e: target-i386: Remove gen_op_movl_T0_im*
- Propagate the definition of gen_op_movl_T0_im to all users.
The function gen_op_movl_T0_imu was unused.
Reviewed-by:... - 09:36 pm Revision 0ae657b1: target-i386: Remove gen_op_movl_T0_im*
- Propagate the definitions into all users. The only time that
gen_op_movl_T1_imu was used, the input was type 'unsign... - 09:36 pm Revision 3250cff8: target-i386: Remove gen_op_mov*_A0_im
- Propagate the definitions into all users. In two cases, this allows
us to share code between the 32-bit and 64-bit i... - 09:36 pm Revision cc0bce88: target-i386: Remove gen_movtl_T*_im
- Propagate the definitions into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richa... - 09:36 pm Revision 40b90233: target-i386: Remove gen_op_andl_T0_ffff
- Replace it with tcg_gen_ext16u_tl. In four places we can combine that
with a previous move into cpu_T[0], and in one... - 09:36 pm Revision f0706f0c: target-i386: Remove gen_op_andl_T0_im
- Replace it with its definition.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henders... - 09:36 pm Revision fd8ca9f6: target-i386: Remove gen_op_st_T0_A0
- Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richar... - 09:36 pm Revision b5afc104: target-i386: Remove gen_op_st_T1_A0
- Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richar... - 09:36 pm Revision ee3138da: target-i386: Fix typo in gen_push_T1
- By inspection, obviously we should be storing T[1] not T[0].
This could only happen for x86_64 in 64-bit mode with 0x... - 09:36 pm Revision c8fbc479: target-i386: Tidy mov[sz][bw]
- We can use the MO_SIGN bit to tidy the reg-reg switch statement
as well as pass it on to gen_op_ld_v, eliminating one... - 09:36 pm Revision 4b1fe067: target-i386: Tidy movsl
- Always perform a sign-extending load. In the extremely unlikely
case that we've used an 0x66 prefix, the extension t... - 09:36 pm Revision 4eeb3939: target-i386: Remove unused arguments to gen_lea_modrm
- The reg_ptr and offset_ptr outputs are universally unused.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Sig... - 09:36 pm Revision 3655a19f: target-i386: Use MO_BE for movbe
- Fold the bswap into the memory operation.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richa... - 09:36 pm Revision 24b9c00f: target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32
- For the 16 and 32-bit cases, we don't need to truncate via
a temporary register.
Reviewed-by: Peter Maydell <peter.m... - 09:36 pm Revision 80b02013: target-i386: Tidy load + truncate
- We can now use tcg_gen_qemu_ld_i32 directly to avoid the truncation.
Reviewed-by: Peter Maydell <peter.maydell@linar... - 09:36 pm Revision 909be183: target-i386: Remove gen_op_ld_T0_A0
- Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richar... - 09:36 pm Revision cc1a80df: target-i386: Remove gen_op_ldu_T0_A0
- Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richar... - 09:36 pm Revision 0f712e10: target-i386: Remove gen_op_ld_T1_A0
- Propagate its definition into all users.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richar... - 09:36 pm Revision dc732b76: target-i386: Remove gen_op_lds_T0_A0
- Replace its users by gen_op_ld_v with the MO_SIGN bit set.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Sig... - 09:36 pm Revision d4faa3e0: target-i386: Introduce gen_op_st_rm_T0_A0
- Too many places have the same test vs OR_TMP0 to indicate
a write back to memory. Hoist that to a subroutine.
Revie... - 09:36 pm Revision 4ba9938c: target-i386: Replace OT_* constants with MO_* constants
- The MO_8/16/32/64 constants have the same encoding and meaning
as the OT_BYTE/WORD/LONG/QUAD. Since we rely on them ... - 09:18 pm Revision 84c6b75d: softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
- In preparation for adding conversions between float16 and float64,
factor out code currently done inline in the float... - 09:18 pm Revision 7b378119: softfloat: Add float16 <=> float64 conversion functions
- Add the conversion functions float16_to_float64() and
float64_to_float16(), which will be needed for the ARM
A64 inst... - 09:18 pm Revision 01a0b83c: softfloat: Refactor code handling various rounding modes
- Refactor the code in various functions which calculates rounding
increments given the current rounding mode, so that ... - 09:18 pm Revision dcc69632: softfloat: Add support for ties-away rounding
- IEEE754-2008 specifies a new rounding mode:
"roundTiesToAway: the floating-point number nearest to the infinitely
pr... - 09:18 pm Revision 59af2dc8: target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
- Make the VFP_CONV_FIX helpers a little more flexible in
preparation for the A64 uses. This requires two changes:
* u... - 09:18 pm Revision 6ab748af: target-arm: Rename A32 VFP conversion helpers
- The VFP conversion helpers for A32 round to zero as this is the only
rounding mode supported. Rename these helpers to... - 09:18 pm Revision 39905e53: target-arm: Ignore most exceptions from scalbn when doing fixpoint conversion
- The VFP fixed point conversion helpers first call float_scalbn and
then convert the result to an integer. This scalbn... - 09:18 pm Revision 8fe2a36f: target-arm: A64: Add extra VFP fixed point conversion helpers
- Define the full set of floating point to fixed point conversion
helpers required to support AArch64.
Signed-off-by: ... - 09:18 pm Revision 3617f86b: target-arm: A64: Add floating-point<->fixed-point instructions
- This patch adds emulation for the instruction group labeled
"Floating-point <-> fixed-point conversions" in the ARM A... - 09:18 pm Revision 6a741338: target-arm: A64: Add floating-point<->integer conversion instructions
- Add support for the AArch64 floating-point <-> integer conversion
instructions to disas_fpintconv. In the process we ... - 09:18 pm Revision e97db91c: target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
- This patch adds support for those instructions in the "Floating-point
data-processing (1 source)" group which are si... - 09:18 pm Revision 096fc768: target-arm: A64: Add support for FCVT between half, single and double
- Add support for FCVT between half, single and double precision.
Signed-off-by: Peter Maydell <peter.maydell@linaro.o... - 09:18 pm Revision 294cdac2: char/cadence_uart: Implement Tx flow control
- If the UART back-end blocks, buffer in the Tx FIFO to try again later.
This stops the IO-thread busy waiting on char ... - 09:18 pm Revision d045815a: target-arm: use c13_context field for CONTEXTIDR
- Use c13_context field instead of c13_fcse for CONTEXTIDR register
definition.
Signed-off-by: Sergey Fedorov <s.fedor... - 09:18 pm Revision 8455bc76: target-arm: remove raw_read|write duplication
- There is an inline duplication of the raw_read and raw_write function
bodies. Fix by just calling raw_read/raw_write ... - 09:18 pm Revision ec0e68ef: arm/xilinx_zynq: Always instantiate the GEMs
- Don't conditionalise GEM instantiation on networking attachments. The
device should always be present even if not att... - 09:18 pm Revision 455e1e14: target-arm: fix build with gcc 4.8.2
- commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aar... - 09:18 pm Revision 07c93508: arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER
- TRIGGER can really mean mean anything (e.g. was it triggered, is it
level-triggered, is it edge-triggered, etc.). Re... - 09:18 pm Revision e3d8cc05: hw: arm_gic: Introduce gic_set_priority function
- To make the code slightly cleaner to look at and make the save/restore
code easier to understand, introduce this func... - 09:18 pm Revision 1bf6beec: softfloat: Fix exception flag handling for float32_to_float16()
- Our float32 to float16 conversion routine was generating the correct
numerical answers, but not always setting the ri... - 09:18 pm Revision e0a2db71: softfloat: Add float to 16bit integer conversions.
- ARMv8 requires support for converting 32 and 64bit floating point
values to signed and unsigned 16bit integers.
Sign... - 09:18 pm Revision 44e09132: softfloat: Add 16 bit integer to float conversions
- Add the float to 16 bit integer conversion routines. These can be
trivially implemented in terms of the int32_to_floa... - 09:18 pm Revision 564658dc: softfloat: Make the int-to-float functions take exact-width types
- Currently the int-to-float functions take types which are specified
as "at least X bits wide", rather than "exactly X... - 09:18 pm Revision f883b389: softfloat: Fix float64_to_uint64
- The comment preceding the float64_to_uint64 routine suggests that
the implementation is broken. And this is, indeed,... - 09:18 pm Revision f2e933d2: softfloat: Only raise Invalid when conversions to int are out of range
- We implement a number of float-to-integer conversions using conversion
to an integer type with a wider range and then... - 09:18 pm Revision 0ace25a5: softfloat: Fix factor 2 error for scalbn on denormal inputs
- If the input to float*_scalbn() is denormal then it represents
a number 0.[mantissabits] * 2^(1-exponentbias) (and th... - 09:18 pm Revision 47a34e00: softfloat: Add float32_to_uint64()
- This patch adds the float32_to_uint64() routine, which converts a
32-bit floating point number to an unsigned 64 bit ... - 09:18 pm Revision a757f1c2: softfloat: Fix float64_to_uint64_round_to_zero
- The float64_to_uint64_round_to_zero routine is incorrect.
For example, the following test pattern:
46697351FF4A... - 09:18 pm Revision 8d551c98: softfloat: Fix float64_to_uint32
- The float64_to_uint32 has several flaws:
- for numbers between 2**32 and 2**64, the inexact exception flag
may g... - 09:18 pm Revision 2958f14d: softfloat: Fix float64_to_uint32_round_to_zero
- The float64_to_uint32_round_to_zero routine is incorrect.
For example, the following test pattern:
425F81378DC0... - 09:18 pm Revision e9ef30c0: softfloat: Provide complete set of accessors for fp state
- Tidy up the get/set accessors for the fp state to add missing ones
and make them all inline in softfloat.h rather tha... - 09:18 pm Revision 76afb0d5: target-arm: A64: Fix vector register access on bigendian hosts
- The A64 128 bit vector registers are stored as a pair of
uint64_t values in the register array. This means that if
we... - 09:18 pm Revision 286cb8b9: target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
- Use the VFP_BINOP macro to provide helpers for min, max, minnum
and maxnum, rather than hand-rolling them. (The float... - 09:18 pm Revision 459cc342: target-arm: A64: Add "Floating-point data-processing (2 source)" insns
- This patch adds emulation for the "Floating-point data-processing (2 source)"
group of instructions.
Signed-off-by: ... - 09:18 pm Revision cd54be5f: target-arm: A64: Add "Floating-point data-processing (3 source)" insns
- This patch adds emulation for the "Floating-point data-processing (3 source)"
group of instructions.
Signed-off-by: ... - 09:18 pm Revision 624490c3: target-arm: A64: Add fmov (scalar, immediate) instruction
- This patch adds emulation for the fmov instruction working on scalars
with an immediate payload.
Signed-off-by: Alex... - 09:18 pm Revision 24497657: target-arm: A64: Add support for floating point compare
- Add decoding support for C3.6.22 Floating-point compare.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>... - 09:18 pm Revision 32ca04a6: target-arm: A64: Add support for floating point conditional compare
- This adds decoding support for C3.6.23 FP Conditional Compare.
Signed-off-by: Claudio Fontana <claudio.fontana@linar... - 09:18 pm Revision 7b2440e4: target-arm: A64: Add support for floating point cond select
- This adds decoding support for C3.6.24 FP conditional select.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro... - 09:18 pm Revision f9dfa558: target-arm: Give the FPSCR rounding modes names
- When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statemen... - 09:18 pm Revision 2c7fd04c: char/cadence_uart: Mark struct fields as public/private
- As per current QOM conventions.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: a1e31bd6... - 09:18 pm Revision 362f6568: char/cadence_uart: Add missing uart_update_state
- This should be rechecked on bus write accesses as such accesses may
change the underlying state that generates the in... - 09:18 pm Revision b56fab88: char/cadence_uart: Fix reset.
- Don't reset the uart as an init step. Register the reset function as a
proper reset fn instead.
Signed-off-by: Peter... - 09:18 pm Revision 8998a3c0: char/cadence_uart: s/r_fifo/rx_fifo
- Rename this field to match the many other uses of "rx". Xilinx
docmentation (UG585) also refers to this as "RxFIFO".
... - 09:18 pm Revision a24234ca: char/cadence_uart: Simplify status generation
- The status register bits are always pure functions of other device
state. Move the generation of these bits to the up... - 09:18 pm Revision 2c628d98: char/cadence_uart: Define Missing SR/ISR fields
- Some (interrupt) status register bits relating to the TxFIFO path were
not defined. Define them. This prepares suppor... - 09:18 pm Revision faa79359: char/cadence_uart: Remove TX timer & add TX FIFO state
- This tx timer implementation is flawed. Despite the controller
attempting to time the guest visable assertion of the ... - 09:18 pm Revision 61654c77: char/cadence_uart: Fix can_receive logic
- The can_receive logic was only taking into account the RxFIFO
occupancy. RxFIFO population is only used for the echo ... - 09:18 pm Revision 9e263f73: char/cadence_uart: Use the TX fifo for transmission
- Populate the TxFIFO with the Tx data before sending. Prepares
support for proper Tx flow control implementation.
Sig... - 09:18 pm Revision a33f37a1: char/cadence_uart: Delete redundant rx rst logic
- uart_rx_reset() called immediately above already does this. Remove.
Signed-off-by: Peter Crosthwaite <peter.crosthwa... - 09:18 pm Revision 03468633: target-arm: A64: add support for add/sub with carry
- This patch adds support for C3.5.3 Add/subtract (with carry):
instructions ADC, ADCS, SBC, SBCS.
Signed-off-by: Clau... - 09:18 pm Revision fc514b09: target-arm: A64: add support for conditional compare insns
- this patch adds support for C3.5.4 - C3.5.5
Conditional compare (both immediate and register)
Signed-off-by: Claudio... - 09:18 pm Revision 66759c06: target-arm: aarch64: add support for ld lit
- Adds support for Load Register (literal), both normal
and SIMD/FP forms.
Signed-off-by: Alexander Graf <agraf@suse.d... - 09:18 pm Revision 90ba562c: target-arm: Widen exclusive-access support struct fields to 64 bits
- In preparation for adding support for A64 load/store exclusive instructions,
widen the fields in the CPU state struct... - 09:18 pm Revision 2df75664: target-arm: A64: support for ld/st/cl exclusive
- This implement exclusive loads/stores for aarch64 along the lines of
arm32 and ppc implementations. The exclusive loa... - 09:18 pm Revision 749c7970: linux-user: AArch64: define TARGET_CLONE_BACKWARDS
- The AArch64 linux-user support was written before but merged after
commit 4ce6243dc621 which cleaned up the handling ... - 09:18 pm Revision e0350d0c: linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext
- Use the helpers provided for getting the correct FPSR and FPCR
values for the signal context.
Signed-off-by: Will Ne... - 09:18 pm Revision 2d123ad2: .travis.yml: Add aarch64-* targets
- Now the AArch64 targets are in mainline we can include them in our
Travis test matrix.
Signed-off-by: Alex Bennée <a... - 09:18 pm Revision 0f64fdaf: default-configs: Add config for aarch64-linux-user
- Add a config for aarch64-linux-user, thereby enabling it as
a valid target.
Signed-off-by: Peter Maydell <peter.mayd... - 09:18 pm Revision 83d210fb: target-arm: A64: Add support for dumping AArch64 VFP register state
- When dumping the current CPU state, we can also get a request
to dump the FPU state along with the CPU's integer stat... - 09:17 pm Revision b0d2b7d0: target-arm: A64: Implement minimal set of EL0-visible sysregs
- Implement an initial minimal set of EL0-visible system registers:
* NZCV
* FPCR
* FPSR
* CTR_EL0
* DCZID_EL0
Si... - 09:17 pm Revision 19917791: target-arm: Widen thread-local register state fields to 64 bits
- The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a vi... - 09:17 pm Revision e4fe830b: target-arm: Widen thread-local register state fields to 64 bits
- The common pattern for system registers in a 64-bit capable ARM
CPU is that when in AArch32 the cp15 register is a vi... - 09:17 pm Revision 60322b39: target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
- The cpregs APIs used by the decoder (get_arm_cp_reginfo() and
cp_access_ok()) currently take either a CPUARMState* or... - 09:17 pm Revision fea50522: target-arm: A64: Implement MRS/MSR/SYS/SYSL
- The AArch64 equivalent of the traditional AArch32
cp15 coprocessor registers is the set of instructions
MRS/MSR/SYS/S... - 09:05 pm Revision 3523e4bd: target-i386: Use new tcg_gen_qemu_st_* helpers
- In preference to the older helpers. Stores only in this patch.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org... - 09:05 pm Revision 3c5f4116: target-i386: Use new tcg_gen_qemu_ld_* helpers
- In preference to the older helpers. Loads only in this patch.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>... - 09:05 pm Revision 5c42a7cd: target-i386: Stop encoding DisasContext.mem_index
- Now that we don't combine mem_index with operand size info,
we don't need to encode it. Which tidies many places tha... - 09:05 pm Revision 323d1876: target-i386: Push DisasContext into load/store helpers
- Rather than add s->mem_index into a combined size+mem_index
argument, pass the context down. This will allow cleanin... - 09:05 pm Revision 03afa5f8: exec: Delay CPU_LOG_TB_CPU until we actually execute a TB
- The previous placement could result in duplicate logging while
still processing interrupts.
Reviewed-by: Peter Mayde...
01/06/2014
- 10:02 pm Revision 5433a0a8: hw: Remove assert_no_error usages
- Replace assert_no_error() usages with the error_abort system.
&error_abort is passed into API calls to signal to the ... - 10:02 pm Revision 00b81053: target-i386: Remove assert_no_error usage
- Replace an assert_no_error() usage with the error_abort system.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@... - 10:02 pm Revision 87ea75d5: qemu-option: Remove qemu_opts_create_nofail
- This is a boiler-plate _nofail variant of qemu_opts_create. Remove and
use error_abort in call sites.
null/0 argumen... - 10:02 pm Revision 59427871: qerror: Remove assert_no_error()
- This is no longer needed, and is obsoleted by error_abort. Remove.
Signed-off-by: Peter Crosthwaite <peter.crosthwai... - 10:02 pm Revision c9501142: migration: qmp_migrate(): keep working after syntax error
- If a user or QMP client enter a bad syntax for the migrate
command in QMP/HMP, then the migrate command will never su... - 10:02 pm Revision 90c3f6e0: qdev: Delete dead code
- This is unreachable code, as it's already asserted that no errors have
occurred. Delete.
Signed-off-by: Peter Crosth... - 09:01 pm Revision 5d24ee70: error: Add error_abort
- Add a special Error * that can be passed to error handling APIs to
signal that any errors are fatal and should abort ... - 08:45 pm Revision b0ed5e9f: qom: catch errors in object_property_add_child
- Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Igor M... - 08:45 pm Revision cff8b2c6: monitor: add object-add (QMP) and object_add (HMP) command
- Add two commands that are the monitor counterparts of -object. The commands
have the same Visitor-based implementati... - 08:45 pm Revision ab2d0531: monitor: add object-del (QMP) and object_del (HMP) command
- These two commands invoke the "unparent" method of Object.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Review... - 08:45 pm Revision 28ec2598: qom: fix leak for objects created with -object
- The object must be unref-ed when its variable goes out of scope.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
... - 08:45 pm Revision 513b8c74: rng: initialize file descriptor to -1
- The file descriptor is never initialized to -1, which makes rng-random
close stdin if an object is created and immedi... - 08:45 pm Revision abf23329: qemu-monitor: HMP cpu-add wrapper
- Add HMP cpu-add wrapper to allow cpu hot plugging via monitor.
Signed-off-by: Jason J. Herne <jjherne@us.ibm.com>
Re... - 08:29 pm Revision eca01d3a: vl: add missing transition debug->finish_migrate
- This fixes an abort if you invoke the "migrate" command while the
guest is being debugged.
Cc: qemu-stable@nongnu.or...
01/05/2014
- 12:15 am Revision 6e6efd61: target-arm: Pull "add one cpreg to hashtable" into its own function
- define_one_arm_cp_reg_with_opaque() has a set of nested loops which
insert a cpreg entry into the hashtable for each ... - 12:15 am Revision f5a0a5a5: target-arm: Update generic cpreg code for AArch64
- Update the generic cpreg support code to also handle AArch64:
AArch64-visible registers coexist in the same hash tabl...
01/01/2014
- 04:03 pm Revision 08fb77ed: configure: Rewrite code for help message
- In the new form most lines of the code now look like the final output:
there is no leading echo command and the lines... - 04:03 pm Revision f6f0b7d9: configure: Python tests must be done before help message
- The help message uses $python and displays its value, so that macro
should be tested and set early.
With this modifi... - 04:03 pm Revision 88e020e5: doc: Mention chardev:id in available devices for -serial
- It is possible to pre-define a character device with the -chardev option
and reference its id as serial device. The m... - 04:03 pm Revision f57d6693: pxa27x: Reduce size of keyboard matrix mapping
- The row and column values use only a very limited range (-1 ... 7),
so a byte value is sufficient.
Signed-off-by: St... - 04:03 pm Revision 52975c31: pxa27x: Add 'const' attribute to keyboard maps
- The mapping is a hardware feature, so it is relatively constant.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewe... - 04:03 pm Revision 7dbc1158: mainstone: Fix duplicate array values for key 'space'
- cgcc reported a duplicate initialisation. Mainstone includes a matrix
keyboard where two different positions map to '... - 04:03 pm Revision 5862ad0f: acpi unit-test: Remove temporary disk after test
- Signed-off-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
12/30/2013
- 11:05 pm Revision 2ba82852: mempath prefault: fix off-by-one error
- Fix off-by-one error (noticed by Andrea Arcangeli).
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: ...
12/24/2013
- 07:02 pm Revision 6780a22c: qdev: Drop misleading qbus_free() function
- Same reasoning as commit 02a5c4c97422b40034f31265e0f139f7846172a8
("qdev: Drop misleading qdev_free() function"). Th... - 07:02 pm Revision d3b0c9e9: apic: Cleanup for QOM'ification
- Do some cleanup, including:
1. Remove DO_UPCAST() for APICCommonState
2. Change DeviceState pointers from 'd' to 'dev... - 07:02 pm Revision ff6986ce: apic: QOM'ify APIC
- Convert 'init' function to QOM's 'realize' for apic, kvm/apic and
xen/xen_apic.
Signed-off-by: xiaoqiang zhao <zxq_y... - 07:02 pm Revision 494c2717: icc_bus: QOM'ify ICC
- For consistency, QOM'ify APIC's parent bus.
Signed-off-by: xiaoqiang zhao <zxq_yx_007@163.com>
Signed-off-by: Andrea... - 07:02 pm Revision f9771858: ioapic: Cleanup for QOM'ification
- Some cleanups:
* ioapic_common.c: Rename 'register_types' to 'ioapic_common_register_types'
* Replace inline 'DEVICE(... - 07:02 pm Revision db0f8888: ioapic: QOM'ify ioapic
- Convert 'init' function to QOM's 'realize' for ioapic and kvm-ioapic.
Change variable 'ioapic_no' from static to glob... - 07:02 pm Revision 11c308b1: qdev-monitor: Improve error message for -device nonexistant
- Once upon a time, the error message was:
qemu: -device nonexistant: Device "nonexistant" not found. Try -device... - 07:02 pm Revision f54c19ca: qom: Detect bad reentrance during object_class_foreach()
- We should not modify the type hash table while it is being iterated on.
Assert that it does not happen.
Signed-off-b... - 06:27 pm Revision 1b111dc1: hw: cannot_instantiate_with_device_add_yet due to pointer props
- Pointer properties can be set only by code, not by device_add. A
device with a pointer property can work with device... - 06:27 pm Revision c272758f: qdev: Document that pointer properties kill device_add
- Ask users of DEFINE_PROP_PTR() to set
cannot_instantiate_with_device_add_yet, or explain why it's not
needed.
Signed... - 06:27 pm Revision 0ab4c94c: qom: Split out object and class caches
- The object-cast and class-cast caches cannot be shared because class
caching is conditional on the target type not be... - 06:27 pm Revision 14389dbd: tests: Test QOM interface casting
- Add basic regression testing for QOM Interface usage.
Test checks casting to interface type/class for following cases... - 06:27 pm Revision b061dc41: qom: Do not register interface "types" in the type table and fix names
- There should be no need to look up nor enumerate the interface "types",
whose "classes" are really just vtables. Jus... - 06:26 pm Revision 061e84f7: qdev-monitor: Avoid device_add crashing on non-device driver name
- Watch this:
$ upstream-qemu -nodefaults -S -display none -monitor stdio
QEMU 1.7.50 monitor - type 'help' fo... - 02:47 pm Revision 258f5abe: target-i386: Cleanup 'foo' feature handling
- Features check, enforce, hv_relaxed and hv_vapic are treated as boolean
set to 'on' when passed from command line, so... - 02:47 pm Revision d024d209: target-i386: Cleanup 'foo=val' feature handling
- Features family, model, stepping, level, hv_spinlocks are treated similarly
when passed from command line, so it's no... - 02:47 pm Revision 912ffc47: target-i386: Convert 'check' and 'enforce' to static properties
- * Additionally convert check_cpuid & enforce_cpuid to bool and make them
members of X86CPU
* Make 'enforce' feature... - 01:30 pm Revision 0f46685d: target-i386: Convert 'hv_vapic' to static property
- Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de> - 01:30 pm Revision 89314504: target-i386: Convert 'hv_relaxed' to static property
- Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de> - 01:30 pm Revision c8f0f88e: target-i386: Convert 'hv_spinlocks' to static property
- Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Andreas Färber <afaerber@suse.de> - 01:29 pm Revision 693fa551: cpu-exec: Optimize X86CPU usage in cpu_exec()
- Replace growing numbers of inline x86_env_get_cpu() with x86_cpu variable.
Reviewed-by: Chen Fan <chen.fan@cn.fujits... - 01:27 am Revision ce5458e8: target-arm: A64: implement FMOV
- Implement FMOV, ie non-converting moves between general purpose
registers and floating point registers. This is a sub... - 01:27 am Revision 52c8b9af: target-arm: A64: add support for 3 src data proc insns
- This patch adds emulation for the "Data-processing (3 source)"
family of instructions, namely MADD, MSUB, SMADDL, SMS... - 01:27 am Revision faa0ba46: target-arm: A64: Add decoder skeleton for FP instructions
- Add a top level decoder skeleton for FP instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Review... - 01:27 am Revision 9618e809: target-arm: A64: implement SVC, BRK
- Add decoding for the exception generating instructions, and implement
SVC (syscalls) and BRK (software breakpoint).
... - 01:27 am Revision 229b7a05: target-arm: A64: add support for ld/st with reg offset
- This adds support for the load/store forms using a register offset.
Signed-off-by: Alex Bennée <alex.bennee@linaro.o... - 01:27 am Revision a5e94a9d: target-arm: A64: add support for ld/st with index
- This adds support for the pre/post-index ld/st forms with immediate
offsets as well as the un-scaled immediate form (... - 01:27 am Revision b0ff21b4: target-arm: A64: add support for add, addi, sub, subi
- Implement the non-carry forms of addition and subtraction
(immediate, extended register and shifted register).
This i... - 01:27 am Revision ed6ec679: target-arm: A64: add support for move wide instructions
- This patch adds emulation for the mov wide instructions
(MOVN, MOVZ, MOVK).
Signed-off-by: Alex Bennée <alex.bennee@... - 01:27 am Revision 4a08d475: target-arm: A64: add support for ld/st pair
- This patch support the basic load and store pair instructions and
includes the generic helper functions:
* do_gpr_... - 01:27 am Revision d5612f10: target-arm: A64: add support for ld/st unsigned imm
- This adds support for the forms of ld/st with a 12 bit
unsigned immediate offset.
Signed-off-by: Alex Bennée <alex.b...
12/23/2013
- 06:02 pm Revision ddaaefb4: piix: fix 32bit pci hole
- Make the 32bit pci hole start at end of ram, so all possible address
space is covered.
We used to try and make addre... - 06:02 pm Revision 83d07047: virtio: add back call to virtio_bus_device_unplugged
- This got lost in a rebase.
Reported-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini... - 06:02 pm Revision 5bf58abf: target-arm: fix build with gcc 4.8.2
- commit 5ce4f35781028ce1aee3341e6002f925fdc7aaf3
"target-arm: A64: add set_pc cpu method"
introduces an array aar... - 05:30 pm Revision 02e51483: target-i386: Move apic_state field from CPUX86State to X86CPU
- This motion is preparing for refactoring vCPU APIC subsequently.
Signed-off-by: Chen Fan <chen.fan.fnst@cn.fujitsu.c... - 04:32 pm Revision eb2535f4: cputlb: Tidy memset() of arrays
- Don't duplicate the array length computation in the memset()
when plain sizeof() can produce the correct results.
Si... - 04:31 pm Revision 4fadb3bb: cputlb: Use memset() when flushing entries
- The size of tlb_table is 4k on a 64-bit host. For overwriting
memory at this size, cacheline tricks can help.
Signe... - 02:02 pm Revision e5187b56: fix -boot strict regressed in commit 6ef4716
- Commit 6ef4716 cleaned up parsing of -boot option argument, but
accidentally dropped parameter strict. It should hav... - 02:02 pm Revision 0d9e61c2: linux-user: Use macro TARGET_NSIG_WORDS where possible
- This improves readability and simplifies the code.
Cc: Riku Voipio <riku.voipio@iki.fi>
Signed-off-by: Stefan Weil <... - 02:02 pm Revision 6f2bfda3: vl: make boot_strict variable static (not used outside vl.c)
- Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Amos Kong <akong@redhat.com> - 02:02 pm Revision 33dfdb56: x86: only allow real mode to access 32bit without LMA
- When we're running in non-64bit mode with qemu-system-x86_64 we can
still end up with virtual addresses that are abov... - 02:02 pm Revision c46b07f0: exynos4210: Use macro ARRAY_SIZE where possible
- This improves readability and simplifies the code.
Cc: Dmitry Solodkiy <d.solodkiy@samsung.com>
Cc: Evgeny Voevodin ... - 02:02 pm Revision 2e0fc3a4: openrisc: Fix spelling in comment (transaltion -> translation)
- I also removed two hyphens in the same comment.
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Jia Liu <pr... - 02:02 pm Revision dff7424d: misc: Use macro ARRAY_SIZE where possible
- This improves readability and simplifies the code.
Cc: Anthony Liguori <aliguori@amazon.com>
Cc: Gerd Hoffmann <krax... - 02:02 pm Revision 5d70192b: ui/cocoa: Use macro ARRAY_SIZE where possible
- This improves readability and simplifies the code.
Cc: Andreas Färber <andreas.faerber@web.de>
Cc: Anthony Liguori <... - 02:02 pm Revision 112f2ac9: hw/arm/highbank: Simplify code (memory region in device state)
- The memory region can be included by value instead of by reference in the
device state.
Signed-off-by: Stefan Weil <... - 01:12 pm Revision c1a1af87: ACPI: Q35 DSDT: fix CPU hotplug GPE0.2 handler
- Fix bogus CPU hotplug GPE handler.
Make Q35 CPU hotplug GPE handler match PIIX4 one, since
CPU hotplug event is trigg... - 01:12 pm Revision aef52ee8: ACPI/DSDT-CPU: cleanup bogus comment
- Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com> - 01:12 pm Revision 81e3e75b: pci: do not export pci_bus_reset
- qbus_reset_all can be used instead. There is no semantic change
because pcibus_reset returns 1 and takes care of the... - 01:12 pm Revision 9bdbbfc3: pci: clean up resetting of IRQs
- pci_device_reset will deassert the INTX pins, and this will make the
irq_count array all-zeroes. Check that this is ... - 01:12 pm Revision 0293214b: qdev: allow both pre- and post-order vists in qdev walking functions
- Resetting should be done in post-order, not pre-order. However,
qdev_walk_children and qbus_walk_children do not all... - 01:12 pm Revision dcc20931: qdev: switch reset to post-order
- Post-order is the only sensible direction for the reset signals.
For example, suppose pre-order is used and the paren... - 01:12 pm Revision bb43d383: piix: gigabyte alignment for ram
- Map 3G (i440fx) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.
Keep old memory layout... - 01:12 pm Revision ecdbfceb: pc_piix: document gigabyte_align
- Document the logic behind the below/above 4G split.
Signed-off-by: Michael S. Tsirkin <mst@redhat.com> - 01:12 pm Revision 637a5acb: hw/i386/pc_sysfw: support two flash drives
- This patch allows the user to usefully specify
-drive file=img_1,if=pflash,format=raw,readonly \
-drive file=img... - 01:12 pm Revision b817e3fb: i440fx-test: qtest_start() should be paired with qtest_end()
- Similarly to commit 1d9358e6
("libqtest: New qtest_end() to go with qtest_start()").
Signed-off-by: Laszlo Ersek <le... - 01:12 pm Revision c37805b6: i440fx-test: give each GTest case its own qtest
- The current two GTest cases, /i440fx/defaults and /i440fx/pam can share a
qemu process, but the next two cases will n... - 01:12 pm Revision 27d59ccd: i440fx-test: generate temporary firmware blob
- The blob is 64K in size and contains 0x00..0xFF repeatedly.
The client code added to main() wouldn't make much sense... - 01:12 pm Revision 3bcc77ae: i440fx-test: verify firmware under 4G and 1M, both -bios and -pflash
- Check whether the firmware is not hidden by other memory regions.
Qemu is started in paused mode: it shouldn't try t... - 01:12 pm Revision e4f308bb: acpi: piix4: remove not needed GPE0 mask
- Hardcoded GPE0 mask isn't really needed. Since GPE0_STS initialized
with all bits cleared and only QEMU itself can se... - 01:12 pm Revision 2c047956: acpi: ich9: allow guest to clear SCI rised by GPE
- it fixes IRQ storm since guest isn't able to lower SCI IRQ
after it has been handled when it clears GPE event.
Signe... - 01:12 pm Revision 06313503: acpi: factor out common pm_update_sci() into acpi core
- ... and rename it into acpi_update_sci() since it changes
SCI on only on PM registers status.
Signed-off-by: Igor Ma... - 01:27 am Revision 7ea5e78f: qdev: Do not let the user try to device_add when it cannot work
- Such devices have always been unavailable and omitted from the list of
available devices shown by device_add help. U... - 01:27 am Revision 08c58f92: pci-host: Consistently set cannot_instantiate_with_device_add_yet
- Many PCI host bridges consist of a sysbus device and a PCI device.
You need both for the thing to work. Arguably, th... - 01:27 am Revision bfa6dfd0: ich9: Document why cannot_instantiate_with_device_add_yet
- An ICH9 southbridge contains several PCI devices, some of them with
multiple functions. We model each function as a ... - 01:27 am Revision 81aab2ff: piix3 piix4: Clean up use of cannot_instantiate_with_device_add_yet
- A PIIX3/PIIX4 southbridge has multiple functions. We model each
function as a separate qdev. Two of them need some ... - 01:27 am Revision 04916ee9: vt82c686: Clean up use of cannot_instantiate_with_device_add_yet
- A VT82C686B southbridge has multiple functions. We model each
function as a separate qdev. One of them need some sp... - 01:27 am Revision f3b17640: isa: Clean up use of cannot_instantiate_with_device_add_yet
- Drop it when there's no obvious reason why device_add could not work.
Else keep and document why.
* isa-fdc: drop
*... - 01:27 am Revision f37a4374: apic: Document why cannot_instantiate_with_device_add_yet
- Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off... - 01:27 am Revision efec3dd6: qdev: Replace no_user by cannot_instantiate_with_device_add_yet
- In an ideal world, machines can be built by wiring devices together
with configuration, not code. Unfortunately, tha... - 01:27 am Revision 837d3716: sysbus: Set cannot_instantiate_with_device_add_yet
- device_add plugs devices into suitable bus. For "real" buses, that
actually connects the device. For sysbus, the co... - 01:27 am Revision ffa95714: cpu: Document why cannot_instantiate_with_device_add_yet
- Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off...
12/22/2013
- 08:15 pm Revision f976b09e: PPC: Fix compilation with TCG debug
- The recent VSX patches broken compilation of QEMU when configurated
with --enable-debug, as it was treating "target l... - 03:59 pm Revision 8a1bd297: scsi-disk: add UNMAP limits to block limits VPD page
- Linux prefers WRITE SAME to UNMAP if the limits are zero, and WRITE
SAME does not discard anything unless the device ...
12/21/2013
- 05:46 pm Revision e8092f7a: Merge tag 'signed-s390-for-upstream' of git://github.com/agraf/qemu
- Patch queue for s390 - 2013-12-18
This covers mostly minor bug fixes and implements the SIGP START
hypercall which a... - 05:42 pm Revision 3376f415: target-sh4: Use new qemu_ld/st opcodes
- Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> - 05:42 pm Revision 5f68f5ae: target-mips: Use new qemu_ld/st opcodes
- Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> - 05:41 pm Revision 8589467f: tcg/i386: fix a comment
- The comments apply to 8-bit stores, not 8-byte stores.
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-b...
12/20/2013
- 08:38 pm Revision 2a13f991: seccomp: exit if seccomp_init() fails
- This fixes a bug where we weren't exiting if seccomp_init() failed.
Signed-off-by: Corey Bryant <coreyb@linux.vnet.i... - 05:26 pm Revision f95c625c: mirror: Don't close target
- Let reference count manage target and don't call bdrv_close here.
Signed-off-by: Fam Zheng <famz@redhat.com>
Reviewe... - 05:26 pm Revision 5bc361b8: mirror: Move base to MirrorBlockJob
- This allows setting the base before entering mirror_run, commit will
make use of it.
Signed-off-by: Fam Zheng <famz@... - 05:26 pm Revision 03544a6e: block: Add commit_active_start()
- commit_active_start is implemented in block/mirror.c, It will create a
job with "commit" type and designated base in ... - 05:26 pm Revision 20a63d2c: commit: Support commit active layer
- If active is top, it will be mirrored to base, (with block/mirror.c
code), then the image is switched when user compl... - 05:26 pm Revision 4de43470: qemu-iotests: Update test cases for commit active
- Factor out commit test common logic into super class, and update test
of committing the active image.
Signed-off-by:... - 05:26 pm Revision 18da7f94: commit: Remove unused check
- We support top == active for commit now, remove the check and add an
assertion here.
Signed-off-by: Fam Zheng <famz@... - 02:57 pm Revision de99c417: qemu-iotests: drop duplicate virtio-blk initialization failure
- Commit 75884afd5c6c42e523b08565e289dbe319e17ad9 ("virtio-blk: Convert to
QOM realize") dropped a duplicate error_repo... - 02:56 pm Revision 917703c1: vmdk: Allow vmdk_create to work with protocol
- This improves vmdk_create to use bdrv_* functions to replace qemu_open
and other fd functions. The error handling are... - 10:11 am Revision b47053bd: vmdk: Check VMFS extent line field number
- VMFS extent line in description file should be with 4 fields:
RW <size> VMFS "file-name.vmdk"
Check the number ... - 10:11 am Revision 7e30e6a6: block: vhdx - improve error message, and .bdrv_check implementation
- If there is a dirty log file to be replayed in a VHDX image, it is
replayed in .vhdx_open(). However, if the file is... - 10:11 am Revision 8282db1b: docs: updated qemu-img man page and qemu-doc to reflect VHDX support.
- The man page for qemu-img, and the qemu-doc, did not mention VHDX
as a supported format. This adds in reference to V... - 10:11 am Revision 219c2521: block/iscsi: Fix compilation for libiscsi 1.4.0 (API change)
- Function iscsi_read10_task got additional parameters starting with version
libiscsi 1.5.0.
libiscsi 1.4.0 is still w... - 10:11 am Revision c27de2a3: qapi-schema: fix QEMU 1.8 references
- We are moving boldly on to QEMU 2.0 in the next release. Some patches
written at a time where we assumed 1.8 would b... - 10:11 am Revision 4d684832: vring: create a common function to parse descriptors
- Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> - 10:11 am Revision 781c117f: vring: factor common code for error exits
- Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> - 10:11 am Revision 8c1b566f: dataplane: change vring API to use VirtQueueElement
- Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> - 10:11 am Revision 87b7f2f8: dataplane: replace hostmem with memory_region_find
- Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com> - 10:11 am Revision e50d7607: sheepdog: fix dynamic grow for running qcow2 format
- When running qcow2 over sheepdog, we might meet following problem
qemu-system-x86_64: shrinking is not supported
... - 03:03 am Revision f8251db1: Merge remote-tracking branch 'agraf/tags/signed-ppc-for-upstream' into staging
- Patch queue for ppc - 2013-12-20
Alexander Graf (3):
PPC: Use default pci bus name for grackle and heathrow
... - 02:58 am Revision 5fe269b1: spapr: limit numa memory regions by ram size
- This makes sure that all NUMA memory blocks reside within RAM or
have zero length.
Reviewed-by: Thomas Huth <thuth@l... - 02:58 am Revision c4177479: spapr: make sure RMA is in first mode of first memory node
- The SPAPR specification says that the RMA starts at the LPAR's logical
address 0 and is the first logical memory bloc... - 02:58 am Revision be5907f2: device_tree: qemu_fdt_setprop: Rename val_array arg
- Looking at the implementation, this doesn't really have a lot to do
with arrays. Its just a pointer to a buffer and i... - 02:58 am Revision 5a4348d1: device_tree: s/qemu_devtree/qemu_fdt globally
- The qemu_devtree API is a wrapper around the fdt_ set of APIs.
Rename accordingly.
Signed-off-by: Peter Crosthwaite ... - 02:58 am Revision c2b63f03: PPC: Add VSX to hflags
- We generate different code depending on whether MSR_VSX is set or
clear, so it needs to be part of our hflags too whi... - 02:58 am Revision acc42968: Add xxsldwi
- This patch adds the VSX Shift Left Double by Word Immediate
(xxsldwi) instruction.
Signed-off-by: Tom Musta <tommust... - 02:58 am Revision 76c15fe0: Add xxspltw
- This patch adds the VSX Splat Word (xxsplatw) instruction.
This is the first instruction to use the UIM immediate fi... - 02:58 am Revision 551e3ef7: Add xxsel
- This patch adds the VSX Select (xxsel) instruction.
The xxsel instruction has four VSR operands. Thus the xC
instru... - 02:58 am Revision 79ca8a6a: Add Power7 VSX Logical Instructions
- This patch adds the VSX logical instructions that are defined
by the Version 2.06 Power ISA (aka Power7):
- xxlan... - 02:58 am Revision ce577d2e: Add xxmrgh/xxmrgl
- This patch adds the VSX Merge High Word and VSX Merge Low Word
instructions.
V2: Now implemented using deposit (per ... - 02:58 am Revision be574920: Add VSX Vector Move Instructions
- This patch adds the vector move instructions:
- xvabsdp - Vector Absolute Value Double-Precision
- xvnabsdp - Ve... - 02:58 am Revision df020ce0: Add VSX Scalar Move Instructions
- This patch adds the VSX scalar move instructions:
- xsabsdp (Scalar Absolute Value Double-Precision)
- xsnabspd ... - 02:58 am Revision 582b55a9: roms: Flush icache when writing roms to guest memory
- We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basica... - 02:58 am Revision 3978b863: spapr: tie spapr-nvram to -pflash
- spapr-nvram's drive property is currently connected to a non-existent
"-machine nvram=<drivename>" option. Instead, ... - 02:58 am Revision 8a0e1104: PPC: Use default pci bus name for grackle and heathrow
- There's no good reason to call our bus "pci" rather than let the default
bus name take over ("pci.0").
The big downs... - 02:57 am Revision a64d325d: spapr-rtas: replace return code constants with macros
- Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Alexander Graf <agraf@suse.de> - 02:57 am Revision 3ada6b11: spapr-rtas: add ibm, (get|set)-system-parameter
- This adds very basic handlers for ibm,get-system-parameter and
ibm,set-system-parameter RTAS calls.
The only paramet... - 02:57 am Revision b650d6a2: target-ppc: move POWER7+ to a separate family
- So far POWER7+ was a part of POWER7 family. However it has a different
PVR base value so in order to support PVR mask... - 02:57 am Revision 86e61ce3: Add stxvw4x
- This patch adds the Store VSX Vector Word*4 Indexed (stxvw4x)
instruction.
Signed-off-by: Tom Musta <tommusta@gmail.... - 02:57 am Revision 9231ba9e: Add stxsdx
- This patch adds the Store VSX Scalar Doubleword Indexed (stxsdx)
instruction.
Signed-off-by: Tom Musta <tommusta@gma... - 02:57 am Revision 897e61d1: Add lxvw4x
- This patch adds the Load VSX Vector Word*4 Indexed (lxvw4x)
instruction.
V2: changed to use deposit_i64 per Richard ... - 02:57 am Revision ca03b467: Add lxvdsx
- This patch adds the Load VSX Vector Doubleword & Splat Indexed
(lxvdsx) instruction.
Signed-off-by: Tom Musta <tommu... - 02:57 am Revision fa1832d7: Add lxsdx
- This patch adds the Load VSX Scalar Doubleowrd Indexed (lxsdx)
instruction.
The lower 8 bytes of the target register... - 02:57 am Revision cd73f2c9: Add xxpermdi
- This patch adds the xxpermdi instruction. The instruction
uses bits 22, 23, 29 and 30 for non-opcode fields (DM, AX
... - 02:57 am Revision fbed2478: Add stxvd2x
- This patch adds the stxvd2x instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchar... - 02:57 am Revision 304af367: Add lxvd2x
- This patch adds the lxvd2x instruction.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Anton Blanchard... - 02:57 am Revision 472b24ce: Add VSR to Global Registers
- This patch adds VSX VSRs to the the list of global register indices.
More specifically, it adds the lower halves of t... - 02:57 am Revision f9fc6d81: Add VSX Instruction Decoders
- This patch adds decoders for the VSX fields XT, XS, XA, XB and
DM. The first four are split fields and a general hel... - 02:57 am Revision 1f29871c: Add MSR VSX and Associated Exception
- This patch adds support for the VSX bit of the PowerPC Machine
State Register (MSR) as well as the corresponding VSX ... - 02:57 am Revision 74f23997: Declare and Enable VSX
- This patch adds the flag POWERPC_FLAG_VSX to the list of defined
flags and also adds this flag to the list of support... - 02:57 am Revision 3bc9ccc0: powerpc: add PVR mask support
- IBM POWERPC processors encode PVR as a CPU family in higher 16 bits and
a CPU version in lower 16 bits. Since there i... - 02:57 am Revision c65f9a07: target-ppc: add stubs for KVM breakpoints
- The latest update to v3.13-rc3 (bf63839f) breaks the
ppc build with KVM:
kvm-all.o: In function `kvm_update_guest_de...
12/19/2013
- 09:56 pm Revision 3dc7e2a3: Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131217' into sta...
- target-arm queue:
* AES instruction support for 32 bit ARM
* pflash01: much better emulation of 2x16bit and similar...
12/18/2013
- 03:24 pm Revision 10c8599a: s390x/ioinst: CHSC has to set a condition code
- I missed to set the CC in the CHSC instruction when I refactored
the CC setting in the IO instructions with the follo... - 03:24 pm Revision 638129ff: s390x/kvm: Fix diagnose handling.
- The instruction intercept handler for diagnose used only the displacement
when trying to calculate the function code.... - 03:24 pm Revision 4f91e0b5: s390x/kvm: Removed duplicated SIGP defines
- The SIGP order defines are also available in cpu.h,
so there is no need to re-define them in kvm.c.
Signed-off-by: T... - 03:24 pm Revision cd7a0f4c: s390x/kvm: Removed s390_store_status stub
- The SIGP order STORE STATUS AT ADDRESS will be handled in
kernel space, so we do not need the stub in QEMU anymore.
... - 03:24 pm Revision 3796f0e1: s390x/kvm: Fixed condition code for unknown SIGP orders
- If SIGP is called with an unknown order code, it has to return CC1
instead of CC3 and set the "invalid order" bit in ... - 03:24 pm Revision b20a461f: s390x/kvm: Implemented SIGP START
- This patch adds the missing START order to the SIGP instruction handler.
Signed-off-by: Thomas Huth <thuth@linux.vne... - 03:24 pm Revision b8031adb: s390x/kvm: Simplified the calculation of the SIGP order code
- We've already got a helper function for calculating the
base/displacement of RS formatted instructions, so we can
get... - 03:24 pm Revision 0b9972a2: s390x/kvm: Fix coding style in handle_sigp()
- To make scripts/checkpatch.pl happy for the following patches,
the coding style in handle_sigp() has to be fixed firs... - 11:13 am Revision 6bdf863d: kvm: x86: Separately write feature control MSR on reset
- If the guest is running in nested mode on system reset, clearing the
feature MSR signals the kernel to leave this mod...
12/17/2013
- 10:12 pm Revision e801de93: target-arm: A64: add support for EXTR
- This patch adds emulation support for the EXTR instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio:... - 10:12 pm Revision 8220e911: target-arm: A64: add support for 2-src data processing and DIV
- This patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.
Signed-off-by:... - 10:12 pm Revision 6c1adc91: target-arm: A64: add support for 2-src shift reg insns
- This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV
Sign... - 10:12 pm Revision 680ead21: target-arm: A64: add support for 1-src data processing and CLZ
- This patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ (count leading zero... - 10:12 pm Revision 82e14b02: target-arm: A64: add support for 1-src RBIT insn
- This adds support for the C5.6.147 RBIT instruction.
Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted... - 10:12 pm Revision 45323209: target-arm: A64: add support for 1-src REV insns
- This adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.
Signed-off-by: Claudio Fontana <claudio.fontana@... - 10:12 pm Revision 88077742: target-arm: A64: add support for bitfield insns
- This patch implements the C3.4.2 Bitfield instructions:
SBFM, BFM, UBFM.
Signed-off-by: Claudio Fontana <claudio.fon... - 10:12 pm Revision afd3fe4c: host-utils: add clrsb32/64 - count leading redundant sign bits
- this patch introduces wrappers for the clrsb builtins,
which count the leading redundant sign bits.
Signed-off-by: C... - 10:12 pm Revision e80c5020: target-arm: A64: add support for 1-src CLS insn
- this patch adds support for the CLS instruction.
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-... - 10:12 pm Revision 71b46089: target-arm: A64: add support for logical (immediate) insns
- This patch adds support for C3.4.4 Logical (immediate),
which include AND, ANDS, ORR, EOR.
Signed-off-by: Alexander ... - 10:12 pm Revision c6f09eb4: hw/arm: add very initial support for Canon DIGIC SoC
- DIGIC is Canon Inc.'s name for a family of SoC
for digital cameras and camcorders.
There is no publicly available sp... - 10:12 pm Revision d91fd756: hw/arm/digic: prepare DIGIC-based boards support
- Also this patch adds initial support for Canon
PowerShot A1100 IS compact camera.
Signed-off-by: Antony Pavlov <anto... - 10:12 pm Revision 576e99cb: hw/arm/digic: add timer support
- Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
... - 10:12 pm Revision 142593c9: hw/arm/digic: add UART support
- Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed... - 10:12 pm Revision 04234a37: hw/arm/digic: add NOR ROM support
- Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Message-id: 1387188908-754-6-git-send-email-antonynpavlov@gmai... - 10:12 pm Revision 9082f121: MAINTAINERS: Document 'Canon DIGIC' machine
- Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Message-id: 1387188908-754-7-git-send-email-antonynpavlov@gmai... - 10:12 pm Revision a1f05e79: vmstate: Add support for an array of ptimer_state *
- Add support for defining a vmstate field which is an array
of pointers to structures, and use this to define a
VMSTAT... - 10:12 pm Revision 3589de8c: hw/timer: add allwinner a10 timer
- Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Messag... - 10:12 pm Revision c3931ee8: hw/intc: add allwinner A10 interrupt controller
- Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Review... - 10:12 pm Revision 9158fa54: hw/arm: add allwinner a10 SoC support
- Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Messag... - 10:12 pm Revision a01c0053: hw/arm: add cubieboard support
- Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Messag... - 10:12 pm Revision 84291fe7: MAINTAINERS: add myself to maintain allwinner-a10
- Signed-off-by: liguang <lig.fnst@cn.fujitsu.com>
Message-id: 1387159292-10436-7-git-send-email-lig.fnst@cn.fujitsu.co... - 09:42 pm Revision 832ffa1c: target-arm: A64: add support for logical (shifted register)
- Add support for the instructions described in "C3.5.10 Logical
(shifted register)".
We store the flags in the same l... - 09:42 pm Revision 15bfe8b6: target-arm: A64: add support for ADR and ADRP
- Add support for the instructions described in
"C3.4.6 PC-rel. addressing" (ADR and ADRP).
Signed-off-by: Alexander G... - 09:42 pm Revision b001c8c3: target-arm: A64: add support for BR, BLR and RET insns
- Implement BR, BLR and RET. This is all of the 'unconditional
branch (register)' instruction category except for ERET
... - 09:42 pm Revision 39fb730a: target-arm: A64: add support for conditional branches
- This patch adds emulation for the conditional branch (b.cond) instruction.
Signed-off-by: Alexander Graf <agraf@suse... - 09:42 pm Revision db0f7958: target-arm: A64: add support for 'test and branch' imm
- This patch adds emulation for the test and branch insns,
TBZ and TBNZ.
Signed-off-by: Alexander Graf <agraf@suse.de>... - 09:42 pm Revision 60e53388: target-arm: A64: add support for compare and branch imm
- This patch adds emulation for the compare and branch insns,
CBZ and CBNZ.
Signed-off-by: Alexander Graf <agraf@suse.... - 09:42 pm Revision e952d8c7: target-arm: A64: add support for conditional select
- This patch adds support for the instruction group "C3.5.6
Conditional select": CSEL, CSINC, CSINV, CSNEG.
Signed-off... - 09:42 pm Revision 6a669427: target-arm: Support fp registers in gdb stub
- Register the aarch64-fpu XML and implement the necessary
read/write handlers so we can support reading and writing
of... - 09:42 pm Revision d3e35a1f: target-arm: A64: add stubs for a64 specific helpers
- We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with the... - 09:42 pm Revision ad7ee8a2: target-arm: A64: provide skeleton for a64 insn decoding
- Provide a skeleton for a64 instruction decoding in translate-a64.c,
by dividing instructions into the classes defined... - 09:42 pm Revision 87462e0f: target-arm: A64: expand decoding skeleton for system instructions
- Decode the various kinds of system instructions:
hints (HINT), which include NOP, YIELD, WFE, WFI, SEV, SEL
sync in... - 09:42 pm Revision 11e169de: target-arm: A64: add support for B and BL insns
- Implement the B and BL instructions (PC relative branches and calls).
For convenience in managing TCG temporaries wh... - 09:42 pm Revision 013424d4: default-configs: Add config for aarch64-softmmu
- Add a config for aarch64-softmmu; this enables building of this target.
The resulting executable doesn't know about a... - 09:42 pm Revision 40f860cd: target-arm: Split A64 from A32/T32 gen_intermediate_code_internal()
- The A32/T32 gen_intermediate_code_internal() is complicated because it
has to deal with:
* conditionally executed in... - 09:42 pm Revision 5ce4f357: target-arm: A64: add set_pc cpu method
- When executing translation blocks we need to be able to recover
our program counter. Add a method to set it for AArch... - 09:42 pm Revision f903fa22: target-arm: A64: provide functions for accessing FPCR and FPSR
- The information which AArch32 holds in the FPSCR is split for
AArch64 into two logically distinct registers, FPSR and... - 09:42 pm Revision d356312f: target-arm: Clean up handling of AArch64 PSTATE
- The env->pstate field is a little odd since it doesn't strictly
speaking represent an architectural register. However... - 09:42 pm Revision 26861c7c: target-arm: Add minimal KVM AArch64 support
- Add the bare minimum set of functions needed for control of an
AArch64 KVM vcpu:
* CPU initialization
* minimal get... - 09:42 pm Revision 70a5f682: configure: Enable KVM for aarch64 host/target combination
- Enable KVM if the host and target CPU are both aarch64. Note
that host aarch64 + target arm is not valid for KVM acce... - 09:42 pm Revision 47b1da81: hw/arm/boot: Allow easier swapping in of different loader code
- For AArch64 we will obviously require a different set of
primary and secondary boot loader code fragments. However cu... - 09:42 pm Revision 4d9ebf75: hw/arm/boot: Add boot support for AArch64 processor
- This commit adds support for booting a single AArch64 CPU by setting
appropriate registers. The bootloader includes p... - 09:42 pm Revision c2577128: arm/xilinx_zynq: Implement CBAR initialisation
- Fix the CBAR initialisation by using the newly defined static property.
Zynq will now correctly init the CBAR to the ... - 09:42 pm Revision e2cddeeb: arm/highbank.c: Fix MPCore periphbase name
- GIC_BASE_ADDR is not the base address of the GIC. Its clear from the
code that this is the base address of the MPCore... - 09:42 pm Revision 68e0a40a: ARM: cpu: add "reset_hivecs" property
- Add an ARM CPU property for the reset value of hivecs as it is a
board/SoC configurable setting.
The existence of th... - 09:42 pm Revision 387f9806: ARM: arm_cpu_reset: make it possible to use high vectors for reset_exc
- If hivecs are being used on reset, the CPU should come out of reset at
the hivecs reset vector (0xFFFF0000)
Signed-o... - 09:42 pm Revision b197ebd4: target-arm/kvm: Split 32 bit only code into its own file
- Split ARM KVM support code which is 32 bit specific out into its
own file, which we only compile on 32 bit hosts. Thi... - 09:42 pm Revision d8ba780b: target-arm: Define and use ARM_FEATURE_CBAR
- Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendo... - 09:42 pm Revision 07a5b0d2: target-arm/cpu: Convert reset CBAR to a property
- The reset value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a... - 09:42 pm Revision f282f296: arm/highbank: Use object_new() rather than cpu_arm_init()
- To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite <peter.... - 09:42 pm Revision c0f1ead9: arm/highbank: Fix CBAR initialisation
- Fix the CBAR initialisation by using the newly defined static property.
CBAR is now set before realization, so the in... - 09:42 pm Revision d8bbdcf8: arm/xilinx_zynq: Use object_new() rather than cpu_arm_init()
- To allow the machine model to set device properties before CPU
realization.
Signed-off-by: Peter Crosthwaite <peter.... - 09:42 pm Revision fa21a7b1: Add max device width parameter for NOR devices
- For handling CFI and device ID reads, we need to not only know the
width that a NOR flash device is configured for, b... - 09:42 pm Revision 4433e660: Fix CFI query responses for NOR flash
- This change fixes the CFI query responses to handle NOR device
widths that are different from the bank width. Suppor... - 09:42 pm Revision 0163a2dc: Fix NOR flash device ID reading
- Fix NOR flash manufacturer and device ID reading. This now
properly takes into account device widths and device max ... - 09:42 pm Revision 3671cd87: target-arm/helper.c: Allow cp15.c15 dummy override
- The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overri... - 09:42 pm Revision 4b6fedca: rename pflash_t member width to bank_width
- Rename the 'width' member of the pflash_t structure
in preparation for adding a bank_width member.
Signed-off-by: Ro... - 09:42 pm Revision 1997b485: Add device-width property to pflash_cfi01
- The width of the devices that make up the flash interface
is required to mask certain commands, in particular the
wri... - 09:42 pm Revision 2003889f: return status for each NOR flash device
- Now that we know how wide each flash device that makes up the bank is,
return status for each device in the bank. Le... - 09:42 pm Revision b8433303: Set proper device-width for vexpress flash
- Create vexpress specific pflash registration
function which properly configures the device-width
of 16 bits (2 bytes)... - 09:42 pm Revision 9d935509: target-arm: add support for v8 AES instructions
- This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch3... - 01:33 am Revision f46e720a: qemu_opts_parse(): always check return value
- qemu_opts_parse() can always return NULL, even if the QemuOptsList.desc in
question would be trivial to satisfy (eg. ...
12/16/2013
- 07:44 pm Revision b91f9324: Merge remote-tracking branch 'spice/tags/pull-spice-1' into staging
- Collection of little cleanups anf bugfixes.
nbd patches in preparation of spice-nbd.
# gpg: Signature made Mon 16 De... - 07:43 pm Revision 80d6f5ea: Merge remote-tracking branch 'kwolf/tags/for-anthony' into staging
- Block patches
# gpg: Signature made Fri 13 Dec 2013 09:47:03 AM PST using RSA key ID C88F2FD6
# gpg: Can't check sig... - 12:25 pm Revision 8b9dfe90: block/iscsi: use a bh to schedule co reentrance
- this fixes a potential segfault and performance regression.
If the coroutine is reentered directly in the iscsi_co_g... - 11:12 am Revision 2302c1ca: Split nbd block client code
- Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-o... - 11:12 am Revision 314f7ea7: qmp_change_blockdev() remove unused has_format
- Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> - 11:12 am Revision f7d48052: include: add missing config-host.h include
- Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> - 11:12 am Revision d61b0c9a: char: add qemu_chr_fe_event()
- Teach the chardev frontend to send event. This is used by the Spice port
chardev currently.
Signed-off-by: Marc-Andr... - 11:12 am Revision be733d6d: spice-char: implement chardev port event
- Wire up chardev fe_event to Spice port.
Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Signed-off-by:... - 11:12 am Revision d8a03a09: spice-char: remove unused field
- Signed-off-by: Marc-André Lureau <marcandre.lureau@gmail.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> - 11:12 am Revision 75c70e37: spice: stop server for qxl hard reset
- Hard reset can happen at any time. We should be able to put qxl into a
known-good state no matter what. Stop spice ... - 11:12 am Revision e2bc625f: nbd: pass export name as init argument
- There is no need to keep the export name around, and it seems a better
fit as an argument in the init() call.
Signed... - 11:12 am Revision 5ad283eb: nbd: make nbd_client_session_close() idempotent
- Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-o... - 11:12 am Revision 69152c09: nbd: finish any pending coroutine
- Make sure all pending coroutines are finished when closing the session.
Signed-off-by: Marc-André Lureau <marcandre.... - 11:12 am Revision b1b27b64: nbd: avoid uninitialized warnings
- ==15815== Thread 1:
==15815== Syscall param socketcall.sendto(msg) points to uninitialised byte(s)
==15815== at 0x... - 11:12 am Revision 7cc6a25f: spice: move qemu_spice_display_*() from spice-graphics to spice-core
- Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
- 11:12 am Revision b50f3e42: spice: move spice_server_vm_{start,stop} calls into qemu_spice_display_*()
- So calling spice server to start/stop the worker goes
hand in hand with the status variable update.
Signed-off-by: G... - 11:12 am Revision e53a18e4: nbd: don't change socket block during negotiate
- The caller might handle non-blocking using coroutine. Leave the choice
to the caller to use a blocking or non-blockin... - 11:12 am Revision f1d3e586: spice: flip streaming video mode to off by default
- Video streaming detection heuristics in spice-server have problems
keeping modern desktop animations (as done by gnom... - 11:12 am Revision fa88afa5: vscclient: do not add a socket watch if there is not data to send
- Fixes the following error:
** (process:780): CRITICAL **: do_socket_send: assertion
`socket_to_send->len != 0' failed...
12/13/2013
- 09:10 pm Revision e157b8fd: Merge remote-tracking branch 'bonzini/virtio' into staging
- # By Andreas Färber (18) and Paolo Bonzini (12)
# Via Paolo Bonzini
* bonzini/virtio: (30 commits)
virtio: Convert ... - 09:10 pm Revision 5d0e2280: Merge remote-tracking branch 'mst/tags/for_anthony' into staging
- acpi.pci,pc,memory core fixes
Most notably this includes changes to exec to support
full 64 bit addresses.
This als... - 09:10 pm Revision bf6e3cc4: Merge remote-tracking branch 'bonzini/scsi-next' into staging
- # By Paolo Bonzini (4) and Peter Lieven (1)
# Via Paolo Bonzini
* bonzini/scsi-next:
help: add id suboption to -isc... - 06:11 pm Revision c547e564: blkdebug: Use QLIST_FOREACH_SAFE to resume IO
- Qemu-iotest 030 was broken.
When the coroutine runs and finishes, it will remove itself from the req
list, so let's ... - 05:45 pm Revision 802c3d4c: qemu-img: make progress output more accurate during convert
- the progress output is very bumpy if the input images contains
a significant portion of unallocated sectors. This pat... - 03:49 pm Revision 3d94ce60: block: expect get_block_status errors in bdrv_make_zero
- during testing around with 4k LUNs a bad target implementation
triggert an -EIO in iscsi_get_block_status, but it got... - 03:49 pm Revision 01443e13: qapi-schema.json: Change 1.8 reference to 2.0
- Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com> - 03:49 pm Revision f671d173: block/vvfat: Fix compiler warnings for OpenBSD
- The buildbot shows these compiler warnings:
block/vvfat.c: In function 'create_short_and_long_name':
block/vvfat.c:6... - 03:49 pm Revision a3120dee: sheepdog: check if '-o redundancy' is passed from user
- This fix a segfault (that is caused by b3af018f3) of following command:
$ qemu-img convert some_img sheepdog:some_im... - 02:38 pm Revision a94b36dd: roms: Flush icache when writing roms to guest memory
- We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're basica... - 02:00 am Revision 47acdd63: target-microblaze: Use the new qemu_ld/st opcodes
- The ability of the new opcodes to byte-swap the memory operation
simplifies the code in and around dec_load and dec_s...
12/12/2013
- 02:13 pm Revision 0522604b: target-i386: clear guest TSC on reset
- VCPU TSC is not cleared by a warm reset (*), which leaves some types of Linux
guests (non-pvops guests and those wit... - 02:12 pm Revision f86746c2: target-i386: do not special case TSC writeback
- Newer kernels are capable of synchronizing TSC values of multiple VCPUs
on writeback, but we were excluding the power... - 02:10 pm Revision 79e9ebeb: target-i386: Intel MPX
- Add some MPX related definiation, and hardcode sizes and offsets
of xsave features 3 and 4. It also add corresponding...
12/11/2013
- 08:11 pm Revision 8ac2adf7: acpi unit-test: adjust the test data structure for better handling
- Ensure more then one instance of test_data may exist
at a given time. It will help to compare different
acpi table ve... - 08:11 pm Revision 142e0950: hpet: fix build with CONFIG_HPET off
- make hpet_find inline so we don't need
to build hpet.c to check if hpet is enabled.
Fixes link error with CONFIG_HPE... - 08:11 pm Revision 51116102: pc: use macro for HPET type
- avoid hard-coding strings
Signed-off-by: Michael S. Tsirkin <mst@redhat.com> - 08:11 pm Revision 7a10ef51: hpet: enable to entitle more irq pins for hpet
- Owning to some different hardware design, piix and q35 need
different compat. So making them diverge.
On q35, IRQ2/8... - 08:11 pm Revision 15650602: acpi unit-test: load and check facs table
- FACS table does not have a checksum, so we can
check at least the signature (existence).
Signed-off-by: Marcel Apfel... - 08:11 pm Revision 53cb28cb: exec: separate sections and nodes per address space
- Every address space has its own nodes and sections, but
it uses the same global arrays of nodes/section.
This limits... - 08:11 pm Revision 6307d974: memory.c: bugfix - ref counting mismatch in memory_region_find
- 'address_space_get_flatview' gets a reference to a FlatView.
If the flatview lookup fails, the code returns without
"... - 08:11 pm Revision 0d63b2dd: hpet: inverse polarity when pin above ISA_NUM_IRQS
- According to hpet spec, hpet irq is high active. But according to
ICH spec, there is inversion before the input of io... - 08:11 pm Revision 4c41425d: pci: fix pci bridge fw path
- qemu uses "pci" as name for pci bridges in the firmware device path.
seabios expects "pci-bridge". Result is that bo... - 02:14 am Revision 6747f645: Merge remote-tracking branch 'rth/tcg-temp-order' into staging
- # By Richard Henderson
# Via Richard Henderson
* rth/tcg-temp-order:
tcg: Use bitmaps for free temporaries
Message... - 02:14 am Revision b9aad5d6: Merge remote-tracking branch 'stefanha/net-next' into staging
- # By Vincenzo Maffione (2) and others
# Via Stefan Hajnoczi
* stefanha/net-next:
net: Update netdev peer on link ch... - 02:13 am Revision 1ead3ed5: Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20131210' into sta...
- target-arm queue:
* support REFCNT register on integrator/cp board
* implement the A9MP's global timer
* add the '... - 02:11 am Revision b5527dad: Merge remote-tracking branch 'kraxel/tags/pull-audio-1' into staging
- Change audio wakeup rate from 250 Hz to 100 Hz.
Emulation bugfixes for intel-hda and adlib.
# gpg: Signature made Mo... - 02:11 am Revision 75c4ce82: Merge remote-tracking branch 'alon/libcacard_ccid.4' into staging
- # By Stefan Weil
# Via Alon Levy
* alon/libcacard_ccid.4:
libcacard: Fix compilation for older versions of glib (bu... - 02:09 am Revision 45506cc2: Merge remote-tracking branch 'mjt/trivial-patches' into staging
- # By Stefan Weil
# Via Michael Tokarev
* mjt/trivial-patches:
qxl: Add missing trace.h (fix broken build)
Message-...
12/10/2013
- 07:23 pm Revision 0ec9eabc: tcg: Use bitmaps for free temporaries
- We previously allocated 32-bits per temp for the next_free_temp entry.
We now allocate 4 bits per temp across the 4 b... - 03:28 pm Revision 11785f53: net/cadence_gem: Don't assert against 0 buffer address
- This has no real hardware analog and asserting correctness of DMA
addresses is not a perhiperal level problem. Delete... - 03:28 pm Revision 7cfd65e4: net/cadence_gem: simplify rx buf descriptor walking
- There was a replication of the rx descriptor address walking logic.
Reorder the flow control to remove. This refactor... - 03:28 pm Revision 06c2fe95: net/cadence_gem: Prefetch rx descriptors ASAP
- The real hardware prefetches rx buffer descriptors ASAP and
potentially throws relevant interrupts following the fetc... - 03:28 pm Revision 63af1e0c: net/cadence_gem: Implement RX descriptor match mode flags
- The various Rx packet address matching mode flags were not being set in
the rx descriptor. Implement.
Reported-by: D... - 03:28 pm Revision a03f7429: net/cadence_gem: Implement SAR match bit in rx desc
- Bit 27 of the RX buffer desc word 1 should be set when the packet was
accepted due to specific address register match... - 03:28 pm Revision 64eb9301: net/cadence_gem: Implement SAR (de)activation
- The Specific address registers can be enabled or disabled by software.
QEMU was assuming they were always enabled. Im... - 03:28 pm Revision 17cf2c76: net/cadence_gem: Add missing VMSTATE_END_OF_LIST
- Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 8f8c2bfb15f40fb5f0d5766aa4cd3d54c596de6a.... - 03:28 pm Revision 30570698: net/cadence_gem: Fix rx multi-fragment packets
- Bytes_to_copy was being updated before its final use where it
advances the rx buffer pointer. This was causing total ... - 03:28 pm Revision 191946c5: net/cadence_gem: Fix small packet FCS stripping
- The minimum packet size is 64, however this is before FCS stripping
occurs. So when FCS stripping the minimum packet ... - 03:28 pm Revision e2314fda: net/cadence_gem: Fix register w1c logic
- This write-1-clear logic was incorrect. It was always clearing w1c
bits regardless of whether the written value was 1... - 03:28 pm Revision 3ae5725f: net/cadence_gem: Improve can_receive debug printfery
- Currently this just floods indicating that can_receive has been called
by the net framework. Instead, save the result... - 03:28 pm Revision 8202aa53: net/cadence_gem: Don't rx packets when no rx buffer available
- Return false from can_receive() when no valid buffer descriptor is
available. Ensures against mass packet droppage in... - 03:28 pm Revision 6a57f3eb: target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.
- Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and... - 03:28 pm Revision 04731fb5: target-arm: Implement ARMv8 VSEL instruction.
- This adds support for the VSEL floating point selection instruction
which was added in ARMv8.
Signed-off-by: Will Ne... - 03:28 pm Revision 74f1c6dd: target-arm: fix TTBCR write masking
- Current implementation is not accurate according to ARMv7-AR reference
manual. See "B4.1.153 TTBCR, Translation Table... - 03:28 pm Revision e17ab310: softfloat: Add minNum() and maxNum() functions to softfloat.
- Add floatnn_minnum() and floatnn_maxnum() functions which are equivalent
to the minNum() and maxNum() functions from ... - 03:28 pm Revision 40cfacdd: target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.
- This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton <will.newt... - 03:28 pm Revision 505935fc: target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.
- This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.
Signed-off-by: Will Newton <will.newto... - 03:28 pm Revision 09f78135: target-arm: Use new qemu_ld/st opcodes
- Retain the existing gen_aa32_* inlines, to aid compilation for A64.
Cc: Peter Maydell <peter.maydell@linaro.org>
Sig... - 03:28 pm Revision e70614ea: softfloat: Remove unused argument from MINMAX macro.
- The nan_exp argument is not used, so remove it.
Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Pet... - 03:28 pm Revision 3541addc: target-arm: Don't hardcode KVM target CPU to be A15
- Instead of assuming that a KVM target CPU must always be a
Cortex-A15 and hardcoding this in kvm_arch_init_vcpu(),
st... - 03:28 pm Revision a96c0514: target-arm: Provide '-cpu host' when running KVM
- Implement '-cpu host' for ARM when we're using KVM, broadly
in line with other KVM-supporting architectures.
Signed-... - 03:28 pm Revision 198aa064: hw/arm/virt: Support -cpu host
- Support -cpu host in virt machine (treating it like an A15, ie
with a GIC v2 and the A15's private peripherals.)
Sig... - 03:28 pm Revision 24e822ea: net/cadence_gem: Implement mac level loopback mode
- Cadence GEM has a MAC level loopback mode. Implement. Use the same basic
operation as the already implemented PHY loo... - 03:28 pm Revision 3b2c97f9: net/cadence_gem: Update DMA rx descriptors as we process them
- We were updating the ownership bit of all descriptors if packets
get split and written through several descriptors.
... - 03:28 pm Revision ef6de70e: device_tree.c: Terminate the empty reservemap in create_device_tree()
- Device trees created with create_device_tree() may not have any
entries in their reservemap, because the FDT API requ... - 03:28 pm Revision 0fb79851: hw/arm/boot: Allow boards to provide an fdt blob
- If no fdt is provided on command line and the new field
get_dtb in struct arm_boot_info is set then call it to
get a ... - 03:28 pm Revision f5fdcd6e: hw/arm: Add 'virt' platform
- Add 'virt' platform support corresponding to arch/arm/mach-virt
in the Linux kernel tree. This has no platform-specif... - 03:28 pm Revision 54d3e3f5: target-arm: Add ARMCPU field for Linux device-tree 'compatible' string
- Linux requires device tree CPU nodes to include a 'compatible'
string describing the CPU. Add a field in the ARMCPU s... - 03:28 pm Revision 5de16430: target-arm: Allow secondary KVM CPUs to be booted via PSCI
- New ARM boards are generally expected to boot their secondary CPUs
via the PSCI interface, rather than ad-hoc "loop a... - 03:28 pm Revision a22ec1e6: target-arm: Provide PSCI constants to generic QEMU code
- Provide versions of the KVM PSCI constants to non-KVM code;
this will allow us to avoid an ifdef in boards which set ... - 03:28 pm Revision 72b0cd35: target-arm: Provide mechanism for getting KVM constants even if not CONFIG_KVM
- There are a number of places where it would be convenient for ARM
code to have working definitions of KVM constants e... - 03:28 pm Revision 57e72f2a: cpu/a9mpcore: Add Global Timer
- Add the global timer to A9 MPCore.
Signed-off-by: François LEGAL <devel@thom.fr.eu.org>
Reviewed-by: Peter Maydell <... - 03:24 pm Revision f53977f7: integrator/cp: add support for REFCNT register
- Linux kernel from version 3.4 requires CM_REFCNT register for sched timer
for Integrator/CP board (integrator_defconf... - 03:24 pm Revision d3053e6b: cpu/a9mpcore: rename timerbusdev variable
- Rename this variable for consistency with the above defined mptimerdev
variable.
Signed-off-by: Peter Crosthwaite <p... - 03:24 pm Revision 4c25f365: cpu/a9mpcore: reorder operations/declarations
- To make it consistent for easier code reading. The order in which
variables are defined and functions are called is s... - 03:24 pm Revision c21c3b53: hw/timer: Introduce ARM A9 Global Timer.
- The ARM A9 MPCore has a timer that is global to all cores in the cluster.
The timer is shared but each core has a pri... - 01:29 pm Revision b29ad07e: smbios: Set system manufacturer, product & version by default
- Currently, we get SeaBIOS defaults: manufacturer Bochs, product Bochs,
no version. Best SeaBIOS can do, but we can p... - 01:29 pm Revision 53333801: acpi unit-test: verify signature and checksum
- Read all ACPI tables from guest - will be useful for further unit tests.
Follow pointers between ACPI tables checkin... - 01:29 pm Revision 53db092a: acpi: strip compiler info in built-in DSDT
- IASL stores it's revision in each table header it generates.
That's not nice since guests will see a change each time... - 01:29 pm Revision 6b9b4405: ACPI DSDT: Make control method `IQCR` serialized
- Forward-port the following commit from seabios:
commit 995bbeef78b338370f426bf8d0399038c3fa259c
Author: Paul Menzel ... - 12:29 pm Revision d4fce24f: qtest: split configuration of qtest accelerator and chardev
- qtest uses the icount infrastructure to implement a test-driven vm_clock. This
however is not necessary when using -... - 12:29 pm Revision 83d08f26: pc: map PCI address space as catchall region for not mapped addresses
- With a help of negative memory region priority PCI address space
is mapped underneath RAM regions effectively catchin... - 12:29 pm Revision e689f7c6: hw: Pass QEMUMachine to its init() method
- Put it in QEMUMachineInitArgs, so I don't have to touch every board.
Reviewed-by: Andreas Färber <afaerber@suse.de>
... - 12:29 pm Revision ad6423a7: acpi-test: basic acpi unit-test
- We run bios, and boot a minimal boot sector that immediately halts.
Then poke at memory to find ACPI tables.
This on... - 12:29 pm Revision 046a6486: MAINTAINERS: update X86 machine entry
- Add a bunch of files missing, and add self as maintainer. Since I'm
hacking on these anyway, it will be helpful if p... - 12:29 pm Revision cf252e51: pci: fix address space size for bridge
- Address space size for bridge should be full 64 bit,
so we should use UINT64_MAX not INT64_MAX as it's size.
Signed-... - 12:29 pm Revision 286690e3: pc: s/INT64_MAX/UINT64_MAX/
- It doesn't make sense for a region to be INT64_MAX in size:
memory core uses UINT64_MAX as a special value meaning
"a... - 12:29 pm Revision 92b8e39c: spapr_pci: s/INT64_MAX/UINT64_MAX/
- It doesn't make sense for a region to be INT64_MAX in size:
memory core uses UINT64_MAX as a special value meaning
"a... - 12:29 pm Revision 03f49957: split definitions for exec.c and translate-all.c radix trees
- The exec.c and translate-all.c radix trees are quite different, and
the exec.c one in particular is not limited to th... - 12:29 pm Revision 9736e55b: exec: replace leaf with skip
- In preparation for dynamic radix tree depth support, rename is_leaf
field to skip, telling us how many bits to skip t... - 12:29 pm Revision 8b795765: exec: extend skip field to 6 bit, page entry to 32 bit
- Extend skip to 6 bit. As page entry doesn't fit in 16 bit
any longer anyway, extend it to 32 bit.
This doubles node m... - 12:29 pm Revision 97115a8d: exec: pass hw address to phys_page_find
- callers always shift by target page bits so let's just do this
internally.
Signed-off-by: Michael S. Tsirkin <mst@re... - 12:29 pm Revision b35ba30f: exec: memory radix tree page level compression
- At the moment, memory radix tree is already variable width, but it can
only skip the low bits of address.
This is ef... - 12:29 pm Revision 57271d63: exec: make address spaces 64-bit wide
- As an alternative to commit 818f86b (exec: limit system memory
size, 2013-11-04) let's just make all address spaces 6... - 12:29 pm Revision 026736ce: exec: reduce L2_PAGE_SIZE
- With the single exception of ppc with 16M pages,
we get the same number of levels
with L2_PAGE_SIZE = 10 as with L2_P...
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