root / hw / arm_sysctl.c @ 0200db65
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1 | 5fafdf24 | ths | /*
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2 | e69954b9 | pbrook | * Status and system control registers for ARM RealView/Versatile boards.
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3 | e69954b9 | pbrook | *
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4 | 9ee6e8bb | pbrook | * Copyright (c) 2006-2007 CodeSourcery.
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5 | e69954b9 | pbrook | * Written by Paul Brook
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6 | e69954b9 | pbrook | *
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7 | 8e31bf38 | Matthew Fernandez | * This code is licensed under the GPL.
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8 | e69954b9 | pbrook | */
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9 | e69954b9 | pbrook | |
10 | 042eb37a | Daniel Jacobowitz | #include "hw.h" |
11 | 042eb37a | Daniel Jacobowitz | #include "qemu-timer.h" |
12 | 82634c2d | Paul Brook | #include "sysbus.h" |
13 | 9596ebb7 | pbrook | #include "primecell.h" |
14 | 87ecb68b | pbrook | #include "sysemu.h" |
15 | e69954b9 | pbrook | |
16 | e69954b9 | pbrook | #define LOCK_VALUE 0xa05f |
17 | e69954b9 | pbrook | |
18 | e69954b9 | pbrook | typedef struct { |
19 | 82634c2d | Paul Brook | SysBusDevice busdev; |
20 | 460d7c53 | Avi Kivity | MemoryRegion iomem; |
21 | 242ea2c6 | Peter Maydell | qemu_irq pl110_mux_ctrl; |
22 | 242ea2c6 | Peter Maydell | |
23 | e69954b9 | pbrook | uint32_t sys_id; |
24 | e69954b9 | pbrook | uint32_t leds; |
25 | e69954b9 | pbrook | uint16_t lockval; |
26 | e69954b9 | pbrook | uint32_t cfgdata1; |
27 | e69954b9 | pbrook | uint32_t cfgdata2; |
28 | e69954b9 | pbrook | uint32_t flags; |
29 | e69954b9 | pbrook | uint32_t nvflags; |
30 | e69954b9 | pbrook | uint32_t resetlevel; |
31 | 26e92f65 | Paul Brook | uint32_t proc_id; |
32 | b50ff6f5 | Peter Maydell | uint32_t sys_mci; |
33 | 34933c8c | Peter Maydell | uint32_t sys_cfgdata; |
34 | 34933c8c | Peter Maydell | uint32_t sys_cfgctrl; |
35 | 34933c8c | Peter Maydell | uint32_t sys_cfgstat; |
36 | 242ea2c6 | Peter Maydell | uint32_t sys_clcd; |
37 | e69954b9 | pbrook | } arm_sysctl_state; |
38 | e69954b9 | pbrook | |
39 | b5ad0ae7 | Peter Maydell | static const VMStateDescription vmstate_arm_sysctl = { |
40 | b5ad0ae7 | Peter Maydell | .name = "realview_sysctl",
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41 | 242ea2c6 | Peter Maydell | .version_id = 3,
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42 | b5ad0ae7 | Peter Maydell | .minimum_version_id = 1,
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43 | b5ad0ae7 | Peter Maydell | .fields = (VMStateField[]) { |
44 | b5ad0ae7 | Peter Maydell | VMSTATE_UINT32(leds, arm_sysctl_state), |
45 | b5ad0ae7 | Peter Maydell | VMSTATE_UINT16(lockval, arm_sysctl_state), |
46 | b5ad0ae7 | Peter Maydell | VMSTATE_UINT32(cfgdata1, arm_sysctl_state), |
47 | b5ad0ae7 | Peter Maydell | VMSTATE_UINT32(cfgdata2, arm_sysctl_state), |
48 | b5ad0ae7 | Peter Maydell | VMSTATE_UINT32(flags, arm_sysctl_state), |
49 | b5ad0ae7 | Peter Maydell | VMSTATE_UINT32(nvflags, arm_sysctl_state), |
50 | b5ad0ae7 | Peter Maydell | VMSTATE_UINT32(resetlevel, arm_sysctl_state), |
51 | 34933c8c | Peter Maydell | VMSTATE_UINT32_V(sys_mci, arm_sysctl_state, 2),
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52 | 34933c8c | Peter Maydell | VMSTATE_UINT32_V(sys_cfgdata, arm_sysctl_state, 2),
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53 | 34933c8c | Peter Maydell | VMSTATE_UINT32_V(sys_cfgctrl, arm_sysctl_state, 2),
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54 | 34933c8c | Peter Maydell | VMSTATE_UINT32_V(sys_cfgstat, arm_sysctl_state, 2),
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55 | 242ea2c6 | Peter Maydell | VMSTATE_UINT32_V(sys_clcd, arm_sysctl_state, 3),
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56 | b5ad0ae7 | Peter Maydell | VMSTATE_END_OF_LIST() |
57 | b5ad0ae7 | Peter Maydell | } |
58 | b5ad0ae7 | Peter Maydell | }; |
59 | b5ad0ae7 | Peter Maydell | |
60 | b50ff6f5 | Peter Maydell | /* The PB926 actually uses a different format for
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61 | b50ff6f5 | Peter Maydell | * its SYS_ID register. Fortunately the bits which are
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62 | b50ff6f5 | Peter Maydell | * board type on later boards are distinct.
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63 | b50ff6f5 | Peter Maydell | */
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64 | b50ff6f5 | Peter Maydell | #define BOARD_ID_PB926 0x100 |
65 | b50ff6f5 | Peter Maydell | #define BOARD_ID_EB 0x140 |
66 | b50ff6f5 | Peter Maydell | #define BOARD_ID_PBA8 0x178 |
67 | b50ff6f5 | Peter Maydell | #define BOARD_ID_PBX 0x182 |
68 | 34933c8c | Peter Maydell | #define BOARD_ID_VEXPRESS 0x190 |
69 | b50ff6f5 | Peter Maydell | |
70 | b50ff6f5 | Peter Maydell | static int board_id(arm_sysctl_state *s) |
71 | b50ff6f5 | Peter Maydell | { |
72 | b50ff6f5 | Peter Maydell | /* Extract the board ID field from the SYS_ID register value */
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73 | b50ff6f5 | Peter Maydell | return (s->sys_id >> 16) & 0xfff; |
74 | b50ff6f5 | Peter Maydell | } |
75 | b50ff6f5 | Peter Maydell | |
76 | be0f204a | Paul Brook | static void arm_sysctl_reset(DeviceState *d) |
77 | be0f204a | Paul Brook | { |
78 | be0f204a | Paul Brook | arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, sysbus_from_qdev(d)); |
79 | be0f204a | Paul Brook | |
80 | be0f204a | Paul Brook | s->leds = 0;
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81 | be0f204a | Paul Brook | s->lockval = 0;
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82 | be0f204a | Paul Brook | s->cfgdata1 = 0;
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83 | be0f204a | Paul Brook | s->cfgdata2 = 0;
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84 | be0f204a | Paul Brook | s->flags = 0;
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85 | be0f204a | Paul Brook | s->resetlevel = 0;
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86 | 242ea2c6 | Peter Maydell | if (board_id(s) == BOARD_ID_VEXPRESS) {
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87 | 242ea2c6 | Peter Maydell | /* On VExpress this register will RAZ/WI */
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88 | 242ea2c6 | Peter Maydell | s->sys_clcd = 0;
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89 | 242ea2c6 | Peter Maydell | } else {
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90 | 242ea2c6 | Peter Maydell | /* All others: CLCDID 0x1f, indicating VGA */
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91 | 242ea2c6 | Peter Maydell | s->sys_clcd = 0x1f00;
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92 | 242ea2c6 | Peter Maydell | } |
93 | be0f204a | Paul Brook | } |
94 | be0f204a | Paul Brook | |
95 | 460d7c53 | Avi Kivity | static uint64_t arm_sysctl_read(void *opaque, target_phys_addr_t offset, |
96 | 460d7c53 | Avi Kivity | unsigned size)
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97 | e69954b9 | pbrook | { |
98 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
99 | e69954b9 | pbrook | |
100 | e69954b9 | pbrook | switch (offset) {
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101 | e69954b9 | pbrook | case 0x00: /* ID */ |
102 | e69954b9 | pbrook | return s->sys_id;
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103 | e69954b9 | pbrook | case 0x04: /* SW */ |
104 | e69954b9 | pbrook | /* General purpose hardware switches.
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105 | e69954b9 | pbrook | We don't have a useful way of exposing these to the user. */
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106 | e69954b9 | pbrook | return 0; |
107 | e69954b9 | pbrook | case 0x08: /* LED */ |
108 | e69954b9 | pbrook | return s->leds;
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109 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
110 | e69954b9 | pbrook | return s->lockval;
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111 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
112 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
113 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
114 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
115 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
116 | e69954b9 | pbrook | case 0x24: /* 100HZ */ |
117 | e69954b9 | pbrook | /* ??? Implement these. */
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118 | e69954b9 | pbrook | return 0; |
119 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
120 | e69954b9 | pbrook | return s->cfgdata1;
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121 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
122 | e69954b9 | pbrook | return s->cfgdata2;
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123 | e69954b9 | pbrook | case 0x30: /* FLAGS */ |
124 | e69954b9 | pbrook | return s->flags;
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125 | e69954b9 | pbrook | case 0x38: /* NVFLAGS */ |
126 | e69954b9 | pbrook | return s->nvflags;
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127 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
128 | 34933c8c | Peter Maydell | if (board_id(s) == BOARD_ID_VEXPRESS) {
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129 | 34933c8c | Peter Maydell | /* reserved: RAZ/WI */
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130 | 34933c8c | Peter Maydell | return 0; |
131 | 34933c8c | Peter Maydell | } |
132 | e69954b9 | pbrook | return s->resetlevel;
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133 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
134 | e69954b9 | pbrook | return 1; |
135 | e69954b9 | pbrook | case 0x48: /* MCI */ |
136 | b50ff6f5 | Peter Maydell | return s->sys_mci;
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137 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
138 | e69954b9 | pbrook | return 0; |
139 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
140 | 242ea2c6 | Peter Maydell | return s->sys_clcd;
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141 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
142 | e69954b9 | pbrook | return 0; |
143 | e69954b9 | pbrook | case 0x58: /* BOOTCS */ |
144 | e69954b9 | pbrook | return 0; |
145 | e69954b9 | pbrook | case 0x5c: /* 24MHz */ |
146 | 74475455 | Paolo Bonzini | return muldiv64(qemu_get_clock_ns(vm_clock), 24000000, get_ticks_per_sec()); |
147 | e69954b9 | pbrook | case 0x60: /* MISC */ |
148 | e69954b9 | pbrook | return 0; |
149 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
150 | 26e92f65 | Paul Brook | return s->proc_id;
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151 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
152 | e69954b9 | pbrook | return 0xff000000; |
153 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
154 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
155 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
156 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
157 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
158 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
159 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
160 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
161 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
162 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
163 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
164 | e69954b9 | pbrook | case 0xc0: /* SYS_TEST_OSC0 */ |
165 | e69954b9 | pbrook | case 0xc4: /* SYS_TEST_OSC1 */ |
166 | e69954b9 | pbrook | case 0xc8: /* SYS_TEST_OSC2 */ |
167 | e69954b9 | pbrook | case 0xcc: /* SYS_TEST_OSC3 */ |
168 | e69954b9 | pbrook | case 0xd0: /* SYS_TEST_OSC4 */ |
169 | e69954b9 | pbrook | return 0; |
170 | 34933c8c | Peter Maydell | case 0xa0: /* SYS_CFGDATA */ |
171 | 34933c8c | Peter Maydell | if (board_id(s) != BOARD_ID_VEXPRESS) {
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172 | 34933c8c | Peter Maydell | goto bad_reg;
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173 | 34933c8c | Peter Maydell | } |
174 | 34933c8c | Peter Maydell | return s->sys_cfgdata;
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175 | 34933c8c | Peter Maydell | case 0xa4: /* SYS_CFGCTRL */ |
176 | 34933c8c | Peter Maydell | if (board_id(s) != BOARD_ID_VEXPRESS) {
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177 | 34933c8c | Peter Maydell | goto bad_reg;
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178 | 34933c8c | Peter Maydell | } |
179 | 34933c8c | Peter Maydell | return s->sys_cfgctrl;
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180 | 34933c8c | Peter Maydell | case 0xa8: /* SYS_CFGSTAT */ |
181 | 34933c8c | Peter Maydell | if (board_id(s) != BOARD_ID_VEXPRESS) {
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182 | 34933c8c | Peter Maydell | goto bad_reg;
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183 | 34933c8c | Peter Maydell | } |
184 | 34933c8c | Peter Maydell | return s->sys_cfgstat;
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185 | e69954b9 | pbrook | default:
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186 | 34933c8c | Peter Maydell | bad_reg:
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187 | e69954b9 | pbrook | printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset); |
188 | e69954b9 | pbrook | return 0; |
189 | e69954b9 | pbrook | } |
190 | e69954b9 | pbrook | } |
191 | e69954b9 | pbrook | |
192 | c227f099 | Anthony Liguori | static void arm_sysctl_write(void *opaque, target_phys_addr_t offset, |
193 | 460d7c53 | Avi Kivity | uint64_t val, unsigned size)
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194 | e69954b9 | pbrook | { |
195 | e69954b9 | pbrook | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
196 | e69954b9 | pbrook | |
197 | e69954b9 | pbrook | switch (offset) {
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198 | e69954b9 | pbrook | case 0x08: /* LED */ |
199 | e69954b9 | pbrook | s->leds = val; |
200 | e69954b9 | pbrook | case 0x0c: /* OSC0 */ |
201 | e69954b9 | pbrook | case 0x10: /* OSC1 */ |
202 | e69954b9 | pbrook | case 0x14: /* OSC2 */ |
203 | e69954b9 | pbrook | case 0x18: /* OSC3 */ |
204 | e69954b9 | pbrook | case 0x1c: /* OSC4 */ |
205 | e69954b9 | pbrook | /* ??? */
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206 | e69954b9 | pbrook | break;
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207 | e69954b9 | pbrook | case 0x20: /* LOCK */ |
208 | e69954b9 | pbrook | if (val == LOCK_VALUE)
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209 | e69954b9 | pbrook | s->lockval = val; |
210 | e69954b9 | pbrook | else
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211 | e69954b9 | pbrook | s->lockval = val & 0x7fff;
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212 | e69954b9 | pbrook | break;
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213 | e69954b9 | pbrook | case 0x28: /* CFGDATA1 */ |
214 | e69954b9 | pbrook | /* ??? Need to implement this. */
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215 | e69954b9 | pbrook | s->cfgdata1 = val; |
216 | e69954b9 | pbrook | break;
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217 | e69954b9 | pbrook | case 0x2c: /* CFGDATA2 */ |
218 | e69954b9 | pbrook | /* ??? Need to implement this. */
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219 | e69954b9 | pbrook | s->cfgdata2 = val; |
220 | e69954b9 | pbrook | break;
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221 | e69954b9 | pbrook | case 0x30: /* FLAGSSET */ |
222 | e69954b9 | pbrook | s->flags |= val; |
223 | e69954b9 | pbrook | break;
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224 | e69954b9 | pbrook | case 0x34: /* FLAGSCLR */ |
225 | e69954b9 | pbrook | s->flags &= ~val; |
226 | e69954b9 | pbrook | break;
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227 | e69954b9 | pbrook | case 0x38: /* NVFLAGSSET */ |
228 | e69954b9 | pbrook | s->nvflags |= val; |
229 | e69954b9 | pbrook | break;
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230 | e69954b9 | pbrook | case 0x3c: /* NVFLAGSCLR */ |
231 | e69954b9 | pbrook | s->nvflags &= ~val; |
232 | e69954b9 | pbrook | break;
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233 | e69954b9 | pbrook | case 0x40: /* RESETCTL */ |
234 | 34933c8c | Peter Maydell | if (board_id(s) == BOARD_ID_VEXPRESS) {
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235 | 34933c8c | Peter Maydell | /* reserved: RAZ/WI */
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236 | 34933c8c | Peter Maydell | break;
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237 | 34933c8c | Peter Maydell | } |
238 | e69954b9 | pbrook | if (s->lockval == LOCK_VALUE) {
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239 | e69954b9 | pbrook | s->resetlevel = val; |
240 | e69954b9 | pbrook | if (val & 0x100) |
241 | f3d6b95e | pbrook | qemu_system_reset_request (); |
242 | e69954b9 | pbrook | } |
243 | e69954b9 | pbrook | break;
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244 | e69954b9 | pbrook | case 0x44: /* PCICTL */ |
245 | e69954b9 | pbrook | /* nothing to do. */
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246 | e69954b9 | pbrook | break;
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247 | e69954b9 | pbrook | case 0x4c: /* FLASH */ |
248 | 242ea2c6 | Peter Maydell | break;
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249 | e69954b9 | pbrook | case 0x50: /* CLCD */ |
250 | 242ea2c6 | Peter Maydell | switch (board_id(s)) {
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251 | 242ea2c6 | Peter Maydell | case BOARD_ID_PB926:
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252 | 242ea2c6 | Peter Maydell | /* On 926 bits 13:8 are R/O, bits 1:0 control
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253 | 242ea2c6 | Peter Maydell | * the mux that defines how to interpret the PL110
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254 | 242ea2c6 | Peter Maydell | * graphics format, and other bits are r/w but we
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255 | 242ea2c6 | Peter Maydell | * don't implement them to do anything.
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256 | 242ea2c6 | Peter Maydell | */
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257 | 242ea2c6 | Peter Maydell | s->sys_clcd &= 0x3f00;
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258 | 242ea2c6 | Peter Maydell | s->sys_clcd |= val & ~0x3f00;
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259 | 242ea2c6 | Peter Maydell | qemu_set_irq(s->pl110_mux_ctrl, val & 3);
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260 | 242ea2c6 | Peter Maydell | break;
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261 | 242ea2c6 | Peter Maydell | case BOARD_ID_EB:
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262 | 242ea2c6 | Peter Maydell | /* The EB is the same except that there is no mux since
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263 | 242ea2c6 | Peter Maydell | * the EB has a PL111.
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264 | 242ea2c6 | Peter Maydell | */
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265 | 242ea2c6 | Peter Maydell | s->sys_clcd &= 0x3f00;
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266 | 242ea2c6 | Peter Maydell | s->sys_clcd |= val & ~0x3f00;
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267 | 242ea2c6 | Peter Maydell | break;
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268 | 242ea2c6 | Peter Maydell | case BOARD_ID_PBA8:
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269 | 242ea2c6 | Peter Maydell | case BOARD_ID_PBX:
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270 | 242ea2c6 | Peter Maydell | /* On PBA8 and PBX bit 7 is r/w and all other bits
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271 | 242ea2c6 | Peter Maydell | * are either r/o or RAZ/WI.
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272 | 242ea2c6 | Peter Maydell | */
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273 | 242ea2c6 | Peter Maydell | s->sys_clcd &= (1 << 7); |
274 | 242ea2c6 | Peter Maydell | s->sys_clcd |= val & ~(1 << 7); |
275 | 242ea2c6 | Peter Maydell | break;
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276 | 242ea2c6 | Peter Maydell | case BOARD_ID_VEXPRESS:
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277 | 242ea2c6 | Peter Maydell | default:
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278 | 242ea2c6 | Peter Maydell | /* On VExpress this register is unimplemented and will RAZ/WI */
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279 | 242ea2c6 | Peter Maydell | break;
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280 | 242ea2c6 | Peter Maydell | } |
281 | e69954b9 | pbrook | case 0x54: /* CLCDSER */ |
282 | e69954b9 | pbrook | case 0x64: /* DMAPSR0 */ |
283 | e69954b9 | pbrook | case 0x68: /* DMAPSR1 */ |
284 | e69954b9 | pbrook | case 0x6c: /* DMAPSR2 */ |
285 | e69954b9 | pbrook | case 0x70: /* IOSEL */ |
286 | e69954b9 | pbrook | case 0x74: /* PLDCTL */ |
287 | e69954b9 | pbrook | case 0x80: /* BUSID */ |
288 | e69954b9 | pbrook | case 0x84: /* PROCID0 */ |
289 | e69954b9 | pbrook | case 0x88: /* PROCID1 */ |
290 | e69954b9 | pbrook | case 0x8c: /* OSCRESET0 */ |
291 | e69954b9 | pbrook | case 0x90: /* OSCRESET1 */ |
292 | e69954b9 | pbrook | case 0x94: /* OSCRESET2 */ |
293 | e69954b9 | pbrook | case 0x98: /* OSCRESET3 */ |
294 | e69954b9 | pbrook | case 0x9c: /* OSCRESET4 */ |
295 | e69954b9 | pbrook | break;
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296 | 34933c8c | Peter Maydell | case 0xa0: /* SYS_CFGDATA */ |
297 | 34933c8c | Peter Maydell | if (board_id(s) != BOARD_ID_VEXPRESS) {
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298 | 34933c8c | Peter Maydell | goto bad_reg;
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299 | 34933c8c | Peter Maydell | } |
300 | 34933c8c | Peter Maydell | s->sys_cfgdata = val; |
301 | 34933c8c | Peter Maydell | return;
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302 | 34933c8c | Peter Maydell | case 0xa4: /* SYS_CFGCTRL */ |
303 | 34933c8c | Peter Maydell | if (board_id(s) != BOARD_ID_VEXPRESS) {
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304 | 34933c8c | Peter Maydell | goto bad_reg;
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305 | 34933c8c | Peter Maydell | } |
306 | 34933c8c | Peter Maydell | s->sys_cfgctrl = val & ~(3 << 18); |
307 | 34933c8c | Peter Maydell | s->sys_cfgstat = 1; /* complete */ |
308 | 34933c8c | Peter Maydell | switch (s->sys_cfgctrl) {
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309 | 34933c8c | Peter Maydell | case 0xc0800000: /* SYS_CFG_SHUTDOWN to motherboard */ |
310 | 34933c8c | Peter Maydell | qemu_system_shutdown_request(); |
311 | 34933c8c | Peter Maydell | break;
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312 | 34933c8c | Peter Maydell | case 0xc0900000: /* SYS_CFG_REBOOT to motherboard */ |
313 | 34933c8c | Peter Maydell | qemu_system_reset_request(); |
314 | 34933c8c | Peter Maydell | break;
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315 | 34933c8c | Peter Maydell | default:
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316 | 34933c8c | Peter Maydell | s->sys_cfgstat |= 2; /* error */ |
317 | 34933c8c | Peter Maydell | } |
318 | 34933c8c | Peter Maydell | return;
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319 | 34933c8c | Peter Maydell | case 0xa8: /* SYS_CFGSTAT */ |
320 | 34933c8c | Peter Maydell | if (board_id(s) != BOARD_ID_VEXPRESS) {
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321 | 34933c8c | Peter Maydell | goto bad_reg;
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322 | 34933c8c | Peter Maydell | } |
323 | 34933c8c | Peter Maydell | s->sys_cfgstat = val & 3;
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324 | 34933c8c | Peter Maydell | return;
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325 | e69954b9 | pbrook | default:
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326 | 34933c8c | Peter Maydell | bad_reg:
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327 | e69954b9 | pbrook | printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); |
328 | e69954b9 | pbrook | return;
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329 | e69954b9 | pbrook | } |
330 | e69954b9 | pbrook | } |
331 | e69954b9 | pbrook | |
332 | 460d7c53 | Avi Kivity | static const MemoryRegionOps arm_sysctl_ops = { |
333 | 460d7c53 | Avi Kivity | .read = arm_sysctl_read, |
334 | 460d7c53 | Avi Kivity | .write = arm_sysctl_write, |
335 | 460d7c53 | Avi Kivity | .endianness = DEVICE_NATIVE_ENDIAN, |
336 | e69954b9 | pbrook | }; |
337 | e69954b9 | pbrook | |
338 | b50ff6f5 | Peter Maydell | static void arm_sysctl_gpio_set(void *opaque, int line, int level) |
339 | b50ff6f5 | Peter Maydell | { |
340 | b50ff6f5 | Peter Maydell | arm_sysctl_state *s = (arm_sysctl_state *)opaque; |
341 | b50ff6f5 | Peter Maydell | switch (line) {
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342 | b50ff6f5 | Peter Maydell | case ARM_SYSCTL_GPIO_MMC_WPROT:
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343 | b50ff6f5 | Peter Maydell | { |
344 | b50ff6f5 | Peter Maydell | /* For PB926 and EB write-protect is bit 2 of SYS_MCI;
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345 | b50ff6f5 | Peter Maydell | * for all later boards it is bit 1.
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346 | b50ff6f5 | Peter Maydell | */
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347 | b50ff6f5 | Peter Maydell | int bit = 2; |
348 | b50ff6f5 | Peter Maydell | if ((board_id(s) == BOARD_ID_PB926) || (board_id(s) == BOARD_ID_EB)) {
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349 | b50ff6f5 | Peter Maydell | bit = 4;
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350 | b50ff6f5 | Peter Maydell | } |
351 | b50ff6f5 | Peter Maydell | s->sys_mci &= ~bit; |
352 | b50ff6f5 | Peter Maydell | if (level) {
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353 | b50ff6f5 | Peter Maydell | s->sys_mci |= bit; |
354 | b50ff6f5 | Peter Maydell | } |
355 | b50ff6f5 | Peter Maydell | break;
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356 | b50ff6f5 | Peter Maydell | } |
357 | b50ff6f5 | Peter Maydell | case ARM_SYSCTL_GPIO_MMC_CARDIN:
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358 | b50ff6f5 | Peter Maydell | s->sys_mci &= ~1;
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359 | b50ff6f5 | Peter Maydell | if (level) {
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360 | b50ff6f5 | Peter Maydell | s->sys_mci |= 1;
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361 | b50ff6f5 | Peter Maydell | } |
362 | b50ff6f5 | Peter Maydell | break;
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363 | b50ff6f5 | Peter Maydell | } |
364 | b50ff6f5 | Peter Maydell | } |
365 | b50ff6f5 | Peter Maydell | |
366 | 81a322d4 | Gerd Hoffmann | static int arm_sysctl_init1(SysBusDevice *dev) |
367 | e69954b9 | pbrook | { |
368 | 82634c2d | Paul Brook | arm_sysctl_state *s = FROM_SYSBUS(arm_sysctl_state, dev); |
369 | e69954b9 | pbrook | |
370 | 460d7c53 | Avi Kivity | memory_region_init_io(&s->iomem, &arm_sysctl_ops, s, "arm-sysctl", 0x1000); |
371 | 460d7c53 | Avi Kivity | sysbus_init_mmio_region(dev, &s->iomem); |
372 | b50ff6f5 | Peter Maydell | qdev_init_gpio_in(&s->busdev.qdev, arm_sysctl_gpio_set, 2);
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373 | 242ea2c6 | Peter Maydell | qdev_init_gpio_out(&s->busdev.qdev, &s->pl110_mux_ctrl, 1);
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374 | 81a322d4 | Gerd Hoffmann | return 0; |
375 | e69954b9 | pbrook | } |
376 | 82634c2d | Paul Brook | |
377 | 82634c2d | Paul Brook | /* Legacy helper function. */
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378 | 26e92f65 | Paul Brook | void arm_sysctl_init(uint32_t base, uint32_t sys_id, uint32_t proc_id)
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379 | 82634c2d | Paul Brook | { |
380 | 82634c2d | Paul Brook | DeviceState *dev; |
381 | 82634c2d | Paul Brook | |
382 | 82634c2d | Paul Brook | dev = qdev_create(NULL, "realview_sysctl"); |
383 | ee6847d1 | Gerd Hoffmann | qdev_prop_set_uint32(dev, "sys_id", sys_id);
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384 | e23a1b33 | Markus Armbruster | qdev_init_nofail(dev); |
385 | 26e92f65 | Paul Brook | qdev_prop_set_uint32(dev, "proc_id", proc_id);
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386 | 82634c2d | Paul Brook | sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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387 | 82634c2d | Paul Brook | } |
388 | 82634c2d | Paul Brook | |
389 | ee6847d1 | Gerd Hoffmann | static SysBusDeviceInfo arm_sysctl_info = {
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390 | ee6847d1 | Gerd Hoffmann | .init = arm_sysctl_init1, |
391 | ee6847d1 | Gerd Hoffmann | .qdev.name = "realview_sysctl",
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392 | ee6847d1 | Gerd Hoffmann | .qdev.size = sizeof(arm_sysctl_state),
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393 | b5ad0ae7 | Peter Maydell | .qdev.vmsd = &vmstate_arm_sysctl, |
394 | be0f204a | Paul Brook | .qdev.reset = arm_sysctl_reset, |
395 | ee6847d1 | Gerd Hoffmann | .qdev.props = (Property[]) { |
396 | e325775b | Gerd Hoffmann | DEFINE_PROP_UINT32("sys_id", arm_sysctl_state, sys_id, 0), |
397 | 26e92f65 | Paul Brook | DEFINE_PROP_UINT32("proc_id", arm_sysctl_state, proc_id, 0), |
398 | e325775b | Gerd Hoffmann | DEFINE_PROP_END_OF_LIST(), |
399 | ee6847d1 | Gerd Hoffmann | } |
400 | ee6847d1 | Gerd Hoffmann | }; |
401 | ee6847d1 | Gerd Hoffmann | |
402 | 82634c2d | Paul Brook | static void arm_sysctl_register_devices(void) |
403 | 82634c2d | Paul Brook | { |
404 | ee6847d1 | Gerd Hoffmann | sysbus_register_withprop(&arm_sysctl_info); |
405 | 82634c2d | Paul Brook | } |
406 | 82634c2d | Paul Brook | |
407 | 82634c2d | Paul Brook | device_init(arm_sysctl_register_devices) |