Archipelago » qemu

/*

 * QEMU Floppy disk emulator (Intel 82078)

 *

 * Copyright (c) 2003, 2007 Jocelyn Mayer

 * Copyright (c) 2008 Herv? Poussineau

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

/*

 * The controller is used in Sun4m systems in a slightly different

 * way. There are changes in DOR register and DMA is not available.

 */

#include "hw.h"

#include "fdc.h"

#include "qemu-error.h"

#include "qemu-timer.h"

#include "isa.h"

#include "sysbus.h"

#include "qdev-addr.h"

#include "blockdev.h"

#include "sysemu.h"

/********************************************************/

/* debug Floppy devices */

//#define DEBUG_FLOPPY

#ifdef DEBUG_FLOPPY

#define FLOPPY_DPRINTF(fmt, ...)                                \

    do { printf("FLOPPY: " fmt , ## __VA_ARGS__); } while (0)

#else

#define FLOPPY_DPRINTF(fmt, ...)

#endif

#define FLOPPY_ERROR(fmt, ...)                                          \

    do { printf("FLOPPY ERROR: %s: " fmt, __func__ , ## __VA_ARGS__); } while (0)

/********************************************************/

/* Floppy drive emulation                               */

#define GET_CUR_DRV(fdctrl) ((fdctrl)->cur_drv)

#define SET_CUR_DRV(fdctrl, drive) ((fdctrl)->cur_drv = (drive))

/* Will always be a fixed parameter for us */

#define FD_SECTOR_LEN          512

#define FD_SECTOR_SC           2   /* Sector size code */

#define FD_RESET_SENSEI_COUNT  4   /* Number of sense interrupts on RESET */

/* Floppy disk drive emulation */

typedef enum FDiskFlags {

    FDISK_DBL_SIDES  = 0x01,

} FDiskFlags;

typedef struct FDrive {

    BlockDriverState *bs;

    /* Drive status */

    FDriveType drive;

    uint8_t perpendicular;    /* 2.88 MB access mode    */

    /* Position */

    uint8_t head;

    uint8_t track;

    uint8_t sect;

    /* Media */

    FDiskFlags flags;

    uint8_t last_sect;        /* Nb sector per track    */

    uint8_t max_track;        /* Nb of tracks           */

    uint16_t bps;             /* Bytes per sector       */

    uint8_t ro;               /* Is read-only           */

    uint8_t media_changed;    /* Is media changed       */

} FDrive;

static void fd_init(FDrive *drv)

{

    /* Drive */

    drv->drive = FDRIVE_DRV_NONE;

    drv->perpendicular = 0;

    /* Disk */

    drv->last_sect = 0;

    drv->max_track = 0;

}

static int fd_sector_calc(uint8_t head, uint8_t track, uint8_t sect,

                          uint8_t last_sect)

{

    return (((track * 2) + head) * last_sect) + sect - 1;

}

/* Returns current position, in sectors, for given drive */

static int fd_sector(FDrive *drv)

{

    return fd_sector_calc(drv->head, drv->track, drv->sect, drv->last_sect);

}

/* Seek to a new position:

 * returns 0 if already on right track

 * returns 1 if track changed

 * returns 2 if track is invalid

 * returns 3 if sector is invalid

 * returns 4 if seek is disabled

 */

static int fd_seek(FDrive *drv, uint8_t head, uint8_t track, uint8_t sect,

                   int enable_seek)

{

    uint32_t sector;

    int ret;

    if (track > drv->max_track ||

        (head != 0 && (drv->flags & FDISK_DBL_SIDES) == 0)) {

        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",

                       head, track, sect, 1,

                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,

                       drv->max_track, drv->last_sect);

        return 2;

    }

    if (sect > drv->last_sect) {

        FLOPPY_DPRINTF("try to read %d %02x %02x (max=%d %d %02x %02x)\n",

                       head, track, sect, 1,

                       (drv->flags & FDISK_DBL_SIDES) == 0 ? 0 : 1,

                       drv->max_track, drv->last_sect);

        return 3;

    }

    sector = fd_sector_calc(head, track, sect, drv->last_sect);

    ret = 0;

    if (sector != fd_sector(drv)) {

#if 0

        if (!enable_seek) {

            FLOPPY_ERROR("no implicit seek %d %02x %02x (max=%d %02x %02x)\n",

                         head, track, sect, 1, drv->max_track, drv->last_sect);

            return 4;

        }

#endif

        drv->head = head;

        if (drv->track != track)

            ret = 1;

        drv->track = track;

        drv->sect = sect;

    }

    return ret;

}

/* Set drive back to track 0 */

static void fd_recalibrate(FDrive *drv)

{

    FLOPPY_DPRINTF("recalibrate\n");

    drv->head = 0;

    drv->track = 0;

    drv->sect = 1;

}

/* Revalidate a disk drive after a disk change */

static void fd_revalidate(FDrive *drv)

{

    int nb_heads, max_track, last_sect, ro;

    FDriveType drive;

    FLOPPY_DPRINTF("revalidate\n");

    if (drv->bs != NULL && bdrv_is_inserted(drv->bs)) {

        ro = bdrv_is_read_only(drv->bs);

        bdrv_get_floppy_geometry_hint(drv->bs, &nb_heads, &max_track,

                                      &last_sect, drv->drive, &drive);

        if (nb_heads != 0 && max_track != 0 && last_sect != 0) {

            FLOPPY_DPRINTF("User defined disk (%d %d %d)",

                           nb_heads - 1, max_track, last_sect);

        } else {

            FLOPPY_DPRINTF("Floppy disk (%d h %d t %d s) %s\n", nb_heads,

                           max_track, last_sect, ro ? "ro" : "rw");

        }

        if (nb_heads == 1) {

            drv->flags &= ~FDISK_DBL_SIDES;

        } else {

            drv->flags |= FDISK_DBL_SIDES;

        }

        drv->max_track = max_track;

        drv->last_sect = last_sect;

        drv->ro = ro;

        drv->drive = drive;

    } else {

        FLOPPY_DPRINTF("No disk in drive\n");

        drv->last_sect = 0;

        drv->max_track = 0;

        drv->flags &= ~FDISK_DBL_SIDES;

    }

}

/********************************************************/

/* Intel 82078 floppy disk controller emulation          */

typedef struct FDCtrl FDCtrl;

static void fdctrl_reset(FDCtrl *fdctrl, int do_irq);

static void fdctrl_reset_fifo(FDCtrl *fdctrl);

static int fdctrl_transfer_handler (void *opaque, int nchan,

                                    int dma_pos, int dma_len);

static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0);

static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl);

static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl);

static uint32_t fdctrl_read_dor(FDCtrl *fdctrl);

static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value);

static uint32_t fdctrl_read_tape(FDCtrl *fdctrl);

static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value);

static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl);

static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value);

static uint32_t fdctrl_read_data(FDCtrl *fdctrl);

static void fdctrl_write_data(FDCtrl *fdctrl, uint32_t value);

static uint32_t fdctrl_read_dir(FDCtrl *fdctrl);

enum {

    FD_DIR_WRITE   = 0,

    FD_DIR_READ    = 1,

    FD_DIR_SCANE   = 2,

    FD_DIR_SCANL   = 3,

    FD_DIR_SCANH   = 4,

};

enum {

    FD_STATE_MULTI  = 0x01,        /* multi track flag */

    FD_STATE_FORMAT = 0x02,        /* format flag */

    FD_STATE_SEEK   = 0x04,        /* seek flag */

};

enum {

    FD_REG_SRA = 0x00,

    FD_REG_SRB = 0x01,

    FD_REG_DOR = 0x02,

    FD_REG_TDR = 0x03,

    FD_REG_MSR = 0x04,

    FD_REG_DSR = 0x04,

    FD_REG_FIFO = 0x05,

    FD_REG_DIR = 0x07,

};

enum {

    FD_CMD_READ_TRACK = 0x02,

    FD_CMD_SPECIFY = 0x03,

    FD_CMD_SENSE_DRIVE_STATUS = 0x04,

    FD_CMD_WRITE = 0x05,

    FD_CMD_READ = 0x06,

    FD_CMD_RECALIBRATE = 0x07,

    FD_CMD_SENSE_INTERRUPT_STATUS = 0x08,

    FD_CMD_WRITE_DELETED = 0x09,

    FD_CMD_READ_ID = 0x0a,

    FD_CMD_READ_DELETED = 0x0c,

    FD_CMD_FORMAT_TRACK = 0x0d,

    FD_CMD_DUMPREG = 0x0e,

    FD_CMD_SEEK = 0x0f,

    FD_CMD_VERSION = 0x10,

    FD_CMD_SCAN_EQUAL = 0x11,

    FD_CMD_PERPENDICULAR_MODE = 0x12,

    FD_CMD_CONFIGURE = 0x13,

    FD_CMD_LOCK = 0x14,

    FD_CMD_VERIFY = 0x16,

    FD_CMD_POWERDOWN_MODE = 0x17,

    FD_CMD_PART_ID = 0x18,

    FD_CMD_SCAN_LOW_OR_EQUAL = 0x19,

    FD_CMD_SCAN_HIGH_OR_EQUAL = 0x1d,

    FD_CMD_SAVE = 0x2e,

    FD_CMD_OPTION = 0x33,

    FD_CMD_RESTORE = 0x4e,

    FD_CMD_DRIVE_SPECIFICATION_COMMAND = 0x8e,

    FD_CMD_RELATIVE_SEEK_OUT = 0x8f,

    FD_CMD_FORMAT_AND_WRITE = 0xcd,

    FD_CMD_RELATIVE_SEEK_IN = 0xcf,

};

enum {

    FD_CONFIG_PRETRK = 0xff, /* Pre-compensation set to track 0 */

    FD_CONFIG_FIFOTHR = 0x0f, /* FIFO threshold set to 1 byte */

    FD_CONFIG_POLL  = 0x10, /* Poll enabled */

    FD_CONFIG_EFIFO = 0x20, /* FIFO disabled */

    FD_CONFIG_EIS   = 0x40, /* No implied seeks */

};

enum {

    FD_SR0_EQPMT    = 0x10,

    FD_SR0_SEEK     = 0x20,

    FD_SR0_ABNTERM  = 0x40,

    FD_SR0_INVCMD   = 0x80,

    FD_SR0_RDYCHG   = 0xc0,

};

enum {

    FD_SR1_EC       = 0x80, /* End of cylinder */

};

enum {

    FD_SR2_SNS      = 0x04, /* Scan not satisfied */

    FD_SR2_SEH      = 0x08, /* Scan equal hit */

};

enum {

    FD_SRA_DIR      = 0x01,

    FD_SRA_nWP      = 0x02,

    FD_SRA_nINDX    = 0x04,

    FD_SRA_HDSEL    = 0x08,

    FD_SRA_nTRK0    = 0x10,

    FD_SRA_STEP     = 0x20,

    FD_SRA_nDRV2    = 0x40,

    FD_SRA_INTPEND  = 0x80,

};

enum {

    FD_SRB_MTR0     = 0x01,

    FD_SRB_MTR1     = 0x02,

    FD_SRB_WGATE    = 0x04,

    FD_SRB_RDATA    = 0x08,

    FD_SRB_WDATA    = 0x10,

    FD_SRB_DR0      = 0x20,

};

enum {

#if MAX_FD == 4

    FD_DOR_SELMASK  = 0x03,

#else

    FD_DOR_SELMASK  = 0x01,

#endif

    FD_DOR_nRESET   = 0x04,

    FD_DOR_DMAEN    = 0x08,

    FD_DOR_MOTEN0   = 0x10,

    FD_DOR_MOTEN1   = 0x20,

    FD_DOR_MOTEN2   = 0x40,

    FD_DOR_MOTEN3   = 0x80,

};

enum {

#if MAX_FD == 4

    FD_TDR_BOOTSEL  = 0x0c,

#else

    FD_TDR_BOOTSEL  = 0x04,

#endif

};

enum {

    FD_DSR_DRATEMASK= 0x03,

    FD_DSR_PWRDOWN  = 0x40,

    FD_DSR_SWRESET  = 0x80,

};

enum {

    FD_MSR_DRV0BUSY = 0x01,

    FD_MSR_DRV1BUSY = 0x02,

    FD_MSR_DRV2BUSY = 0x04,

    FD_MSR_DRV3BUSY = 0x08,

    FD_MSR_CMDBUSY  = 0x10,

    FD_MSR_NONDMA   = 0x20,

    FD_MSR_DIO      = 0x40,

    FD_MSR_RQM      = 0x80,

};

enum {

    FD_DIR_DSKCHG   = 0x80,

};

#define FD_MULTI_TRACK(state) ((state) & FD_STATE_MULTI)

#define FD_DID_SEEK(state) ((state) & FD_STATE_SEEK)

#define FD_FORMAT_CMD(state) ((state) & FD_STATE_FORMAT)

struct FDCtrl {

    qemu_irq irq;

    /* Controller state */

    QEMUTimer *result_timer;

    int dma_chann;

    /* Controller's identification */

    uint8_t version;

    /* HW */

    uint8_t sra;

    uint8_t srb;

    uint8_t dor;

    uint8_t dor_vmstate; /* only used as temp during vmstate */

    uint8_t tdr;

    uint8_t dsr;

    uint8_t msr;

    uint8_t cur_drv;

    uint8_t status0;

    uint8_t status1;

    uint8_t status2;

    /* Command FIFO */

    uint8_t *fifo;

    int32_t fifo_size;

    uint32_t data_pos;

    uint32_t data_len;

    uint8_t data_state;

    uint8_t data_dir;

    uint8_t eot; /* last wanted sector */

    /* States kept only to be returned back */

    /* precompensation */

    uint8_t precomp_trk;

    uint8_t config;

    uint8_t lock;

    /* Power down config (also with status regB access mode */

    uint8_t pwrd;

    /* Floppy drives */

    uint8_t num_floppies;

    /* Sun4m quirks? */

    int sun4m;

    FDrive drives[MAX_FD];

    int reset_sensei;

    /* Timers state */

    uint8_t timer0;

    uint8_t timer1;

};

typedef struct FDCtrlSysBus {

    SysBusDevice busdev;

    struct FDCtrl state;

} FDCtrlSysBus;

typedef struct FDCtrlISABus {

    ISADevice busdev;

    struct FDCtrl state;

    int32_t bootindexA;

    int32_t bootindexB;

} FDCtrlISABus;

static uint32_t fdctrl_read (void *opaque, uint32_t reg)

{

    FDCtrl *fdctrl = opaque;

    uint32_t retval;

    switch (reg) {

    case FD_REG_SRA:

        retval = fdctrl_read_statusA(fdctrl);

        break;

    case FD_REG_SRB:

        retval = fdctrl_read_statusB(fdctrl);

        break;

    case FD_REG_DOR:

        retval = fdctrl_read_dor(fdctrl);

        break;

    case FD_REG_TDR:

        retval = fdctrl_read_tape(fdctrl);

        break;

    case FD_REG_MSR:

        retval = fdctrl_read_main_status(fdctrl);

        break;

    case FD_REG_FIFO:

        retval = fdctrl_read_data(fdctrl);

        break;

    case FD_REG_DIR:

        retval = fdctrl_read_dir(fdctrl);

        break;

    default:

        retval = (uint32_t)(-1);

        break;

    }

    FLOPPY_DPRINTF("read reg%d: 0x%02x\n", reg & 7, retval);

    return retval;

}

static void fdctrl_write (void *opaque, uint32_t reg, uint32_t value)

{

    FDCtrl *fdctrl = opaque;

    FLOPPY_DPRINTF("write reg%d: 0x%02x\n", reg & 7, value);

    switch (reg) {

    case FD_REG_DOR:

        fdctrl_write_dor(fdctrl, value);

        break;

    case FD_REG_TDR:

        fdctrl_write_tape(fdctrl, value);

        break;

    case FD_REG_DSR:

        fdctrl_write_rate(fdctrl, value);

        break;

    case FD_REG_FIFO:

        fdctrl_write_data(fdctrl, value);

        break;

    default:

        break;

    }

}

static uint32_t fdctrl_read_mem (void *opaque, target_phys_addr_t reg)

{

    return fdctrl_read(opaque, (uint32_t)reg);

}

static void fdctrl_write_mem (void *opaque,

                              target_phys_addr_t reg, uint32_t value)

{

    fdctrl_write(opaque, (uint32_t)reg, value);

}

static CPUReadMemoryFunc * const fdctrl_mem_read[3] = {

    fdctrl_read_mem,

    fdctrl_read_mem,

    fdctrl_read_mem,

};

static CPUWriteMemoryFunc * const fdctrl_mem_write[3] = {

    fdctrl_write_mem,

    fdctrl_write_mem,

    fdctrl_write_mem,

};

static CPUReadMemoryFunc * const fdctrl_mem_read_strict[3] = {

    fdctrl_read_mem,

    NULL,

    NULL,

};

static CPUWriteMemoryFunc * const fdctrl_mem_write_strict[3] = {

    fdctrl_write_mem,

    NULL,

    NULL,

};

static bool fdrive_media_changed_needed(void *opaque)

{

    FDrive *drive = opaque;

    return (drive->bs != NULL && drive->media_changed != 1);

}

static const VMStateDescription vmstate_fdrive_media_changed = {

    .name = "fdrive/media_changed",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT8(media_changed, FDrive),

        VMSTATE_END_OF_LIST()

    }

};

static const VMStateDescription vmstate_fdrive = {

    .name = "fdrive",

    .version_id = 1,

    .minimum_version_id = 1,

    .minimum_version_id_old = 1,

    .fields      = (VMStateField[]) {

        VMSTATE_UINT8(head, FDrive),

        VMSTATE_UINT8(track, FDrive),

        VMSTATE_UINT8(sect, FDrive),

        VMSTATE_END_OF_LIST()

    },

    .subsections = (VMStateSubsection[]) {

        {

            .vmsd = &vmstate_fdrive_media_changed,

            .needed = &fdrive_media_changed_needed,

        } , {

            /* empty */

        }

    }

};

static void fdc_pre_save(void *opaque)

{

    FDCtrl *s = opaque;

    s->dor_vmstate = s->dor | GET_CUR_DRV(s);

}

static int fdc_post_load(void *opaque, int version_id)

{

    FDCtrl *s = opaque;

    SET_CUR_DRV(s, s->dor_vmstate & FD_DOR_SELMASK);

    s->dor = s->dor_vmstate & ~FD_DOR_SELMASK;

    return 0;

}

static const VMStateDescription vmstate_fdc = {

    .name = "fdc",

    .version_id = 2,

    .minimum_version_id = 2,

    .minimum_version_id_old = 2,

    .pre_save = fdc_pre_save,

    .post_load = fdc_post_load,

    .fields      = (VMStateField []) {

        /* Controller State */

        VMSTATE_UINT8(sra, FDCtrl),

        VMSTATE_UINT8(srb, FDCtrl),

        VMSTATE_UINT8(dor_vmstate, FDCtrl),

        VMSTATE_UINT8(tdr, FDCtrl),

        VMSTATE_UINT8(dsr, FDCtrl),

        VMSTATE_UINT8(msr, FDCtrl),

        VMSTATE_UINT8(status0, FDCtrl),

        VMSTATE_UINT8(status1, FDCtrl),

        VMSTATE_UINT8(status2, FDCtrl),

        /* Command FIFO */

        VMSTATE_VARRAY_INT32(fifo, FDCtrl, fifo_size, 0, vmstate_info_uint8,

                             uint8_t),

        VMSTATE_UINT32(data_pos, FDCtrl),

        VMSTATE_UINT32(data_len, FDCtrl),

        VMSTATE_UINT8(data_state, FDCtrl),

        VMSTATE_UINT8(data_dir, FDCtrl),

        VMSTATE_UINT8(eot, FDCtrl),

        /* States kept only to be returned back */

        VMSTATE_UINT8(timer0, FDCtrl),

        VMSTATE_UINT8(timer1, FDCtrl),

        VMSTATE_UINT8(precomp_trk, FDCtrl),

        VMSTATE_UINT8(config, FDCtrl),

        VMSTATE_UINT8(lock, FDCtrl),

        VMSTATE_UINT8(pwrd, FDCtrl),

        VMSTATE_UINT8_EQUAL(num_floppies, FDCtrl),

        VMSTATE_STRUCT_ARRAY(drives, FDCtrl, MAX_FD, 1,

                             vmstate_fdrive, FDrive),

        VMSTATE_END_OF_LIST()

    }

};

static void fdctrl_external_reset_sysbus(DeviceState *d)

{

    FDCtrlSysBus *sys = container_of(d, FDCtrlSysBus, busdev.qdev);

    FDCtrl *s = &sys->state;

    fdctrl_reset(s, 0);

}

static void fdctrl_external_reset_isa(DeviceState *d)

{

    FDCtrlISABus *isa = container_of(d, FDCtrlISABus, busdev.qdev);

    FDCtrl *s = &isa->state;

    fdctrl_reset(s, 0);

}

static void fdctrl_handle_tc(void *opaque, int irq, int level)

{

    //FDCtrl *s = opaque;

    if (level) {

        // XXX

        FLOPPY_DPRINTF("TC pulsed\n");

    }

}

/* Change IRQ state */

static void fdctrl_reset_irq(FDCtrl *fdctrl)

{

    if (!(fdctrl->sra & FD_SRA_INTPEND))

        return;

    FLOPPY_DPRINTF("Reset interrupt\n");

    qemu_set_irq(fdctrl->irq, 0);

    fdctrl->sra &= ~FD_SRA_INTPEND;

}

static void fdctrl_raise_irq(FDCtrl *fdctrl, uint8_t status0)

{

    /* Sparc mutation */

    if (fdctrl->sun4m && (fdctrl->msr & FD_MSR_CMDBUSY)) {

        /* XXX: not sure */

        fdctrl->msr &= ~FD_MSR_CMDBUSY;

        fdctrl->msr |= FD_MSR_RQM | FD_MSR_DIO;

        fdctrl->status0 = status0;

        return;

    }

    if (!(fdctrl->sra & FD_SRA_INTPEND)) {

        qemu_set_irq(fdctrl->irq, 1);

        fdctrl->sra |= FD_SRA_INTPEND;

    }

    fdctrl->reset_sensei = 0;

    fdctrl->status0 = status0;

    FLOPPY_DPRINTF("Set interrupt status to 0x%02x\n", fdctrl->status0);

}

/* Reset controller */

static void fdctrl_reset(FDCtrl *fdctrl, int do_irq)

{

    int i;

    FLOPPY_DPRINTF("reset controller\n");

    fdctrl_reset_irq(fdctrl);

    /* Initialise controller */

    fdctrl->sra = 0;

    fdctrl->srb = 0xc0;

    if (!fdctrl->drives[1].bs)

        fdctrl->sra |= FD_SRA_nDRV2;

    fdctrl->cur_drv = 0;

    fdctrl->dor = FD_DOR_nRESET;

    fdctrl->dor |= (fdctrl->dma_chann != -1) ? FD_DOR_DMAEN : 0;

    fdctrl->msr = FD_MSR_RQM;

    /* FIFO state */

    fdctrl->data_pos = 0;

    fdctrl->data_len = 0;

    fdctrl->data_state = 0;

    fdctrl->data_dir = FD_DIR_WRITE;

    for (i = 0; i < MAX_FD; i++)

        fd_recalibrate(&fdctrl->drives[i]);

    fdctrl_reset_fifo(fdctrl);

    if (do_irq) {

        fdctrl_raise_irq(fdctrl, FD_SR0_RDYCHG);

        fdctrl->reset_sensei = FD_RESET_SENSEI_COUNT;

    }

}

static inline FDrive *drv0(FDCtrl *fdctrl)

{

    return &fdctrl->drives[(fdctrl->tdr & FD_TDR_BOOTSEL) >> 2];

}

static inline FDrive *drv1(FDCtrl *fdctrl)

{

    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (1 << 2))

        return &fdctrl->drives[1];

    else

        return &fdctrl->drives[0];

}

#if MAX_FD == 4

static inline FDrive *drv2(FDCtrl *fdctrl)

{

    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (2 << 2))

        return &fdctrl->drives[2];

    else

        return &fdctrl->drives[1];

}

static inline FDrive *drv3(FDCtrl *fdctrl)

{

    if ((fdctrl->tdr & FD_TDR_BOOTSEL) < (3 << 2))

        return &fdctrl->drives[3];

    else

        return &fdctrl->drives[2];

}

#endif

static FDrive *get_cur_drv(FDCtrl *fdctrl)

{

    switch (fdctrl->cur_drv) {

        case 0: return drv0(fdctrl);

        case 1: return drv1(fdctrl);

#if MAX_FD == 4

        case 2: return drv2(fdctrl);

        case 3: return drv3(fdctrl);

#endif

        default: return NULL;

    }

}

/* Status A register : 0x00 (read-only) */

static uint32_t fdctrl_read_statusA(FDCtrl *fdctrl)

{

    uint32_t retval = fdctrl->sra;

    FLOPPY_DPRINTF("status register A: 0x%02x\n", retval);

    return retval;

}

/* Status B register : 0x01 (read-only) */

static uint32_t fdctrl_read_statusB(FDCtrl *fdctrl)

{

    uint32_t retval = fdctrl->srb;

    FLOPPY_DPRINTF("status register B: 0x%02x\n", retval);

    return retval;

}

/* Digital output register : 0x02 */

static uint32_t fdctrl_read_dor(FDCtrl *fdctrl)

{

    uint32_t retval = fdctrl->dor;

    /* Selected drive */

    retval |= fdctrl->cur_drv;

    FLOPPY_DPRINTF("digital output register: 0x%02x\n", retval);

    return retval;

}

static void fdctrl_write_dor(FDCtrl *fdctrl, uint32_t value)

{

    FLOPPY_DPRINTF("digital output register set to 0x%02x\n", value);

    /* Motors */

    if (value & FD_DOR_MOTEN0)

        fdctrl->srb |= FD_SRB_MTR0;

    else

        fdctrl->srb &= ~FD_SRB_MTR0;

    if (value & FD_DOR_MOTEN1)

        fdctrl->srb |= FD_SRB_MTR1;

    else

        fdctrl->srb &= ~FD_SRB_MTR1;

    /* Drive */

    if (value & 1)

        fdctrl->srb |= FD_SRB_DR0;

    else

        fdctrl->srb &= ~FD_SRB_DR0;

    /* Reset */

    if (!(value & FD_DOR_nRESET)) {

        if (fdctrl->dor & FD_DOR_nRESET) {

            FLOPPY_DPRINTF("controller enter RESET state\n");

        }

    } else {

        if (!(fdctrl->dor & FD_DOR_nRESET)) {

            FLOPPY_DPRINTF("controller out of RESET state\n");

            fdctrl_reset(fdctrl, 1);

            fdctrl->dsr &= ~FD_DSR_PWRDOWN;

        }

    }

    /* Selected drive */

    fdctrl->cur_drv = value & FD_DOR_SELMASK;

    fdctrl->dor = value;

}

/* Tape drive register : 0x03 */

static uint32_t fdctrl_read_tape(FDCtrl *fdctrl)

{

    uint32_t retval = fdctrl->tdr;

    FLOPPY_DPRINTF("tape drive register: 0x%02x\n", retval);

    return retval;

}

static void fdctrl_write_tape(FDCtrl *fdctrl, uint32_t value)

{

    /* Reset mode */

    if (!(fdctrl->dor & FD_DOR_nRESET)) {

        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");

        return;

    }

    FLOPPY_DPRINTF("tape drive register set to 0x%02x\n", value);

    /* Disk boot selection indicator */

    fdctrl->tdr = value & FD_TDR_BOOTSEL;

    /* Tape indicators: never allow */

}

/* Main status register : 0x04 (read) */

static uint32_t fdctrl_read_main_status(FDCtrl *fdctrl)

{

    uint32_t retval = fdctrl->msr;

    fdctrl->dsr &= ~FD_DSR_PWRDOWN;

    fdctrl->dor |= FD_DOR_nRESET;

    /* Sparc mutation */

    if (fdctrl->sun4m) {

        retval |= FD_MSR_DIO;

        fdctrl_reset_irq(fdctrl);

    };

    FLOPPY_DPRINTF("main status register: 0x%02x\n", retval);

    return retval;

}

/* Data select rate register : 0x04 (write) */

static void fdctrl_write_rate(FDCtrl *fdctrl, uint32_t value)

{

    /* Reset mode */

    if (!(fdctrl->dor & FD_DOR_nRESET)) {

        FLOPPY_DPRINTF("Floppy controller in RESET state !\n");

        return;

    }

    FLOPPY_DPRINTF("select rate register set to 0x%02x\n", value);

    /* Reset: autoclear */

    if (value & FD_DSR_SWRESET) {

        fdctrl->dor &= ~FD_DOR_nRESET;

        fdctrl_reset(fdctrl, 1);

        fdctrl->dor |= FD_DOR_nRESET;

    }

    if (value & FD_DSR_PWRDOWN) {

        fdctrl_reset(fdctrl, 1);

    }

    fdctrl->dsr = value;

}

static int fdctrl_media_changed(FDrive *drv)

{

    int ret;

    if (!drv->bs)

        return 0;

    if (drv->media_changed) {

        drv->media_changed = 0;

        ret = 1;

    } else {

        ret = bdrv_media_changed(drv->bs);