root / hw / ppc440.c @ 0200db65
History | View | Annotate | Download (3.5 kB)
1 | 75dd595b | aurel32 | /*
|
---|---|---|---|
2 | 75dd595b | aurel32 | * Qemu PowerPC 440 chip emulation
|
3 | 75dd595b | aurel32 | *
|
4 | 75dd595b | aurel32 | * Copyright 2007 IBM Corporation.
|
5 | 75dd595b | aurel32 | * Authors:
|
6 | 75dd595b | aurel32 | * Jerone Young <jyoung5@us.ibm.com>
|
7 | 75dd595b | aurel32 | * Christian Ehrhardt <ehrhardt@linux.vnet.ibm.com>
|
8 | 75dd595b | aurel32 | * Hollis Blanchard <hollisb@us.ibm.com>
|
9 | 75dd595b | aurel32 | *
|
10 | 75dd595b | aurel32 | * This work is licensed under the GNU GPL license version 2 or later.
|
11 | 75dd595b | aurel32 | *
|
12 | 75dd595b | aurel32 | */
|
13 | 75dd595b | aurel32 | |
14 | 75dd595b | aurel32 | #include "hw.h" |
15 | 802670e6 | Blue Swirl | #include "pc.h" |
16 | 75dd595b | aurel32 | #include "isa.h" |
17 | 75dd595b | aurel32 | #include "ppc.h" |
18 | 75dd595b | aurel32 | #include "ppc4xx.h" |
19 | 75dd595b | aurel32 | #include "ppc440.h" |
20 | 75dd595b | aurel32 | #include "ppc405.h" |
21 | 75dd595b | aurel32 | #include "sysemu.h" |
22 | 75dd595b | aurel32 | #include "kvm.h" |
23 | 75dd595b | aurel32 | |
24 | 75dd595b | aurel32 | #define PPC440EP_PCI_CONFIG 0xeec00000 |
25 | 75dd595b | aurel32 | #define PPC440EP_PCI_INTACK 0xeed00000 |
26 | 75dd595b | aurel32 | #define PPC440EP_PCI_SPECIAL 0xeed00000 |
27 | 75dd595b | aurel32 | #define PPC440EP_PCI_REGS 0xef400000 |
28 | 75dd595b | aurel32 | #define PPC440EP_PCI_IO 0xe8000000 |
29 | 75dd595b | aurel32 | #define PPC440EP_PCI_IOLEN 0x00010000 |
30 | 75dd595b | aurel32 | |
31 | 75dd595b | aurel32 | #define PPC440EP_SDRAM_NR_BANKS 4 |
32 | 75dd595b | aurel32 | |
33 | 75dd595b | aurel32 | static const unsigned int ppc440ep_sdram_bank_sizes[] = { |
34 | 75dd595b | aurel32 | 256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0 |
35 | 75dd595b | aurel32 | }; |
36 | 75dd595b | aurel32 | |
37 | 3e9f0113 | Richard Henderson | CPUState *ppc440ep_init(MemoryRegion *address_space_mem, ram_addr_t *ram_size, |
38 | 3e9f0113 | Richard Henderson | PCIBus **pcip, const unsigned int pci_irq_nrs[4], |
39 | 3e9f0113 | Richard Henderson | int do_init, const char *cpu_model) |
40 | 75dd595b | aurel32 | { |
41 | b6dcbe08 | Avi Kivity | MemoryRegion *ram_memories |
42 | b6dcbe08 | Avi Kivity | = g_malloc(PPC440EP_SDRAM_NR_BANKS * sizeof(*ram_memories));
|
43 | c227f099 | Anthony Liguori | target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS]; |
44 | c227f099 | Anthony Liguori | target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS]; |
45 | 75dd595b | aurel32 | CPUState *env; |
46 | 75dd595b | aurel32 | qemu_irq *pic; |
47 | 75dd595b | aurel32 | qemu_irq *irqs; |
48 | 75dd595b | aurel32 | qemu_irq *pci_irqs; |
49 | 75dd595b | aurel32 | |
50 | 0dd4bc7d | Alexander Graf | if (cpu_model == NULL) { |
51 | 0dd4bc7d | Alexander Graf | cpu_model = "440-Xilinx"; // XXX: should be 440EP |
52 | 0dd4bc7d | Alexander Graf | } |
53 | 727170b6 | Blue Swirl | env = cpu_init(cpu_model); |
54 | 75dd595b | aurel32 | if (!env) {
|
55 | 75dd595b | aurel32 | fprintf(stderr, "Unable to initialize CPU!\n");
|
56 | 75dd595b | aurel32 | exit(1);
|
57 | 75dd595b | aurel32 | } |
58 | 75dd595b | aurel32 | |
59 | 75dd595b | aurel32 | ppc_dcr_init(env, NULL, NULL); |
60 | 75dd595b | aurel32 | |
61 | 75dd595b | aurel32 | /* interrupt controller */
|
62 | 7267c094 | Anthony Liguori | irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
|
63 | 75dd595b | aurel32 | irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; |
64 | 75dd595b | aurel32 | irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; |
65 | 75dd595b | aurel32 | pic = ppcuic_init(env, irqs, 0x0C0, 0, 1); |
66 | 75dd595b | aurel32 | |
67 | 75dd595b | aurel32 | /* SDRAM controller */
|
68 | 75dd595b | aurel32 | memset(ram_bases, 0, sizeof(ram_bases)); |
69 | 75dd595b | aurel32 | memset(ram_sizes, 0, sizeof(ram_sizes)); |
70 | 75dd595b | aurel32 | *ram_size = ppc4xx_sdram_adjust(*ram_size, PPC440EP_SDRAM_NR_BANKS, |
71 | b6dcbe08 | Avi Kivity | ram_memories, |
72 | 75dd595b | aurel32 | ram_bases, ram_sizes, |
73 | 75dd595b | aurel32 | ppc440ep_sdram_bank_sizes); |
74 | 75dd595b | aurel32 | /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
|
75 | b6dcbe08 | Avi Kivity | ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories,
|
76 | b6dcbe08 | Avi Kivity | ram_bases, ram_sizes, do_init); |
77 | 75dd595b | aurel32 | |
78 | 75dd595b | aurel32 | /* PCI */
|
79 | 7267c094 | Anthony Liguori | pci_irqs = g_malloc(sizeof(qemu_irq) * 4); |
80 | 75dd595b | aurel32 | pci_irqs[0] = pic[pci_irq_nrs[0]]; |
81 | 75dd595b | aurel32 | pci_irqs[1] = pic[pci_irq_nrs[1]]; |
82 | 75dd595b | aurel32 | pci_irqs[2] = pic[pci_irq_nrs[2]]; |
83 | 75dd595b | aurel32 | pci_irqs[3] = pic[pci_irq_nrs[3]]; |
84 | 75dd595b | aurel32 | *pcip = ppc4xx_pci_init(env, pci_irqs, |
85 | 75dd595b | aurel32 | PPC440EP_PCI_CONFIG, |
86 | 75dd595b | aurel32 | PPC440EP_PCI_INTACK, |
87 | 75dd595b | aurel32 | PPC440EP_PCI_SPECIAL, |
88 | 75dd595b | aurel32 | PPC440EP_PCI_REGS); |
89 | 75dd595b | aurel32 | if (!*pcip)
|
90 | 75dd595b | aurel32 | printf("couldn't create PCI controller!\n");
|
91 | 75dd595b | aurel32 | |
92 | 968d683c | Alexander Graf | isa_mmio_init(PPC440EP_PCI_IO, PPC440EP_PCI_IOLEN); |
93 | 75dd595b | aurel32 | |
94 | 802670e6 | Blue Swirl | if (serial_hds[0] != NULL) { |
95 | 3e9f0113 | Richard Henderson | serial_mm_init(address_space_mem, 0xef600300, 0, pic[0], |
96 | 39186d8a | Richard Henderson | PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
|
97 | 39186d8a | Richard Henderson | DEVICE_BIG_ENDIAN); |
98 | 802670e6 | Blue Swirl | } |
99 | 802670e6 | Blue Swirl | if (serial_hds[1] != NULL) { |
100 | 3e9f0113 | Richard Henderson | serial_mm_init(address_space_mem, 0xef600400, 0, pic[1], |
101 | 39186d8a | Richard Henderson | PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
|
102 | 39186d8a | Richard Henderson | DEVICE_BIG_ENDIAN); |
103 | 802670e6 | Blue Swirl | } |
104 | 75dd595b | aurel32 | |
105 | 75dd595b | aurel32 | return env;
|
106 | 75dd595b | aurel32 | } |