root / hw / spapr_hcall.c @ 0200db65
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#include "sysemu.h" |
---|---|
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#include "cpu.h" |
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#include "dyngen-exec.h" |
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#include "qemu-char.h" |
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#include "sysemu.h" |
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#include "qemu-char.h" |
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#include "helper_regs.h" |
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#include "hw/spapr.h" |
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|
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#define HPTES_PER_GROUP 8 |
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|
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#define HPTE_V_SSIZE_SHIFT 62 |
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#define HPTE_V_AVPN_SHIFT 7 |
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#define HPTE_V_AVPN 0x3fffffffffffff80ULL |
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#define HPTE_V_AVPN_VAL(x) (((x) & HPTE_V_AVPN) >> HPTE_V_AVPN_SHIFT)
|
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#define HPTE_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80UL)) |
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#define HPTE_V_BOLTED 0x0000000000000010ULL |
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#define HPTE_V_LOCK 0x0000000000000008ULL |
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#define HPTE_V_LARGE 0x0000000000000004ULL |
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#define HPTE_V_SECONDARY 0x0000000000000002ULL |
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#define HPTE_V_VALID 0x0000000000000001ULL |
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|
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#define HPTE_R_PP0 0x8000000000000000ULL |
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#define HPTE_R_TS 0x4000000000000000ULL |
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#define HPTE_R_KEY_HI 0x3000000000000000ULL |
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#define HPTE_R_RPN_SHIFT 12 |
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#define HPTE_R_RPN 0x3ffffffffffff000ULL |
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#define HPTE_R_FLAGS 0x00000000000003ffULL |
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#define HPTE_R_PP 0x0000000000000003ULL |
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#define HPTE_R_N 0x0000000000000004ULL |
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#define HPTE_R_G 0x0000000000000008ULL |
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#define HPTE_R_M 0x0000000000000010ULL |
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#define HPTE_R_I 0x0000000000000020ULL |
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#define HPTE_R_W 0x0000000000000040ULL |
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#define HPTE_R_WIMG 0x0000000000000078ULL |
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#define HPTE_R_C 0x0000000000000080ULL |
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#define HPTE_R_R 0x0000000000000100ULL |
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#define HPTE_R_KEY_LO 0x0000000000000e00ULL |
39 |
|
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#define HPTE_V_1TB_SEG 0x4000000000000000ULL |
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#define HPTE_V_VRMA_MASK 0x4001ffffff000000ULL |
42 |
|
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#define HPTE_V_HVLOCK 0x40ULL |
44 |
|
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static inline int lock_hpte(void *hpte, target_ulong bits) |
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{ |
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uint64_t pteh; |
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|
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pteh = ldq_p(hpte); |
50 |
|
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/* We're protected by qemu's global lock here */
|
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if (pteh & bits) {
|
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return 0; |
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} |
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stq_p(hpte, pteh | HPTE_V_HVLOCK); |
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return 1; |
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} |
58 |
|
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static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r,
|
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target_ulong pte_index) |
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{ |
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target_ulong rb, va_low; |
63 |
|
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rb = (v & ~0x7fULL) << 16; /* AVA field */ |
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va_low = pte_index >> 3;
|
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if (v & HPTE_V_SECONDARY) {
|
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va_low = ~va_low; |
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} |
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/* xor vsid from AVA */
|
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if (!(v & HPTE_V_1TB_SEG)) {
|
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va_low ^= v >> 12;
|
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} else {
|
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va_low ^= v >> 24;
|
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} |
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va_low &= 0x7ff;
|
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if (v & HPTE_V_LARGE) {
|
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rb |= 1; /* L field */ |
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#if 0 /* Disable that P7 specific bit for now */
|
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if (r & 0xff000) {
|
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/* non-16MB large page, must be 64k */
|
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/* (masks depend on page size) */
|
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rb |= 0x1000; /* page encoding in LP field */
|
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rb |= (va_low & 0x7f) << 16; /* 7b of VA in AVA/LP field */
|
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rb |= (va_low & 0xfe); /* AVAL field */
|
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}
|
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#endif
|
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} else {
|
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/* 4kB page */
|
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rb |= (va_low & 0x7ff) << 12; /* remaining 11b of AVA */ |
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} |
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rb |= (v >> 54) & 0x300; /* B field */ |
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return rb;
|
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} |
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|
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static target_ulong h_enter(CPUState *env, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
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{ |
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target_ulong flags = args[0];
|
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target_ulong pte_index = args[1];
|
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target_ulong pteh = args[2];
|
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target_ulong ptel = args[3];
|
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target_ulong page_shift = 12;
|
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target_ulong raddr; |
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target_ulong i; |
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uint8_t *hpte; |
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|
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/* only handle 4k and 16M pages for now */
|
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if (pteh & HPTE_V_LARGE) {
|
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#if 0 /* We don't support 64k pages yet */
|
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if ((ptel & 0xf000) == 0x1000) {
|
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/* 64k page */
|
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} else
|
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#endif
|
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if ((ptel & 0xff000) == 0) { |
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/* 16M page */
|
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page_shift = 24;
|
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/* lowest AVA bit must be 0 for 16M pages */
|
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if (pteh & 0x80) { |
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return H_PARAMETER;
|
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} |
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} else {
|
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return H_PARAMETER;
|
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} |
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} |
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|
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raddr = (ptel & HPTE_R_RPN) & ~((1ULL << page_shift) - 1); |
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|
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if (raddr < spapr->ram_limit) {
|
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/* Regular RAM - should have WIMG=0010 */
|
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if ((ptel & HPTE_R_WIMG) != HPTE_R_M) {
|
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return H_PARAMETER;
|
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} |
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} else {
|
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/* Looks like an IO address */
|
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/* FIXME: What WIMG combinations could be sensible for IO?
|
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* For now we allow WIMG=010x, but are there others? */
|
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/* FIXME: Should we check against registered IO addresses? */
|
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if ((ptel & (HPTE_R_W | HPTE_R_I | HPTE_R_M)) != HPTE_R_I) {
|
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return H_PARAMETER;
|
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} |
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} |
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|
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pteh &= ~0x60ULL;
|
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|
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if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
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return H_PARAMETER;
|
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} |
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if (likely((flags & H_EXACT) == 0)) { |
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pte_index &= ~7ULL;
|
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
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for (i = 0; ; ++i) { |
152 |
if (i == 8) { |
153 |
return H_PTEG_FULL;
|
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} |
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if (((ldq_p(hpte) & HPTE_V_VALID) == 0) && |
156 |
lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) { |
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break;
|
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} |
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hpte += HASH_PTE_SIZE_64; |
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} |
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} else {
|
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i = 0;
|
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hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
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if (!lock_hpte(hpte, HPTE_V_HVLOCK | HPTE_V_VALID)) {
|
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return H_PTEG_FULL;
|
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} |
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} |
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stq_p(hpte + (HASH_PTE_SIZE_64/2), ptel);
|
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/* eieio(); FIXME: need some sort of barrier for smp? */
|
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stq_p(hpte, pteh); |
171 |
|
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assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); |
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args[0] = pte_index + i;
|
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return H_SUCCESS;
|
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} |
176 |
|
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enum {
|
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REMOVE_SUCCESS = 0,
|
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REMOVE_NOT_FOUND = 1,
|
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REMOVE_PARM = 2,
|
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REMOVE_HW = 3,
|
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}; |
183 |
|
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static target_ulong remove_hpte(CPUState *env, target_ulong ptex,
|
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target_ulong avpn, |
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target_ulong flags, |
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target_ulong *vp, target_ulong *rp) |
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{ |
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uint8_t *hpte; |
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target_ulong v, r, rb; |
191 |
|
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if ((ptex * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
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return REMOVE_PARM;
|
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} |
195 |
|
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hpte = env->external_htab + (ptex * HASH_PTE_SIZE_64); |
197 |
while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
|
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/* We have no real concurrency in qemu soft-emulation, so we
|
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* will never actually have a contested lock */
|
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assert(0);
|
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} |
202 |
|
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v = ldq_p(hpte); |
204 |
r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
|
205 |
|
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if ((v & HPTE_V_VALID) == 0 || |
207 |
((flags & H_AVPN) && (v & ~0x7fULL) != avpn) ||
|
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((flags & H_ANDCOND) && (v & avpn) != 0)) {
|
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stq_p(hpte, v & ~HPTE_V_HVLOCK); |
210 |
assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); |
211 |
return REMOVE_NOT_FOUND;
|
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} |
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*vp = v & ~HPTE_V_HVLOCK; |
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*rp = r; |
215 |
stq_p(hpte, 0);
|
216 |
rb = compute_tlbie_rb(v, r, ptex); |
217 |
ppc_tlb_invalidate_one(env, rb); |
218 |
assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); |
219 |
return REMOVE_SUCCESS;
|
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} |
221 |
|
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static target_ulong h_remove(CPUState *env, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
224 |
{ |
225 |
target_ulong flags = args[0];
|
226 |
target_ulong pte_index = args[1];
|
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target_ulong avpn = args[2];
|
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int ret;
|
229 |
|
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ret = remove_hpte(env, pte_index, avpn, flags, |
231 |
&args[0], &args[1]); |
232 |
|
233 |
switch (ret) {
|
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case REMOVE_SUCCESS:
|
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return H_SUCCESS;
|
236 |
|
237 |
case REMOVE_NOT_FOUND:
|
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return H_NOT_FOUND;
|
239 |
|
240 |
case REMOVE_PARM:
|
241 |
return H_PARAMETER;
|
242 |
|
243 |
case REMOVE_HW:
|
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return H_HARDWARE;
|
245 |
} |
246 |
|
247 |
assert(0);
|
248 |
} |
249 |
|
250 |
#define H_BULK_REMOVE_TYPE 0xc000000000000000ULL |
251 |
#define H_BULK_REMOVE_REQUEST 0x4000000000000000ULL |
252 |
#define H_BULK_REMOVE_RESPONSE 0x8000000000000000ULL |
253 |
#define H_BULK_REMOVE_END 0xc000000000000000ULL |
254 |
#define H_BULK_REMOVE_CODE 0x3000000000000000ULL |
255 |
#define H_BULK_REMOVE_SUCCESS 0x0000000000000000ULL |
256 |
#define H_BULK_REMOVE_NOT_FOUND 0x1000000000000000ULL |
257 |
#define H_BULK_REMOVE_PARM 0x2000000000000000ULL |
258 |
#define H_BULK_REMOVE_HW 0x3000000000000000ULL |
259 |
#define H_BULK_REMOVE_RC 0x0c00000000000000ULL |
260 |
#define H_BULK_REMOVE_FLAGS 0x0300000000000000ULL |
261 |
#define H_BULK_REMOVE_ABSOLUTE 0x0000000000000000ULL |
262 |
#define H_BULK_REMOVE_ANDCOND 0x0100000000000000ULL |
263 |
#define H_BULK_REMOVE_AVPN 0x0200000000000000ULL |
264 |
#define H_BULK_REMOVE_PTEX 0x00ffffffffffffffULL |
265 |
|
266 |
#define H_BULK_REMOVE_MAX_BATCH 4 |
267 |
|
268 |
static target_ulong h_bulk_remove(CPUState *env, sPAPREnvironment *spapr,
|
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target_ulong opcode, target_ulong *args) |
270 |
{ |
271 |
int i;
|
272 |
|
273 |
for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { |
274 |
target_ulong *tsh = &args[i*2];
|
275 |
target_ulong tsl = args[i*2 + 1]; |
276 |
target_ulong v, r, ret; |
277 |
|
278 |
if ((*tsh & H_BULK_REMOVE_TYPE) == H_BULK_REMOVE_END) {
|
279 |
break;
|
280 |
} else if ((*tsh & H_BULK_REMOVE_TYPE) != H_BULK_REMOVE_REQUEST) { |
281 |
return H_PARAMETER;
|
282 |
} |
283 |
|
284 |
*tsh &= H_BULK_REMOVE_PTEX | H_BULK_REMOVE_FLAGS; |
285 |
*tsh |= H_BULK_REMOVE_RESPONSE; |
286 |
|
287 |
if ((*tsh & H_BULK_REMOVE_ANDCOND) && (*tsh & H_BULK_REMOVE_AVPN)) {
|
288 |
*tsh |= H_BULK_REMOVE_PARM; |
289 |
return H_PARAMETER;
|
290 |
} |
291 |
|
292 |
ret = remove_hpte(env, *tsh & H_BULK_REMOVE_PTEX, tsl, |
293 |
(*tsh & H_BULK_REMOVE_FLAGS) >> 26,
|
294 |
&v, &r); |
295 |
|
296 |
*tsh |= ret << 60;
|
297 |
|
298 |
switch (ret) {
|
299 |
case REMOVE_SUCCESS:
|
300 |
*tsh |= (r & (HPTE_R_C | HPTE_R_R)) << 43;
|
301 |
break;
|
302 |
|
303 |
case REMOVE_PARM:
|
304 |
return H_PARAMETER;
|
305 |
|
306 |
case REMOVE_HW:
|
307 |
return H_HARDWARE;
|
308 |
} |
309 |
} |
310 |
|
311 |
return H_SUCCESS;
|
312 |
} |
313 |
|
314 |
static target_ulong h_protect(CPUState *env, sPAPREnvironment *spapr,
|
315 |
target_ulong opcode, target_ulong *args) |
316 |
{ |
317 |
target_ulong flags = args[0];
|
318 |
target_ulong pte_index = args[1];
|
319 |
target_ulong avpn = args[2];
|
320 |
uint8_t *hpte; |
321 |
target_ulong v, r, rb; |
322 |
|
323 |
if ((pte_index * HASH_PTE_SIZE_64) & ~env->htab_mask) {
|
324 |
return H_PARAMETER;
|
325 |
} |
326 |
|
327 |
hpte = env->external_htab + (pte_index * HASH_PTE_SIZE_64); |
328 |
while (!lock_hpte(hpte, HPTE_V_HVLOCK)) {
|
329 |
/* We have no real concurrency in qemu soft-emulation, so we
|
330 |
* will never actually have a contested lock */
|
331 |
assert(0);
|
332 |
} |
333 |
|
334 |
v = ldq_p(hpte); |
335 |
r = ldq_p(hpte + (HASH_PTE_SIZE_64/2));
|
336 |
|
337 |
if ((v & HPTE_V_VALID) == 0 || |
338 |
((flags & H_AVPN) && (v & ~0x7fULL) != avpn)) {
|
339 |
stq_p(hpte, v & ~HPTE_V_HVLOCK); |
340 |
assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); |
341 |
return H_NOT_FOUND;
|
342 |
} |
343 |
|
344 |
r &= ~(HPTE_R_PP0 | HPTE_R_PP | HPTE_R_N | |
345 |
HPTE_R_KEY_HI | HPTE_R_KEY_LO); |
346 |
r |= (flags << 55) & HPTE_R_PP0;
|
347 |
r |= (flags << 48) & HPTE_R_KEY_HI;
|
348 |
r |= flags & (HPTE_R_PP | HPTE_R_N | HPTE_R_KEY_LO); |
349 |
rb = compute_tlbie_rb(v, r, pte_index); |
350 |
stq_p(hpte, v & ~HPTE_V_VALID); |
351 |
ppc_tlb_invalidate_one(env, rb); |
352 |
stq_p(hpte + (HASH_PTE_SIZE_64/2), r);
|
353 |
/* Don't need a memory barrier, due to qemu's global lock */
|
354 |
stq_p(hpte, v & ~HPTE_V_HVLOCK); |
355 |
assert(!(ldq_p(hpte) & HPTE_V_HVLOCK)); |
356 |
return H_SUCCESS;
|
357 |
} |
358 |
|
359 |
static target_ulong h_set_dabr(CPUState *env, sPAPREnvironment *spapr,
|
360 |
target_ulong opcode, target_ulong *args) |
361 |
{ |
362 |
/* FIXME: actually implement this */
|
363 |
return H_HARDWARE;
|
364 |
} |
365 |
|
366 |
#define FLAGS_REGISTER_VPA 0x0000200000000000ULL |
367 |
#define FLAGS_REGISTER_DTL 0x0000400000000000ULL |
368 |
#define FLAGS_REGISTER_SLBSHADOW 0x0000600000000000ULL |
369 |
#define FLAGS_DEREGISTER_VPA 0x0000a00000000000ULL |
370 |
#define FLAGS_DEREGISTER_DTL 0x0000c00000000000ULL |
371 |
#define FLAGS_DEREGISTER_SLBSHADOW 0x0000e00000000000ULL |
372 |
|
373 |
#define VPA_MIN_SIZE 640 |
374 |
#define VPA_SIZE_OFFSET 0x4 |
375 |
#define VPA_SHARED_PROC_OFFSET 0x9 |
376 |
#define VPA_SHARED_PROC_VAL 0x2 |
377 |
|
378 |
static target_ulong register_vpa(CPUState *env, target_ulong vpa)
|
379 |
{ |
380 |
uint16_t size; |
381 |
uint8_t tmp; |
382 |
|
383 |
if (vpa == 0) { |
384 |
hcall_dprintf("Can't cope with registering a VPA at logical 0\n");
|
385 |
return H_HARDWARE;
|
386 |
} |
387 |
|
388 |
if (vpa % env->dcache_line_size) {
|
389 |
return H_PARAMETER;
|
390 |
} |
391 |
/* FIXME: bounds check the address */
|
392 |
|
393 |
size = lduw_be_phys(vpa + 0x4);
|
394 |
|
395 |
if (size < VPA_MIN_SIZE) {
|
396 |
return H_PARAMETER;
|
397 |
} |
398 |
|
399 |
/* VPA is not allowed to cross a page boundary */
|
400 |
if ((vpa / 4096) != ((vpa + size - 1) / 4096)) { |
401 |
return H_PARAMETER;
|
402 |
} |
403 |
|
404 |
env->vpa = vpa; |
405 |
|
406 |
tmp = ldub_phys(env->vpa + VPA_SHARED_PROC_OFFSET); |
407 |
tmp |= VPA_SHARED_PROC_VAL; |
408 |
stb_phys(env->vpa + VPA_SHARED_PROC_OFFSET, tmp); |
409 |
|
410 |
return H_SUCCESS;
|
411 |
} |
412 |
|
413 |
static target_ulong deregister_vpa(CPUState *env, target_ulong vpa)
|
414 |
{ |
415 |
if (env->slb_shadow) {
|
416 |
return H_RESOURCE;
|
417 |
} |
418 |
|
419 |
if (env->dispatch_trace_log) {
|
420 |
return H_RESOURCE;
|
421 |
} |
422 |
|
423 |
env->vpa = 0;
|
424 |
return H_SUCCESS;
|
425 |
} |
426 |
|
427 |
static target_ulong register_slb_shadow(CPUState *env, target_ulong addr)
|
428 |
{ |
429 |
uint32_t size; |
430 |
|
431 |
if (addr == 0) { |
432 |
hcall_dprintf("Can't cope with SLB shadow at logical 0\n");
|
433 |
return H_HARDWARE;
|
434 |
} |
435 |
|
436 |
size = ldl_be_phys(addr + 0x4);
|
437 |
if (size < 0x8) { |
438 |
return H_PARAMETER;
|
439 |
} |
440 |
|
441 |
if ((addr / 4096) != ((addr + size - 1) / 4096)) { |
442 |
return H_PARAMETER;
|
443 |
} |
444 |
|
445 |
if (!env->vpa) {
|
446 |
return H_RESOURCE;
|
447 |
} |
448 |
|
449 |
env->slb_shadow = addr; |
450 |
|
451 |
return H_SUCCESS;
|
452 |
} |
453 |
|
454 |
static target_ulong deregister_slb_shadow(CPUState *env, target_ulong addr)
|
455 |
{ |
456 |
env->slb_shadow = 0;
|
457 |
return H_SUCCESS;
|
458 |
} |
459 |
|
460 |
static target_ulong register_dtl(CPUState *env, target_ulong addr)
|
461 |
{ |
462 |
uint32_t size; |
463 |
|
464 |
if (addr == 0) { |
465 |
hcall_dprintf("Can't cope with DTL at logical 0\n");
|
466 |
return H_HARDWARE;
|
467 |
} |
468 |
|
469 |
size = ldl_be_phys(addr + 0x4);
|
470 |
|
471 |
if (size < 48) { |
472 |
return H_PARAMETER;
|
473 |
} |
474 |
|
475 |
if (!env->vpa) {
|
476 |
return H_RESOURCE;
|
477 |
} |
478 |
|
479 |
env->dispatch_trace_log = addr; |
480 |
env->dtl_size = size; |
481 |
|
482 |
return H_SUCCESS;
|
483 |
} |
484 |
|
485 |
static target_ulong deregister_dtl(CPUState *emv, target_ulong addr)
|
486 |
{ |
487 |
env->dispatch_trace_log = 0;
|
488 |
env->dtl_size = 0;
|
489 |
|
490 |
return H_SUCCESS;
|
491 |
} |
492 |
|
493 |
static target_ulong h_register_vpa(CPUState *env, sPAPREnvironment *spapr,
|
494 |
target_ulong opcode, target_ulong *args) |
495 |
{ |
496 |
target_ulong flags = args[0];
|
497 |
target_ulong procno = args[1];
|
498 |
target_ulong vpa = args[2];
|
499 |
target_ulong ret = H_PARAMETER; |
500 |
CPUState *tenv; |
501 |
|
502 |
for (tenv = first_cpu; tenv; tenv = tenv->next_cpu) {
|
503 |
if (tenv->cpu_index == procno) {
|
504 |
break;
|
505 |
} |
506 |
} |
507 |
|
508 |
if (!tenv) {
|
509 |
return H_PARAMETER;
|
510 |
} |
511 |
|
512 |
switch (flags) {
|
513 |
case FLAGS_REGISTER_VPA:
|
514 |
ret = register_vpa(tenv, vpa); |
515 |
break;
|
516 |
|
517 |
case FLAGS_DEREGISTER_VPA:
|
518 |
ret = deregister_vpa(tenv, vpa); |
519 |
break;
|
520 |
|
521 |
case FLAGS_REGISTER_SLBSHADOW:
|
522 |
ret = register_slb_shadow(tenv, vpa); |
523 |
break;
|
524 |
|
525 |
case FLAGS_DEREGISTER_SLBSHADOW:
|
526 |
ret = deregister_slb_shadow(tenv, vpa); |
527 |
break;
|
528 |
|
529 |
case FLAGS_REGISTER_DTL:
|
530 |
ret = register_dtl(tenv, vpa); |
531 |
break;
|
532 |
|
533 |
case FLAGS_DEREGISTER_DTL:
|
534 |
ret = deregister_dtl(tenv, vpa); |
535 |
break;
|
536 |
} |
537 |
|
538 |
return ret;
|
539 |
} |
540 |
|
541 |
static target_ulong h_cede(CPUState *env, sPAPREnvironment *spapr,
|
542 |
target_ulong opcode, target_ulong *args) |
543 |
{ |
544 |
env->msr |= (1ULL << MSR_EE);
|
545 |
hreg_compute_hflags(env); |
546 |
if (!cpu_has_work(env)) {
|
547 |
env->halted = 1;
|
548 |
} |
549 |
return H_SUCCESS;
|
550 |
} |
551 |
|
552 |
static target_ulong h_rtas(CPUState *env, sPAPREnvironment *spapr,
|
553 |
target_ulong opcode, target_ulong *args) |
554 |
{ |
555 |
target_ulong rtas_r3 = args[0];
|
556 |
uint32_t token = ldl_be_phys(rtas_r3); |
557 |
uint32_t nargs = ldl_be_phys(rtas_r3 + 4);
|
558 |
uint32_t nret = ldl_be_phys(rtas_r3 + 8);
|
559 |
|
560 |
return spapr_rtas_call(spapr, token, nargs, rtas_r3 + 12, |
561 |
nret, rtas_r3 + 12 + 4*nargs); |
562 |
} |
563 |
|
564 |
static target_ulong h_logical_load(CPUState *env, sPAPREnvironment *spapr,
|
565 |
target_ulong opcode, target_ulong *args) |
566 |
{ |
567 |
target_ulong size = args[0];
|
568 |
target_ulong addr = args[1];
|
569 |
|
570 |
switch (size) {
|
571 |
case 1: |
572 |
args[0] = ldub_phys(addr);
|
573 |
return H_SUCCESS;
|
574 |
case 2: |
575 |
args[0] = lduw_phys(addr);
|
576 |
return H_SUCCESS;
|
577 |
case 4: |
578 |
args[0] = ldl_phys(addr);
|
579 |
return H_SUCCESS;
|
580 |
case 8: |
581 |
args[0] = ldq_phys(addr);
|
582 |
return H_SUCCESS;
|
583 |
} |
584 |
return H_PARAMETER;
|
585 |
} |
586 |
|
587 |
static target_ulong h_logical_store(CPUState *env, sPAPREnvironment *spapr,
|
588 |
target_ulong opcode, target_ulong *args) |
589 |
{ |
590 |
target_ulong size = args[0];
|
591 |
target_ulong addr = args[1];
|
592 |
target_ulong val = args[2];
|
593 |
|
594 |
switch (size) {
|
595 |
case 1: |
596 |
stb_phys(addr, val); |
597 |
return H_SUCCESS;
|
598 |
case 2: |
599 |
stw_phys(addr, val); |
600 |
return H_SUCCESS;
|
601 |
case 4: |
602 |
stl_phys(addr, val); |
603 |
return H_SUCCESS;
|
604 |
case 8: |
605 |
stq_phys(addr, val); |
606 |
return H_SUCCESS;
|
607 |
} |
608 |
return H_PARAMETER;
|
609 |
} |
610 |
|
611 |
static target_ulong h_logical_icbi(CPUState *env, sPAPREnvironment *spapr,
|
612 |
target_ulong opcode, target_ulong *args) |
613 |
{ |
614 |
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
615 |
return H_SUCCESS;
|
616 |
} |
617 |
|
618 |
static target_ulong h_logical_dcbf(CPUState *env, sPAPREnvironment *spapr,
|
619 |
target_ulong opcode, target_ulong *args) |
620 |
{ |
621 |
/* Nothing to do on emulation, KVM will trap this in the kernel */
|
622 |
return H_SUCCESS;
|
623 |
} |
624 |
|
625 |
static spapr_hcall_fn papr_hypercall_table[(MAX_HCALL_OPCODE / 4) + 1]; |
626 |
static spapr_hcall_fn kvmppc_hypercall_table[KVMPPC_HCALL_MAX - KVMPPC_HCALL_BASE + 1]; |
627 |
|
628 |
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
|
629 |
{ |
630 |
spapr_hcall_fn *slot; |
631 |
|
632 |
if (opcode <= MAX_HCALL_OPCODE) {
|
633 |
assert((opcode & 0x3) == 0); |
634 |
|
635 |
slot = &papr_hypercall_table[opcode / 4];
|
636 |
} else {
|
637 |
assert((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)); |
638 |
|
639 |
|
640 |
slot = &kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
641 |
} |
642 |
|
643 |
assert(!(*slot) || (fn == *slot)); |
644 |
*slot = fn; |
645 |
} |
646 |
|
647 |
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode, |
648 |
target_ulong *args) |
649 |
{ |
650 |
if (msr_pr) {
|
651 |
hcall_dprintf("Hypercall made with MSR[PR]=1\n");
|
652 |
return H_PRIVILEGE;
|
653 |
} |
654 |
|
655 |
if ((opcode <= MAX_HCALL_OPCODE)
|
656 |
&& ((opcode & 0x3) == 0)) { |
657 |
spapr_hcall_fn fn = papr_hypercall_table[opcode / 4];
|
658 |
|
659 |
if (fn) {
|
660 |
return fn(env, spapr, opcode, args);
|
661 |
} |
662 |
} else if ((opcode >= KVMPPC_HCALL_BASE) && |
663 |
(opcode <= KVMPPC_HCALL_MAX)) { |
664 |
spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; |
665 |
|
666 |
if (fn) {
|
667 |
return fn(env, spapr, opcode, args);
|
668 |
} |
669 |
} |
670 |
|
671 |
hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode); |
672 |
return H_FUNCTION;
|
673 |
} |
674 |
|
675 |
static void hypercall_init(void) |
676 |
{ |
677 |
/* hcall-pft */
|
678 |
spapr_register_hypercall(H_ENTER, h_enter); |
679 |
spapr_register_hypercall(H_REMOVE, h_remove); |
680 |
spapr_register_hypercall(H_PROTECT, h_protect); |
681 |
|
682 |
/* hcall-bulk */
|
683 |
spapr_register_hypercall(H_BULK_REMOVE, h_bulk_remove); |
684 |
|
685 |
/* hcall-dabr */
|
686 |
spapr_register_hypercall(H_SET_DABR, h_set_dabr); |
687 |
|
688 |
/* hcall-splpar */
|
689 |
spapr_register_hypercall(H_REGISTER_VPA, h_register_vpa); |
690 |
spapr_register_hypercall(H_CEDE, h_cede); |
691 |
|
692 |
/* "debugger" hcalls (also used by SLOF). Note: We do -not- differenciate
|
693 |
* here between the "CI" and the "CACHE" variants, they will use whatever
|
694 |
* mapping attributes qemu is using. When using KVM, the kernel will
|
695 |
* enforce the attributes more strongly
|
696 |
*/
|
697 |
spapr_register_hypercall(H_LOGICAL_CI_LOAD, h_logical_load); |
698 |
spapr_register_hypercall(H_LOGICAL_CI_STORE, h_logical_store); |
699 |
spapr_register_hypercall(H_LOGICAL_CACHE_LOAD, h_logical_load); |
700 |
spapr_register_hypercall(H_LOGICAL_CACHE_STORE, h_logical_store); |
701 |
spapr_register_hypercall(H_LOGICAL_ICBI, h_logical_icbi); |
702 |
spapr_register_hypercall(H_LOGICAL_DCBF, h_logical_dcbf); |
703 |
|
704 |
/* qemu/KVM-PPC specific hcalls */
|
705 |
spapr_register_hypercall(KVMPPC_H_RTAS, h_rtas); |
706 |
} |
707 |
device_init(hypercall_init); |