root / cpu-all.h @ 0497d2f4
History | View | Annotate | Download (29.2 kB)
1 | 5a9fdfec | bellard | /*
|
---|---|---|---|
2 | 5a9fdfec | bellard | * defines common to all virtual CPUs
|
3 | 5fafdf24 | ths | *
|
4 | 5a9fdfec | bellard | * Copyright (c) 2003 Fabrice Bellard
|
5 | 5a9fdfec | bellard | *
|
6 | 5a9fdfec | bellard | * This library is free software; you can redistribute it and/or
|
7 | 5a9fdfec | bellard | * modify it under the terms of the GNU Lesser General Public
|
8 | 5a9fdfec | bellard | * License as published by the Free Software Foundation; either
|
9 | 5a9fdfec | bellard | * version 2 of the License, or (at your option) any later version.
|
10 | 5a9fdfec | bellard | *
|
11 | 5a9fdfec | bellard | * This library is distributed in the hope that it will be useful,
|
12 | 5a9fdfec | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
|
13 | 5a9fdfec | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
14 | 5a9fdfec | bellard | * Lesser General Public License for more details.
|
15 | 5a9fdfec | bellard | *
|
16 | 5a9fdfec | bellard | * You should have received a copy of the GNU Lesser General Public
|
17 | 5a9fdfec | bellard | * License along with this library; if not, write to the Free Software
|
18 | fad6cb1a | aurel32 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
|
19 | 5a9fdfec | bellard | */
|
20 | 5a9fdfec | bellard | #ifndef CPU_ALL_H
|
21 | 5a9fdfec | bellard | #define CPU_ALL_H
|
22 | 5a9fdfec | bellard | |
23 | 7d99a001 | blueswir1 | #include "qemu-common.h" |
24 | 7d99a001 | blueswir1 | |
25 | f54b3f92 | aurel32 | #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__)
|
26 | 0ac4bd56 | bellard | #define WORDS_ALIGNED
|
27 | 0ac4bd56 | bellard | #endif
|
28 | 0ac4bd56 | bellard | |
29 | 5fafdf24 | ths | /* some important defines:
|
30 | 5fafdf24 | ths | *
|
31 | 0ac4bd56 | bellard | * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
|
32 | 0ac4bd56 | bellard | * memory accesses.
|
33 | 5fafdf24 | ths | *
|
34 | 0ac4bd56 | bellard | * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
|
35 | 0ac4bd56 | bellard | * otherwise little endian.
|
36 | 5fafdf24 | ths | *
|
37 | 0ac4bd56 | bellard | * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
|
38 | 5fafdf24 | ths | *
|
39 | 0ac4bd56 | bellard | * TARGET_WORDS_BIGENDIAN : same for target cpu
|
40 | 0ac4bd56 | bellard | */
|
41 | 0ac4bd56 | bellard | |
42 | f193c797 | bellard | #include "bswap.h" |
43 | 939ef593 | aurel32 | #include "softfloat.h" |
44 | f193c797 | bellard | |
45 | f193c797 | bellard | #if defined(WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
|
46 | f193c797 | bellard | #define BSWAP_NEEDED
|
47 | f193c797 | bellard | #endif
|
48 | f193c797 | bellard | |
49 | f193c797 | bellard | #ifdef BSWAP_NEEDED
|
50 | f193c797 | bellard | |
51 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
52 | f193c797 | bellard | { |
53 | f193c797 | bellard | return bswap16(s);
|
54 | f193c797 | bellard | } |
55 | f193c797 | bellard | |
56 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
57 | f193c797 | bellard | { |
58 | f193c797 | bellard | return bswap32(s);
|
59 | f193c797 | bellard | } |
60 | f193c797 | bellard | |
61 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
62 | f193c797 | bellard | { |
63 | f193c797 | bellard | return bswap64(s);
|
64 | f193c797 | bellard | } |
65 | f193c797 | bellard | |
66 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
67 | f193c797 | bellard | { |
68 | f193c797 | bellard | *s = bswap16(*s); |
69 | f193c797 | bellard | } |
70 | f193c797 | bellard | |
71 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
72 | f193c797 | bellard | { |
73 | f193c797 | bellard | *s = bswap32(*s); |
74 | f193c797 | bellard | } |
75 | f193c797 | bellard | |
76 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
77 | f193c797 | bellard | { |
78 | f193c797 | bellard | *s = bswap64(*s); |
79 | f193c797 | bellard | } |
80 | f193c797 | bellard | |
81 | f193c797 | bellard | #else
|
82 | f193c797 | bellard | |
83 | f193c797 | bellard | static inline uint16_t tswap16(uint16_t s) |
84 | f193c797 | bellard | { |
85 | f193c797 | bellard | return s;
|
86 | f193c797 | bellard | } |
87 | f193c797 | bellard | |
88 | f193c797 | bellard | static inline uint32_t tswap32(uint32_t s) |
89 | f193c797 | bellard | { |
90 | f193c797 | bellard | return s;
|
91 | f193c797 | bellard | } |
92 | f193c797 | bellard | |
93 | f193c797 | bellard | static inline uint64_t tswap64(uint64_t s) |
94 | f193c797 | bellard | { |
95 | f193c797 | bellard | return s;
|
96 | f193c797 | bellard | } |
97 | f193c797 | bellard | |
98 | f193c797 | bellard | static inline void tswap16s(uint16_t *s) |
99 | f193c797 | bellard | { |
100 | f193c797 | bellard | } |
101 | f193c797 | bellard | |
102 | f193c797 | bellard | static inline void tswap32s(uint32_t *s) |
103 | f193c797 | bellard | { |
104 | f193c797 | bellard | } |
105 | f193c797 | bellard | |
106 | f193c797 | bellard | static inline void tswap64s(uint64_t *s) |
107 | f193c797 | bellard | { |
108 | f193c797 | bellard | } |
109 | f193c797 | bellard | |
110 | f193c797 | bellard | #endif
|
111 | f193c797 | bellard | |
112 | f193c797 | bellard | #if TARGET_LONG_SIZE == 4 |
113 | f193c797 | bellard | #define tswapl(s) tswap32(s)
|
114 | f193c797 | bellard | #define tswapls(s) tswap32s((uint32_t *)(s))
|
115 | 0a962c02 | bellard | #define bswaptls(s) bswap32s(s)
|
116 | f193c797 | bellard | #else
|
117 | f193c797 | bellard | #define tswapl(s) tswap64(s)
|
118 | f193c797 | bellard | #define tswapls(s) tswap64s((uint64_t *)(s))
|
119 | 0a962c02 | bellard | #define bswaptls(s) bswap64s(s)
|
120 | f193c797 | bellard | #endif
|
121 | f193c797 | bellard | |
122 | 0ca9d380 | aurel32 | typedef union { |
123 | 0ca9d380 | aurel32 | float32 f; |
124 | 0ca9d380 | aurel32 | uint32_t l; |
125 | 0ca9d380 | aurel32 | } CPU_FloatU; |
126 | 0ca9d380 | aurel32 | |
127 | 832ed0fa | bellard | /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
|
128 | 832ed0fa | bellard | endian ! */
|
129 | 0ac4bd56 | bellard | typedef union { |
130 | 53cd6637 | bellard | float64 d; |
131 | 9d60cac0 | bellard | #if defined(WORDS_BIGENDIAN) \
|
132 | 9d60cac0 | bellard | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
133 | 0ac4bd56 | bellard | struct {
|
134 | 0ac4bd56 | bellard | uint32_t upper; |
135 | 832ed0fa | bellard | uint32_t lower; |
136 | 0ac4bd56 | bellard | } l; |
137 | 0ac4bd56 | bellard | #else
|
138 | 0ac4bd56 | bellard | struct {
|
139 | 0ac4bd56 | bellard | uint32_t lower; |
140 | 832ed0fa | bellard | uint32_t upper; |
141 | 0ac4bd56 | bellard | } l; |
142 | 0ac4bd56 | bellard | #endif
|
143 | 0ac4bd56 | bellard | uint64_t ll; |
144 | 0ac4bd56 | bellard | } CPU_DoubleU; |
145 | 0ac4bd56 | bellard | |
146 | 1f587329 | blueswir1 | #ifdef TARGET_SPARC
|
147 | 1f587329 | blueswir1 | typedef union { |
148 | 1f587329 | blueswir1 | float128 q; |
149 | 1f587329 | blueswir1 | #if defined(WORDS_BIGENDIAN) \
|
150 | 1f587329 | blueswir1 | || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT)) |
151 | 1f587329 | blueswir1 | struct {
|
152 | 1f587329 | blueswir1 | uint32_t upmost; |
153 | 1f587329 | blueswir1 | uint32_t upper; |
154 | 1f587329 | blueswir1 | uint32_t lower; |
155 | 1f587329 | blueswir1 | uint32_t lowest; |
156 | 1f587329 | blueswir1 | } l; |
157 | 1f587329 | blueswir1 | struct {
|
158 | 1f587329 | blueswir1 | uint64_t upper; |
159 | 1f587329 | blueswir1 | uint64_t lower; |
160 | 1f587329 | blueswir1 | } ll; |
161 | 1f587329 | blueswir1 | #else
|
162 | 1f587329 | blueswir1 | struct {
|
163 | 1f587329 | blueswir1 | uint32_t lowest; |
164 | 1f587329 | blueswir1 | uint32_t lower; |
165 | 1f587329 | blueswir1 | uint32_t upper; |
166 | 1f587329 | blueswir1 | uint32_t upmost; |
167 | 1f587329 | blueswir1 | } l; |
168 | 1f587329 | blueswir1 | struct {
|
169 | 1f587329 | blueswir1 | uint64_t lower; |
170 | 1f587329 | blueswir1 | uint64_t upper; |
171 | 1f587329 | blueswir1 | } ll; |
172 | 1f587329 | blueswir1 | #endif
|
173 | 1f587329 | blueswir1 | } CPU_QuadU; |
174 | 1f587329 | blueswir1 | #endif
|
175 | 1f587329 | blueswir1 | |
176 | 61382a50 | bellard | /* CPU memory access without any memory or io remapping */
|
177 | 61382a50 | bellard | |
178 | 83d73968 | bellard | /*
|
179 | 83d73968 | bellard | * the generic syntax for the memory accesses is:
|
180 | 83d73968 | bellard | *
|
181 | 83d73968 | bellard | * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
|
182 | 83d73968 | bellard | *
|
183 | 83d73968 | bellard | * store: st{type}{size}{endian}_{access_type}(ptr, val)
|
184 | 83d73968 | bellard | *
|
185 | 83d73968 | bellard | * type is:
|
186 | 83d73968 | bellard | * (empty): integer access
|
187 | 83d73968 | bellard | * f : float access
|
188 | 5fafdf24 | ths | *
|
189 | 83d73968 | bellard | * sign is:
|
190 | 83d73968 | bellard | * (empty): for floats or 32 bit size
|
191 | 83d73968 | bellard | * u : unsigned
|
192 | 83d73968 | bellard | * s : signed
|
193 | 83d73968 | bellard | *
|
194 | 83d73968 | bellard | * size is:
|
195 | 83d73968 | bellard | * b: 8 bits
|
196 | 83d73968 | bellard | * w: 16 bits
|
197 | 83d73968 | bellard | * l: 32 bits
|
198 | 83d73968 | bellard | * q: 64 bits
|
199 | 5fafdf24 | ths | *
|
200 | 83d73968 | bellard | * endian is:
|
201 | 83d73968 | bellard | * (empty): target cpu endianness or 8 bit access
|
202 | 83d73968 | bellard | * r : reversed target cpu endianness (not implemented yet)
|
203 | 83d73968 | bellard | * be : big endian (not implemented yet)
|
204 | 83d73968 | bellard | * le : little endian (not implemented yet)
|
205 | 83d73968 | bellard | *
|
206 | 83d73968 | bellard | * access_type is:
|
207 | 83d73968 | bellard | * raw : host memory access
|
208 | 83d73968 | bellard | * user : user mode access using soft MMU
|
209 | 83d73968 | bellard | * kernel : kernel mode access using soft MMU
|
210 | 83d73968 | bellard | */
|
211 | 8bba3ea1 | balrog | static inline int ldub_p(const void *ptr) |
212 | 5a9fdfec | bellard | { |
213 | 5a9fdfec | bellard | return *(uint8_t *)ptr;
|
214 | 5a9fdfec | bellard | } |
215 | 5a9fdfec | bellard | |
216 | 8bba3ea1 | balrog | static inline int ldsb_p(const void *ptr) |
217 | 5a9fdfec | bellard | { |
218 | 5a9fdfec | bellard | return *(int8_t *)ptr;
|
219 | 5a9fdfec | bellard | } |
220 | 5a9fdfec | bellard | |
221 | c27004ec | bellard | static inline void stb_p(void *ptr, int v) |
222 | 5a9fdfec | bellard | { |
223 | 5a9fdfec | bellard | *(uint8_t *)ptr = v; |
224 | 5a9fdfec | bellard | } |
225 | 5a9fdfec | bellard | |
226 | 5a9fdfec | bellard | /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
|
227 | 5a9fdfec | bellard | kernel handles unaligned load/stores may give better results, but
|
228 | 5a9fdfec | bellard | it is a system wide setting : bad */
|
229 | 2df3b95d | bellard | #if defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
|
230 | 5a9fdfec | bellard | |
231 | 5a9fdfec | bellard | /* conservative code for little endian unaligned accesses */
|
232 | 8bba3ea1 | balrog | static inline int lduw_le_p(const void *ptr) |
233 | 5a9fdfec | bellard | { |
234 | e58ffeb3 | malc | #ifdef _ARCH_PPC
|
235 | 5a9fdfec | bellard | int val;
|
236 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
237 | 5a9fdfec | bellard | return val;
|
238 | 5a9fdfec | bellard | #else
|
239 | e01fe6d5 | malc | const uint8_t *p = ptr;
|
240 | 5a9fdfec | bellard | return p[0] | (p[1] << 8); |
241 | 5a9fdfec | bellard | #endif
|
242 | 5a9fdfec | bellard | } |
243 | 5a9fdfec | bellard | |
244 | 8bba3ea1 | balrog | static inline int ldsw_le_p(const void *ptr) |
245 | 5a9fdfec | bellard | { |
246 | e58ffeb3 | malc | #ifdef _ARCH_PPC
|
247 | 5a9fdfec | bellard | int val;
|
248 | 5a9fdfec | bellard | __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
249 | 5a9fdfec | bellard | return (int16_t)val;
|
250 | 5a9fdfec | bellard | #else
|
251 | e01fe6d5 | malc | const uint8_t *p = ptr;
|
252 | 5a9fdfec | bellard | return (int16_t)(p[0] | (p[1] << 8)); |
253 | 5a9fdfec | bellard | #endif
|
254 | 5a9fdfec | bellard | } |
255 | 5a9fdfec | bellard | |
256 | 8bba3ea1 | balrog | static inline int ldl_le_p(const void *ptr) |
257 | 5a9fdfec | bellard | { |
258 | e58ffeb3 | malc | #ifdef _ARCH_PPC
|
259 | 5a9fdfec | bellard | int val;
|
260 | 5a9fdfec | bellard | __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr)); |
261 | 5a9fdfec | bellard | return val;
|
262 | 5a9fdfec | bellard | #else
|
263 | e01fe6d5 | malc | const uint8_t *p = ptr;
|
264 | 5a9fdfec | bellard | return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); |
265 | 5a9fdfec | bellard | #endif
|
266 | 5a9fdfec | bellard | } |
267 | 5a9fdfec | bellard | |
268 | 8bba3ea1 | balrog | static inline uint64_t ldq_le_p(const void *ptr) |
269 | 5a9fdfec | bellard | { |
270 | e01fe6d5 | malc | const uint8_t *p = ptr;
|
271 | 5a9fdfec | bellard | uint32_t v1, v2; |
272 | f0aca822 | bellard | v1 = ldl_le_p(p); |
273 | f0aca822 | bellard | v2 = ldl_le_p(p + 4);
|
274 | 5a9fdfec | bellard | return v1 | ((uint64_t)v2 << 32); |
275 | 5a9fdfec | bellard | } |
276 | 5a9fdfec | bellard | |
277 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
278 | 5a9fdfec | bellard | { |
279 | e58ffeb3 | malc | #ifdef _ARCH_PPC
|
280 | 5a9fdfec | bellard | __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr)); |
281 | 5a9fdfec | bellard | #else
|
282 | 5a9fdfec | bellard | uint8_t *p = ptr; |
283 | 5a9fdfec | bellard | p[0] = v;
|
284 | 5a9fdfec | bellard | p[1] = v >> 8; |
285 | 5a9fdfec | bellard | #endif
|
286 | 5a9fdfec | bellard | } |
287 | 5a9fdfec | bellard | |
288 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
289 | 5a9fdfec | bellard | { |
290 | e58ffeb3 | malc | #ifdef _ARCH_PPC
|
291 | 5a9fdfec | bellard | __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr)); |
292 | 5a9fdfec | bellard | #else
|
293 | 5a9fdfec | bellard | uint8_t *p = ptr; |
294 | 5a9fdfec | bellard | p[0] = v;
|
295 | 5a9fdfec | bellard | p[1] = v >> 8; |
296 | 5a9fdfec | bellard | p[2] = v >> 16; |
297 | 5a9fdfec | bellard | p[3] = v >> 24; |
298 | 5a9fdfec | bellard | #endif
|
299 | 5a9fdfec | bellard | } |
300 | 5a9fdfec | bellard | |
301 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
302 | 5a9fdfec | bellard | { |
303 | 5a9fdfec | bellard | uint8_t *p = ptr; |
304 | f0aca822 | bellard | stl_le_p(p, (uint32_t)v); |
305 | f0aca822 | bellard | stl_le_p(p + 4, v >> 32); |
306 | 5a9fdfec | bellard | } |
307 | 5a9fdfec | bellard | |
308 | 5a9fdfec | bellard | /* float access */
|
309 | 5a9fdfec | bellard | |
310 | 8bba3ea1 | balrog | static inline float32 ldfl_le_p(const void *ptr) |
311 | 5a9fdfec | bellard | { |
312 | 5a9fdfec | bellard | union {
|
313 | 53cd6637 | bellard | float32 f; |
314 | 5a9fdfec | bellard | uint32_t i; |
315 | 5a9fdfec | bellard | } u; |
316 | 2df3b95d | bellard | u.i = ldl_le_p(ptr); |
317 | 5a9fdfec | bellard | return u.f;
|
318 | 5a9fdfec | bellard | } |
319 | 5a9fdfec | bellard | |
320 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
321 | 5a9fdfec | bellard | { |
322 | 5a9fdfec | bellard | union {
|
323 | 53cd6637 | bellard | float32 f; |
324 | 5a9fdfec | bellard | uint32_t i; |
325 | 5a9fdfec | bellard | } u; |
326 | 5a9fdfec | bellard | u.f = v; |
327 | 2df3b95d | bellard | stl_le_p(ptr, u.i); |
328 | 5a9fdfec | bellard | } |
329 | 5a9fdfec | bellard | |
330 | 8bba3ea1 | balrog | static inline float64 ldfq_le_p(const void *ptr) |
331 | 5a9fdfec | bellard | { |
332 | 0ac4bd56 | bellard | CPU_DoubleU u; |
333 | 2df3b95d | bellard | u.l.lower = ldl_le_p(ptr); |
334 | 2df3b95d | bellard | u.l.upper = ldl_le_p(ptr + 4);
|
335 | 5a9fdfec | bellard | return u.d;
|
336 | 5a9fdfec | bellard | } |
337 | 5a9fdfec | bellard | |
338 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
339 | 5a9fdfec | bellard | { |
340 | 0ac4bd56 | bellard | CPU_DoubleU u; |
341 | 5a9fdfec | bellard | u.d = v; |
342 | 2df3b95d | bellard | stl_le_p(ptr, u.l.lower); |
343 | 2df3b95d | bellard | stl_le_p(ptr + 4, u.l.upper);
|
344 | 5a9fdfec | bellard | } |
345 | 5a9fdfec | bellard | |
346 | 2df3b95d | bellard | #else
|
347 | 2df3b95d | bellard | |
348 | 8bba3ea1 | balrog | static inline int lduw_le_p(const void *ptr) |
349 | 2df3b95d | bellard | { |
350 | 2df3b95d | bellard | return *(uint16_t *)ptr;
|
351 | 2df3b95d | bellard | } |
352 | 2df3b95d | bellard | |
353 | 8bba3ea1 | balrog | static inline int ldsw_le_p(const void *ptr) |
354 | 2df3b95d | bellard | { |
355 | 2df3b95d | bellard | return *(int16_t *)ptr;
|
356 | 2df3b95d | bellard | } |
357 | 93ac68bc | bellard | |
358 | 8bba3ea1 | balrog | static inline int ldl_le_p(const void *ptr) |
359 | 2df3b95d | bellard | { |
360 | 2df3b95d | bellard | return *(uint32_t *)ptr;
|
361 | 2df3b95d | bellard | } |
362 | 2df3b95d | bellard | |
363 | 8bba3ea1 | balrog | static inline uint64_t ldq_le_p(const void *ptr) |
364 | 2df3b95d | bellard | { |
365 | 2df3b95d | bellard | return *(uint64_t *)ptr;
|
366 | 2df3b95d | bellard | } |
367 | 2df3b95d | bellard | |
368 | 2df3b95d | bellard | static inline void stw_le_p(void *ptr, int v) |
369 | 2df3b95d | bellard | { |
370 | 2df3b95d | bellard | *(uint16_t *)ptr = v; |
371 | 2df3b95d | bellard | } |
372 | 2df3b95d | bellard | |
373 | 2df3b95d | bellard | static inline void stl_le_p(void *ptr, int v) |
374 | 2df3b95d | bellard | { |
375 | 2df3b95d | bellard | *(uint32_t *)ptr = v; |
376 | 2df3b95d | bellard | } |
377 | 2df3b95d | bellard | |
378 | 2df3b95d | bellard | static inline void stq_le_p(void *ptr, uint64_t v) |
379 | 2df3b95d | bellard | { |
380 | 2df3b95d | bellard | *(uint64_t *)ptr = v; |
381 | 2df3b95d | bellard | } |
382 | 2df3b95d | bellard | |
383 | 2df3b95d | bellard | /* float access */
|
384 | 2df3b95d | bellard | |
385 | 8bba3ea1 | balrog | static inline float32 ldfl_le_p(const void *ptr) |
386 | 2df3b95d | bellard | { |
387 | 2df3b95d | bellard | return *(float32 *)ptr;
|
388 | 2df3b95d | bellard | } |
389 | 2df3b95d | bellard | |
390 | 8bba3ea1 | balrog | static inline float64 ldfq_le_p(const void *ptr) |
391 | 2df3b95d | bellard | { |
392 | 2df3b95d | bellard | return *(float64 *)ptr;
|
393 | 2df3b95d | bellard | } |
394 | 2df3b95d | bellard | |
395 | 2df3b95d | bellard | static inline void stfl_le_p(void *ptr, float32 v) |
396 | 2df3b95d | bellard | { |
397 | 2df3b95d | bellard | *(float32 *)ptr = v; |
398 | 2df3b95d | bellard | } |
399 | 2df3b95d | bellard | |
400 | 2df3b95d | bellard | static inline void stfq_le_p(void *ptr, float64 v) |
401 | 2df3b95d | bellard | { |
402 | 2df3b95d | bellard | *(float64 *)ptr = v; |
403 | 2df3b95d | bellard | } |
404 | 2df3b95d | bellard | #endif
|
405 | 2df3b95d | bellard | |
406 | 2df3b95d | bellard | #if !defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
|
407 | 2df3b95d | bellard | |
408 | 8bba3ea1 | balrog | static inline int lduw_be_p(const void *ptr) |
409 | 93ac68bc | bellard | { |
410 | 83d73968 | bellard | #if defined(__i386__)
|
411 | 83d73968 | bellard | int val;
|
412 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
413 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
414 | 83d73968 | bellard | : "=q" (val)
|
415 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
416 | 83d73968 | bellard | return val;
|
417 | 83d73968 | bellard | #else
|
418 | e01fe6d5 | malc | const uint8_t *b = ptr;
|
419 | 83d73968 | bellard | return ((b[0] << 8) | b[1]); |
420 | 83d73968 | bellard | #endif
|
421 | 93ac68bc | bellard | } |
422 | 93ac68bc | bellard | |
423 | 8bba3ea1 | balrog | static inline int ldsw_be_p(const void *ptr) |
424 | 93ac68bc | bellard | { |
425 | 83d73968 | bellard | #if defined(__i386__)
|
426 | 83d73968 | bellard | int val;
|
427 | 83d73968 | bellard | asm volatile ("movzwl %1, %0\n" |
428 | 83d73968 | bellard | "xchgb %b0, %h0\n"
|
429 | 83d73968 | bellard | : "=q" (val)
|
430 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr));
|
431 | 83d73968 | bellard | return (int16_t)val;
|
432 | 83d73968 | bellard | #else
|
433 | e01fe6d5 | malc | const uint8_t *b = ptr;
|
434 | 83d73968 | bellard | return (int16_t)((b[0] << 8) | b[1]); |
435 | 83d73968 | bellard | #endif
|
436 | 93ac68bc | bellard | } |
437 | 93ac68bc | bellard | |
438 | 8bba3ea1 | balrog | static inline int ldl_be_p(const void *ptr) |
439 | 93ac68bc | bellard | { |
440 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
441 | 83d73968 | bellard | int val;
|
442 | 83d73968 | bellard | asm volatile ("movl %1, %0\n" |
443 | 83d73968 | bellard | "bswap %0\n"
|
444 | 83d73968 | bellard | : "=r" (val)
|
445 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr));
|
446 | 83d73968 | bellard | return val;
|
447 | 83d73968 | bellard | #else
|
448 | e01fe6d5 | malc | const uint8_t *b = ptr;
|
449 | 83d73968 | bellard | return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3]; |
450 | 83d73968 | bellard | #endif
|
451 | 93ac68bc | bellard | } |
452 | 93ac68bc | bellard | |
453 | 8bba3ea1 | balrog | static inline uint64_t ldq_be_p(const void *ptr) |
454 | 93ac68bc | bellard | { |
455 | 93ac68bc | bellard | uint32_t a,b; |
456 | 2df3b95d | bellard | a = ldl_be_p(ptr); |
457 | 4d7a0880 | blueswir1 | b = ldl_be_p((uint8_t *)ptr + 4);
|
458 | 93ac68bc | bellard | return (((uint64_t)a<<32)|b); |
459 | 93ac68bc | bellard | } |
460 | 93ac68bc | bellard | |
461 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
462 | 93ac68bc | bellard | { |
463 | 83d73968 | bellard | #if defined(__i386__)
|
464 | 83d73968 | bellard | asm volatile ("xchgb %b0, %h0\n" |
465 | 83d73968 | bellard | "movw %w0, %1\n"
|
466 | 83d73968 | bellard | : "=q" (v)
|
467 | 83d73968 | bellard | : "m" (*(uint16_t *)ptr), "0" (v)); |
468 | 83d73968 | bellard | #else
|
469 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
470 | 93ac68bc | bellard | d[0] = v >> 8; |
471 | 93ac68bc | bellard | d[1] = v;
|
472 | 83d73968 | bellard | #endif
|
473 | 93ac68bc | bellard | } |
474 | 93ac68bc | bellard | |
475 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
476 | 93ac68bc | bellard | { |
477 | 4f2ac237 | bellard | #if defined(__i386__) || defined(__x86_64__)
|
478 | 83d73968 | bellard | asm volatile ("bswap %0\n" |
479 | 83d73968 | bellard | "movl %0, %1\n"
|
480 | 83d73968 | bellard | : "=r" (v)
|
481 | 83d73968 | bellard | : "m" (*(uint32_t *)ptr), "0" (v)); |
482 | 83d73968 | bellard | #else
|
483 | 93ac68bc | bellard | uint8_t *d = (uint8_t *) ptr; |
484 | 93ac68bc | bellard | d[0] = v >> 24; |
485 | 93ac68bc | bellard | d[1] = v >> 16; |
486 | 93ac68bc | bellard | d[2] = v >> 8; |
487 | 93ac68bc | bellard | d[3] = v;
|
488 | 83d73968 | bellard | #endif
|
489 | 93ac68bc | bellard | } |
490 | 93ac68bc | bellard | |
491 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
492 | 93ac68bc | bellard | { |
493 | 2df3b95d | bellard | stl_be_p(ptr, v >> 32);
|
494 | 4d7a0880 | blueswir1 | stl_be_p((uint8_t *)ptr + 4, v);
|
495 | 0ac4bd56 | bellard | } |
496 | 0ac4bd56 | bellard | |
497 | 0ac4bd56 | bellard | /* float access */
|
498 | 0ac4bd56 | bellard | |
499 | 8bba3ea1 | balrog | static inline float32 ldfl_be_p(const void *ptr) |
500 | 0ac4bd56 | bellard | { |
501 | 0ac4bd56 | bellard | union {
|
502 | 53cd6637 | bellard | float32 f; |
503 | 0ac4bd56 | bellard | uint32_t i; |
504 | 0ac4bd56 | bellard | } u; |
505 | 2df3b95d | bellard | u.i = ldl_be_p(ptr); |
506 | 0ac4bd56 | bellard | return u.f;
|
507 | 0ac4bd56 | bellard | } |
508 | 0ac4bd56 | bellard | |
509 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
510 | 0ac4bd56 | bellard | { |
511 | 0ac4bd56 | bellard | union {
|
512 | 53cd6637 | bellard | float32 f; |
513 | 0ac4bd56 | bellard | uint32_t i; |
514 | 0ac4bd56 | bellard | } u; |
515 | 0ac4bd56 | bellard | u.f = v; |
516 | 2df3b95d | bellard | stl_be_p(ptr, u.i); |
517 | 0ac4bd56 | bellard | } |
518 | 0ac4bd56 | bellard | |
519 | 8bba3ea1 | balrog | static inline float64 ldfq_be_p(const void *ptr) |
520 | 0ac4bd56 | bellard | { |
521 | 0ac4bd56 | bellard | CPU_DoubleU u; |
522 | 2df3b95d | bellard | u.l.upper = ldl_be_p(ptr); |
523 | 4d7a0880 | blueswir1 | u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
|
524 | 0ac4bd56 | bellard | return u.d;
|
525 | 0ac4bd56 | bellard | } |
526 | 0ac4bd56 | bellard | |
527 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
528 | 0ac4bd56 | bellard | { |
529 | 0ac4bd56 | bellard | CPU_DoubleU u; |
530 | 0ac4bd56 | bellard | u.d = v; |
531 | 2df3b95d | bellard | stl_be_p(ptr, u.l.upper); |
532 | 4d7a0880 | blueswir1 | stl_be_p((uint8_t *)ptr + 4, u.l.lower);
|
533 | 93ac68bc | bellard | } |
534 | 93ac68bc | bellard | |
535 | 5a9fdfec | bellard | #else
|
536 | 5a9fdfec | bellard | |
537 | 8bba3ea1 | balrog | static inline int lduw_be_p(const void *ptr) |
538 | 5a9fdfec | bellard | { |
539 | 5a9fdfec | bellard | return *(uint16_t *)ptr;
|
540 | 5a9fdfec | bellard | } |
541 | 5a9fdfec | bellard | |
542 | 8bba3ea1 | balrog | static inline int ldsw_be_p(const void *ptr) |
543 | 5a9fdfec | bellard | { |
544 | 5a9fdfec | bellard | return *(int16_t *)ptr;
|
545 | 5a9fdfec | bellard | } |
546 | 5a9fdfec | bellard | |
547 | 8bba3ea1 | balrog | static inline int ldl_be_p(const void *ptr) |
548 | 5a9fdfec | bellard | { |
549 | 5a9fdfec | bellard | return *(uint32_t *)ptr;
|
550 | 5a9fdfec | bellard | } |
551 | 5a9fdfec | bellard | |
552 | 8bba3ea1 | balrog | static inline uint64_t ldq_be_p(const void *ptr) |
553 | 5a9fdfec | bellard | { |
554 | 5a9fdfec | bellard | return *(uint64_t *)ptr;
|
555 | 5a9fdfec | bellard | } |
556 | 5a9fdfec | bellard | |
557 | 2df3b95d | bellard | static inline void stw_be_p(void *ptr, int v) |
558 | 5a9fdfec | bellard | { |
559 | 5a9fdfec | bellard | *(uint16_t *)ptr = v; |
560 | 5a9fdfec | bellard | } |
561 | 5a9fdfec | bellard | |
562 | 2df3b95d | bellard | static inline void stl_be_p(void *ptr, int v) |
563 | 5a9fdfec | bellard | { |
564 | 5a9fdfec | bellard | *(uint32_t *)ptr = v; |
565 | 5a9fdfec | bellard | } |
566 | 5a9fdfec | bellard | |
567 | 2df3b95d | bellard | static inline void stq_be_p(void *ptr, uint64_t v) |
568 | 5a9fdfec | bellard | { |
569 | 5a9fdfec | bellard | *(uint64_t *)ptr = v; |
570 | 5a9fdfec | bellard | } |
571 | 5a9fdfec | bellard | |
572 | 5a9fdfec | bellard | /* float access */
|
573 | 5a9fdfec | bellard | |
574 | 8bba3ea1 | balrog | static inline float32 ldfl_be_p(const void *ptr) |
575 | 5a9fdfec | bellard | { |
576 | 53cd6637 | bellard | return *(float32 *)ptr;
|
577 | 5a9fdfec | bellard | } |
578 | 5a9fdfec | bellard | |
579 | 8bba3ea1 | balrog | static inline float64 ldfq_be_p(const void *ptr) |
580 | 5a9fdfec | bellard | { |
581 | 53cd6637 | bellard | return *(float64 *)ptr;
|
582 | 5a9fdfec | bellard | } |
583 | 5a9fdfec | bellard | |
584 | 2df3b95d | bellard | static inline void stfl_be_p(void *ptr, float32 v) |
585 | 5a9fdfec | bellard | { |
586 | 53cd6637 | bellard | *(float32 *)ptr = v; |
587 | 5a9fdfec | bellard | } |
588 | 5a9fdfec | bellard | |
589 | 2df3b95d | bellard | static inline void stfq_be_p(void *ptr, float64 v) |
590 | 5a9fdfec | bellard | { |
591 | 53cd6637 | bellard | *(float64 *)ptr = v; |
592 | 5a9fdfec | bellard | } |
593 | 2df3b95d | bellard | |
594 | 2df3b95d | bellard | #endif
|
595 | 2df3b95d | bellard | |
596 | 2df3b95d | bellard | /* target CPU memory access functions */
|
597 | 2df3b95d | bellard | #if defined(TARGET_WORDS_BIGENDIAN)
|
598 | 2df3b95d | bellard | #define lduw_p(p) lduw_be_p(p)
|
599 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_be_p(p)
|
600 | 2df3b95d | bellard | #define ldl_p(p) ldl_be_p(p)
|
601 | 2df3b95d | bellard | #define ldq_p(p) ldq_be_p(p)
|
602 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_be_p(p)
|
603 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_be_p(p)
|
604 | 2df3b95d | bellard | #define stw_p(p, v) stw_be_p(p, v)
|
605 | 2df3b95d | bellard | #define stl_p(p, v) stl_be_p(p, v)
|
606 | 2df3b95d | bellard | #define stq_p(p, v) stq_be_p(p, v)
|
607 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_be_p(p, v)
|
608 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_be_p(p, v)
|
609 | 2df3b95d | bellard | #else
|
610 | 2df3b95d | bellard | #define lduw_p(p) lduw_le_p(p)
|
611 | 2df3b95d | bellard | #define ldsw_p(p) ldsw_le_p(p)
|
612 | 2df3b95d | bellard | #define ldl_p(p) ldl_le_p(p)
|
613 | 2df3b95d | bellard | #define ldq_p(p) ldq_le_p(p)
|
614 | 2df3b95d | bellard | #define ldfl_p(p) ldfl_le_p(p)
|
615 | 2df3b95d | bellard | #define ldfq_p(p) ldfq_le_p(p)
|
616 | 2df3b95d | bellard | #define stw_p(p, v) stw_le_p(p, v)
|
617 | 2df3b95d | bellard | #define stl_p(p, v) stl_le_p(p, v)
|
618 | 2df3b95d | bellard | #define stq_p(p, v) stq_le_p(p, v)
|
619 | 2df3b95d | bellard | #define stfl_p(p, v) stfl_le_p(p, v)
|
620 | 2df3b95d | bellard | #define stfq_p(p, v) stfq_le_p(p, v)
|
621 | 5a9fdfec | bellard | #endif
|
622 | 5a9fdfec | bellard | |
623 | 61382a50 | bellard | /* MMU memory access macros */
|
624 | 61382a50 | bellard | |
625 | 53a5960a | pbrook | #if defined(CONFIG_USER_ONLY)
|
626 | 0e62fd79 | aurel32 | #include <assert.h> |
627 | 0e62fd79 | aurel32 | #include "qemu-types.h" |
628 | 0e62fd79 | aurel32 | |
629 | 53a5960a | pbrook | /* On some host systems the guest address space is reserved on the host.
|
630 | 53a5960a | pbrook | * This allows the guest address space to be offset to a convenient location.
|
631 | 53a5960a | pbrook | */
|
632 | 53a5960a | pbrook | //#define GUEST_BASE 0x20000000
|
633 | 53a5960a | pbrook | #define GUEST_BASE 0 |
634 | 53a5960a | pbrook | |
635 | 53a5960a | pbrook | /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
|
636 | 53a5960a | pbrook | #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE)) |
637 | 0e62fd79 | aurel32 | #define h2g(x) ({ \
|
638 | 0e62fd79 | aurel32 | unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \ |
639 | 0e62fd79 | aurel32 | /* Check if given address fits target address space */ \
|
640 | 0e62fd79 | aurel32 | assert(__ret == (abi_ulong)__ret); \ |
641 | 0e62fd79 | aurel32 | (abi_ulong)__ret; \ |
642 | 0e62fd79 | aurel32 | }) |
643 | 14cc46b1 | aurel32 | #define h2g_valid(x) ({ \
|
644 | 14cc46b1 | aurel32 | unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \ |
645 | 14cc46b1 | aurel32 | (__guest == (abi_ulong)__guest); \ |
646 | 14cc46b1 | aurel32 | }) |
647 | 53a5960a | pbrook | |
648 | 53a5960a | pbrook | #define saddr(x) g2h(x)
|
649 | 53a5960a | pbrook | #define laddr(x) g2h(x)
|
650 | 53a5960a | pbrook | |
651 | 53a5960a | pbrook | #else /* !CONFIG_USER_ONLY */ |
652 | c27004ec | bellard | /* NOTE: we use double casts if pointers and target_ulong have
|
653 | c27004ec | bellard | different sizes */
|
654 | 53a5960a | pbrook | #define saddr(x) (uint8_t *)(long)(x) |
655 | 53a5960a | pbrook | #define laddr(x) (uint8_t *)(long)(x) |
656 | 53a5960a | pbrook | #endif
|
657 | 53a5960a | pbrook | |
658 | 53a5960a | pbrook | #define ldub_raw(p) ldub_p(laddr((p)))
|
659 | 53a5960a | pbrook | #define ldsb_raw(p) ldsb_p(laddr((p)))
|
660 | 53a5960a | pbrook | #define lduw_raw(p) lduw_p(laddr((p)))
|
661 | 53a5960a | pbrook | #define ldsw_raw(p) ldsw_p(laddr((p)))
|
662 | 53a5960a | pbrook | #define ldl_raw(p) ldl_p(laddr((p)))
|
663 | 53a5960a | pbrook | #define ldq_raw(p) ldq_p(laddr((p)))
|
664 | 53a5960a | pbrook | #define ldfl_raw(p) ldfl_p(laddr((p)))
|
665 | 53a5960a | pbrook | #define ldfq_raw(p) ldfq_p(laddr((p)))
|
666 | 53a5960a | pbrook | #define stb_raw(p, v) stb_p(saddr((p)), v)
|
667 | 53a5960a | pbrook | #define stw_raw(p, v) stw_p(saddr((p)), v)
|
668 | 53a5960a | pbrook | #define stl_raw(p, v) stl_p(saddr((p)), v)
|
669 | 53a5960a | pbrook | #define stq_raw(p, v) stq_p(saddr((p)), v)
|
670 | 53a5960a | pbrook | #define stfl_raw(p, v) stfl_p(saddr((p)), v)
|
671 | 53a5960a | pbrook | #define stfq_raw(p, v) stfq_p(saddr((p)), v)
|
672 | c27004ec | bellard | |
673 | c27004ec | bellard | |
674 | 5fafdf24 | ths | #if defined(CONFIG_USER_ONLY)
|
675 | 61382a50 | bellard | |
676 | 61382a50 | bellard | /* if user mode, no other memory access functions */
|
677 | 61382a50 | bellard | #define ldub(p) ldub_raw(p)
|
678 | 61382a50 | bellard | #define ldsb(p) ldsb_raw(p)
|
679 | 61382a50 | bellard | #define lduw(p) lduw_raw(p)
|
680 | 61382a50 | bellard | #define ldsw(p) ldsw_raw(p)
|
681 | 61382a50 | bellard | #define ldl(p) ldl_raw(p)
|
682 | 61382a50 | bellard | #define ldq(p) ldq_raw(p)
|
683 | 61382a50 | bellard | #define ldfl(p) ldfl_raw(p)
|
684 | 61382a50 | bellard | #define ldfq(p) ldfq_raw(p)
|
685 | 61382a50 | bellard | #define stb(p, v) stb_raw(p, v)
|
686 | 61382a50 | bellard | #define stw(p, v) stw_raw(p, v)
|
687 | 61382a50 | bellard | #define stl(p, v) stl_raw(p, v)
|
688 | 61382a50 | bellard | #define stq(p, v) stq_raw(p, v)
|
689 | 61382a50 | bellard | #define stfl(p, v) stfl_raw(p, v)
|
690 | 61382a50 | bellard | #define stfq(p, v) stfq_raw(p, v)
|
691 | 61382a50 | bellard | |
692 | 61382a50 | bellard | #define ldub_code(p) ldub_raw(p)
|
693 | 61382a50 | bellard | #define ldsb_code(p) ldsb_raw(p)
|
694 | 61382a50 | bellard | #define lduw_code(p) lduw_raw(p)
|
695 | 61382a50 | bellard | #define ldsw_code(p) ldsw_raw(p)
|
696 | 61382a50 | bellard | #define ldl_code(p) ldl_raw(p)
|
697 | bc98a7ef | j_mayer | #define ldq_code(p) ldq_raw(p)
|
698 | 61382a50 | bellard | |
699 | 61382a50 | bellard | #define ldub_kernel(p) ldub_raw(p)
|
700 | 61382a50 | bellard | #define ldsb_kernel(p) ldsb_raw(p)
|
701 | 61382a50 | bellard | #define lduw_kernel(p) lduw_raw(p)
|
702 | 61382a50 | bellard | #define ldsw_kernel(p) ldsw_raw(p)
|
703 | 61382a50 | bellard | #define ldl_kernel(p) ldl_raw(p)
|
704 | bc98a7ef | j_mayer | #define ldq_kernel(p) ldq_raw(p)
|
705 | 0ac4bd56 | bellard | #define ldfl_kernel(p) ldfl_raw(p)
|
706 | 0ac4bd56 | bellard | #define ldfq_kernel(p) ldfq_raw(p)
|
707 | 61382a50 | bellard | #define stb_kernel(p, v) stb_raw(p, v)
|
708 | 61382a50 | bellard | #define stw_kernel(p, v) stw_raw(p, v)
|
709 | 61382a50 | bellard | #define stl_kernel(p, v) stl_raw(p, v)
|
710 | 61382a50 | bellard | #define stq_kernel(p, v) stq_raw(p, v)
|
711 | 0ac4bd56 | bellard | #define stfl_kernel(p, v) stfl_raw(p, v)
|
712 | 0ac4bd56 | bellard | #define stfq_kernel(p, vt) stfq_raw(p, v)
|
713 | 61382a50 | bellard | |
714 | 61382a50 | bellard | #endif /* defined(CONFIG_USER_ONLY) */ |
715 | 61382a50 | bellard | |
716 | 5a9fdfec | bellard | /* page related stuff */
|
717 | 5a9fdfec | bellard | |
718 | 03875444 | aurel32 | #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) |
719 | 5a9fdfec | bellard | #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1) |
720 | 5a9fdfec | bellard | #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK) |
721 | 5a9fdfec | bellard | |
722 | 53a5960a | pbrook | /* ??? These should be the larger of unsigned long and target_ulong. */
|
723 | 83fb7adf | bellard | extern unsigned long qemu_real_host_page_size; |
724 | 83fb7adf | bellard | extern unsigned long qemu_host_page_bits; |
725 | 83fb7adf | bellard | extern unsigned long qemu_host_page_size; |
726 | 83fb7adf | bellard | extern unsigned long qemu_host_page_mask; |
727 | 5a9fdfec | bellard | |
728 | 83fb7adf | bellard | #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask) |
729 | 5a9fdfec | bellard | |
730 | 5a9fdfec | bellard | /* same as PROT_xxx */
|
731 | 5a9fdfec | bellard | #define PAGE_READ 0x0001 |
732 | 5a9fdfec | bellard | #define PAGE_WRITE 0x0002 |
733 | 5a9fdfec | bellard | #define PAGE_EXEC 0x0004 |
734 | 5a9fdfec | bellard | #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
|
735 | 5a9fdfec | bellard | #define PAGE_VALID 0x0008 |
736 | 5a9fdfec | bellard | /* original state of the write flag (used when tracking self-modifying
|
737 | 5a9fdfec | bellard | code */
|
738 | 5fafdf24 | ths | #define PAGE_WRITE_ORG 0x0010 |
739 | 50a9569b | balrog | #define PAGE_RESERVED 0x0020 |
740 | 5a9fdfec | bellard | |
741 | 5a9fdfec | bellard | void page_dump(FILE *f);
|
742 | 53a5960a | pbrook | int page_get_flags(target_ulong address);
|
743 | 53a5960a | pbrook | void page_set_flags(target_ulong start, target_ulong end, int flags); |
744 | 3d97b40b | ths | int page_check_range(target_ulong start, target_ulong len, int flags); |
745 | 5a9fdfec | bellard | |
746 | 26a5f13b | bellard | void cpu_exec_init_all(unsigned long tb_size); |
747 | c5be9f08 | ths | CPUState *cpu_copy(CPUState *env); |
748 | c5be9f08 | ths | |
749 | 5fafdf24 | ths | void cpu_dump_state(CPUState *env, FILE *f,
|
750 | 7fe48483 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
751 | 7fe48483 | bellard | int flags);
|
752 | 76a66253 | j_mayer | void cpu_dump_statistics (CPUState *env, FILE *f,
|
753 | 76a66253 | j_mayer | int (*cpu_fprintf)(FILE *f, const char *fmt, ...), |
754 | 76a66253 | j_mayer | int flags);
|
755 | 7fe48483 | bellard | |
756 | a5e50b26 | malc | void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...) |
757 | 7d99a001 | blueswir1 | __attribute__ ((__format__ (__printf__, 2, 3))); |
758 | f0aca822 | bellard | extern CPUState *first_cpu;
|
759 | e2f22898 | bellard | extern CPUState *cpu_single_env;
|
760 | 2e70f6ef | pbrook | extern int64_t qemu_icount;
|
761 | 2e70f6ef | pbrook | extern int use_icount; |
762 | 5a9fdfec | bellard | |
763 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */ |
764 | 9acbed06 | bellard | #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */ |
765 | 9acbed06 | bellard | #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */ |
766 | ef792f9d | bellard | #define CPU_INTERRUPT_TIMER 0x08 /* internal timer exception pending */ |
767 | 98699967 | bellard | #define CPU_INTERRUPT_FIQ 0x10 /* Fast interrupt pending. */ |
768 | ba3c64fb | bellard | #define CPU_INTERRUPT_HALT 0x20 /* CPU halt wanted */ |
769 | 3b21e03e | bellard | #define CPU_INTERRUPT_SMI 0x40 /* (x86 only) SMI interrupt pending */ |
770 | 6658ffb8 | pbrook | #define CPU_INTERRUPT_DEBUG 0x80 /* Debug event occured. */ |
771 | 0573fbfc | ths | #define CPU_INTERRUPT_VIRQ 0x100 /* virtual interrupt pending. */ |
772 | 474ea849 | aurel32 | #define CPU_INTERRUPT_NMI 0x200 /* NMI pending. */ |
773 | 98699967 | bellard | |
774 | 4690764b | bellard | void cpu_interrupt(CPUState *s, int mask); |
775 | b54ad049 | bellard | void cpu_reset_interrupt(CPUState *env, int mask); |
776 | 68a79315 | bellard | |
777 | a1d1bb31 | aliguori | /* Breakpoint/watchpoint flags */
|
778 | a1d1bb31 | aliguori | #define BP_MEM_READ 0x01 |
779 | a1d1bb31 | aliguori | #define BP_MEM_WRITE 0x02 |
780 | a1d1bb31 | aliguori | #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
|
781 | 06d55cc1 | aliguori | #define BP_STOP_BEFORE_ACCESS 0x04 |
782 | 6e140f28 | aliguori | #define BP_WATCHPOINT_HIT 0x08 |
783 | a1d1bb31 | aliguori | #define BP_GDB 0x10 |
784 | 2dc9f411 | aliguori | #define BP_CPU 0x20 |
785 | a1d1bb31 | aliguori | |
786 | a1d1bb31 | aliguori | int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags, |
787 | a1d1bb31 | aliguori | CPUBreakpoint **breakpoint); |
788 | a1d1bb31 | aliguori | int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags); |
789 | a1d1bb31 | aliguori | void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
|
790 | a1d1bb31 | aliguori | void cpu_breakpoint_remove_all(CPUState *env, int mask); |
791 | a1d1bb31 | aliguori | int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
|
792 | a1d1bb31 | aliguori | int flags, CPUWatchpoint **watchpoint);
|
793 | a1d1bb31 | aliguori | int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
|
794 | a1d1bb31 | aliguori | target_ulong len, int flags);
|
795 | a1d1bb31 | aliguori | void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
|
796 | a1d1bb31 | aliguori | void cpu_watchpoint_remove_all(CPUState *env, int mask); |
797 | 60897d36 | edgar_igl | |
798 | 60897d36 | edgar_igl | #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ |
799 | 60897d36 | edgar_igl | #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ |
800 | 60897d36 | edgar_igl | #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ |
801 | 60897d36 | edgar_igl | |
802 | c33a346e | bellard | void cpu_single_step(CPUState *env, int enabled); |
803 | d95dc32d | bellard | void cpu_reset(CPUState *s);
|
804 | 4c3a88a2 | bellard | |
805 | 13eb76e0 | bellard | /* Return the physical page corresponding to a virtual one. Use it
|
806 | 13eb76e0 | bellard | only for debugging because no protection checks are done. Return -1
|
807 | 13eb76e0 | bellard | if no page found. */
|
808 | 9b3c35e0 | j_mayer | target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr); |
809 | 13eb76e0 | bellard | |
810 | 5fafdf24 | ths | #define CPU_LOG_TB_OUT_ASM (1 << 0) |
811 | 9fddaa0c | bellard | #define CPU_LOG_TB_IN_ASM (1 << 1) |
812 | f193c797 | bellard | #define CPU_LOG_TB_OP (1 << 2) |
813 | f193c797 | bellard | #define CPU_LOG_TB_OP_OPT (1 << 3) |
814 | f193c797 | bellard | #define CPU_LOG_INT (1 << 4) |
815 | f193c797 | bellard | #define CPU_LOG_EXEC (1 << 5) |
816 | f193c797 | bellard | #define CPU_LOG_PCALL (1 << 6) |
817 | fd872598 | bellard | #define CPU_LOG_IOPORT (1 << 7) |
818 | 9fddaa0c | bellard | #define CPU_LOG_TB_CPU (1 << 8) |
819 | eca1bdf4 | aliguori | #define CPU_LOG_RESET (1 << 9) |
820 | f193c797 | bellard | |
821 | f193c797 | bellard | /* define log items */
|
822 | f193c797 | bellard | typedef struct CPULogItem { |
823 | f193c797 | bellard | int mask;
|
824 | f193c797 | bellard | const char *name; |
825 | f193c797 | bellard | const char *help; |
826 | f193c797 | bellard | } CPULogItem; |
827 | f193c797 | bellard | |
828 | c7cd6a37 | blueswir1 | extern const CPULogItem cpu_log_items[]; |
829 | f193c797 | bellard | |
830 | 34865134 | bellard | void cpu_set_log(int log_flags); |
831 | 34865134 | bellard | void cpu_set_log_filename(const char *filename); |
832 | f193c797 | bellard | int cpu_str_to_log_mask(const char *str); |
833 | 34865134 | bellard | |
834 | 09683d35 | bellard | /* IO ports API */
|
835 | 09683d35 | bellard | |
836 | 09683d35 | bellard | /* NOTE: as these functions may be even used when there is an isa
|
837 | 09683d35 | bellard | brige on non x86 targets, we always defined them */
|
838 | 09683d35 | bellard | #ifndef NO_CPU_IO_DEFS
|
839 | 09683d35 | bellard | void cpu_outb(CPUState *env, int addr, int val); |
840 | 09683d35 | bellard | void cpu_outw(CPUState *env, int addr, int val); |
841 | 09683d35 | bellard | void cpu_outl(CPUState *env, int addr, int val); |
842 | 09683d35 | bellard | int cpu_inb(CPUState *env, int addr); |
843 | 09683d35 | bellard | int cpu_inw(CPUState *env, int addr); |
844 | 09683d35 | bellard | int cpu_inl(CPUState *env, int addr); |
845 | 09683d35 | bellard | #endif
|
846 | 09683d35 | bellard | |
847 | 00f82b8a | aurel32 | /* address in the RAM (different from a physical address) */
|
848 | 00f82b8a | aurel32 | #ifdef USE_KQEMU
|
849 | 00f82b8a | aurel32 | typedef uint32_t ram_addr_t;
|
850 | 00f82b8a | aurel32 | #else
|
851 | 00f82b8a | aurel32 | typedef unsigned long ram_addr_t; |
852 | 00f82b8a | aurel32 | #endif
|
853 | 00f82b8a | aurel32 | |
854 | 33417e70 | bellard | /* memory API */
|
855 | 33417e70 | bellard | |
856 | 00f82b8a | aurel32 | extern ram_addr_t phys_ram_size;
|
857 | edf75d59 | bellard | extern int phys_ram_fd; |
858 | edf75d59 | bellard | extern uint8_t *phys_ram_base;
|
859 | 1ccde1cb | bellard | extern uint8_t *phys_ram_dirty;
|
860 | 00f82b8a | aurel32 | extern ram_addr_t ram_size;
|
861 | edf75d59 | bellard | |
862 | edf75d59 | bellard | /* physical memory access */
|
863 | 0f459d16 | pbrook | |
864 | 0f459d16 | pbrook | /* MMIO pages are identified by a combination of an IO device index and
|
865 | 0f459d16 | pbrook | 3 flags. The ROMD code stores the page ram offset in iotlb entry,
|
866 | 0f459d16 | pbrook | so only a limited number of ids are avaiable. */
|
867 | 0f459d16 | pbrook | |
868 | 0f459d16 | pbrook | #define IO_MEM_SHIFT 3 |
869 | 98699967 | bellard | #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT)) |
870 | edf75d59 | bellard | |
871 | edf75d59 | bellard | #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */ |
872 | edf75d59 | bellard | #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */ |
873 | edf75d59 | bellard | #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT) |
874 | 0f459d16 | pbrook | #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT) |
875 | 0f459d16 | pbrook | |
876 | 0f459d16 | pbrook | /* Acts like a ROM when read and like a device when written. */
|
877 | 2a4188a3 | bellard | #define IO_MEM_ROMD (1) |
878 | db7b5426 | blueswir1 | #define IO_MEM_SUBPAGE (2) |
879 | 4254fab8 | blueswir1 | #define IO_MEM_SUBWIDTH (4) |
880 | edf75d59 | bellard | |
881 | 0f459d16 | pbrook | /* Flags stored in the low bits of the TLB virtual address. These are
|
882 | 0f459d16 | pbrook | defined so that fast path ram access is all zeros. */
|
883 | 0f459d16 | pbrook | /* Zero if TLB entry is valid. */
|
884 | 0f459d16 | pbrook | #define TLB_INVALID_MASK (1 << 3) |
885 | 0f459d16 | pbrook | /* Set if TLB entry references a clean RAM page. The iotlb entry will
|
886 | 0f459d16 | pbrook | contain the page physical address. */
|
887 | 0f459d16 | pbrook | #define TLB_NOTDIRTY (1 << 4) |
888 | 0f459d16 | pbrook | /* Set if TLB entry is an IO callback. */
|
889 | 0f459d16 | pbrook | #define TLB_MMIO (1 << 5) |
890 | 0f459d16 | pbrook | |
891 | 7727994d | bellard | typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value); |
892 | 7727994d | bellard | typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr); |
893 | 33417e70 | bellard | |
894 | 8da3ff18 | pbrook | void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
|
895 | 8da3ff18 | pbrook | ram_addr_t size, |
896 | 8da3ff18 | pbrook | ram_addr_t phys_offset, |
897 | 8da3ff18 | pbrook | ram_addr_t region_offset); |
898 | 8da3ff18 | pbrook | static inline void cpu_register_physical_memory(target_phys_addr_t start_addr, |
899 | 8da3ff18 | pbrook | ram_addr_t size, |
900 | 8da3ff18 | pbrook | ram_addr_t phys_offset) |
901 | 8da3ff18 | pbrook | { |
902 | 8da3ff18 | pbrook | cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
|
903 | 8da3ff18 | pbrook | } |
904 | 8da3ff18 | pbrook | |
905 | 00f82b8a | aurel32 | ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr); |
906 | 00f82b8a | aurel32 | ram_addr_t qemu_ram_alloc(ram_addr_t); |
907 | e9a1ab19 | bellard | void qemu_ram_free(ram_addr_t addr);
|
908 | 33417e70 | bellard | int cpu_register_io_memory(int io_index, |
909 | 33417e70 | bellard | CPUReadMemoryFunc **mem_read, |
910 | 7727994d | bellard | CPUWriteMemoryFunc **mem_write, |
911 | 7727994d | bellard | void *opaque);
|
912 | 88715657 | aliguori | void cpu_unregister_io_memory(int table_address); |
913 | 8926b517 | bellard | CPUWriteMemoryFunc **cpu_get_io_memory_write(int io_index);
|
914 | 8926b517 | bellard | CPUReadMemoryFunc **cpu_get_io_memory_read(int io_index);
|
915 | 33417e70 | bellard | |
916 | 2e12669a | bellard | void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
|
917 | 13eb76e0 | bellard | int len, int is_write); |
918 | 5fafdf24 | ths | static inline void cpu_physical_memory_read(target_phys_addr_t addr, |
919 | 2e12669a | bellard | uint8_t *buf, int len)
|
920 | 8b1f24b0 | bellard | { |
921 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, buf, len, 0);
|
922 | 8b1f24b0 | bellard | } |
923 | 5fafdf24 | ths | static inline void cpu_physical_memory_write(target_phys_addr_t addr, |
924 | 2e12669a | bellard | const uint8_t *buf, int len) |
925 | 8b1f24b0 | bellard | { |
926 | 8b1f24b0 | bellard | cpu_physical_memory_rw(addr, (uint8_t *)buf, len, 1);
|
927 | 8b1f24b0 | bellard | } |
928 | 6d16c2f8 | aliguori | void *cpu_physical_memory_map(target_phys_addr_t addr,
|
929 | 6d16c2f8 | aliguori | target_phys_addr_t *plen, |
930 | 6d16c2f8 | aliguori | int is_write);
|
931 | 6d16c2f8 | aliguori | void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len, |
932 | 6d16c2f8 | aliguori | int is_write, target_phys_addr_t access_len);
|
933 | ba223c29 | aliguori | void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); |
934 | ba223c29 | aliguori | void cpu_unregister_map_client(void *cookie); |
935 | 6d16c2f8 | aliguori | |
936 | aab33094 | bellard | uint32_t ldub_phys(target_phys_addr_t addr); |
937 | aab33094 | bellard | uint32_t lduw_phys(target_phys_addr_t addr); |
938 | 8df1cd07 | bellard | uint32_t ldl_phys(target_phys_addr_t addr); |
939 | aab33094 | bellard | uint64_t ldq_phys(target_phys_addr_t addr); |
940 | 8df1cd07 | bellard | void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
|
941 | bc98a7ef | j_mayer | void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
|
942 | aab33094 | bellard | void stb_phys(target_phys_addr_t addr, uint32_t val);
|
943 | aab33094 | bellard | void stw_phys(target_phys_addr_t addr, uint32_t val);
|
944 | 8df1cd07 | bellard | void stl_phys(target_phys_addr_t addr, uint32_t val);
|
945 | aab33094 | bellard | void stq_phys(target_phys_addr_t addr, uint64_t val);
|
946 | 8b1f24b0 | bellard | |
947 | 5fafdf24 | ths | void cpu_physical_memory_write_rom(target_phys_addr_t addr,
|
948 | d0ecd2aa | bellard | const uint8_t *buf, int len); |
949 | 5fafdf24 | ths | int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
|
950 | 8b1f24b0 | bellard | uint8_t *buf, int len, int is_write); |
951 | 13eb76e0 | bellard | |
952 | 74576198 | aliguori | #define VGA_DIRTY_FLAG 0x01 |
953 | 74576198 | aliguori | #define CODE_DIRTY_FLAG 0x02 |
954 | 74576198 | aliguori | #define KQEMU_DIRTY_FLAG 0x04 |
955 | 74576198 | aliguori | #define MIGRATION_DIRTY_FLAG 0x08 |
956 | 0a962c02 | bellard | |
957 | 1ccde1cb | bellard | /* read dirty bit (return 0 or 1) */
|
958 | 04c504cc | bellard | static inline int cpu_physical_memory_is_dirty(ram_addr_t addr) |
959 | 1ccde1cb | bellard | { |
960 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] == 0xff; |
961 | 0a962c02 | bellard | } |
962 | 0a962c02 | bellard | |
963 | 5fafdf24 | ths | static inline int cpu_physical_memory_get_dirty(ram_addr_t addr, |
964 | 0a962c02 | bellard | int dirty_flags)
|
965 | 0a962c02 | bellard | { |
966 | 0a962c02 | bellard | return phys_ram_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
|
967 | 1ccde1cb | bellard | } |
968 | 1ccde1cb | bellard | |
969 | 04c504cc | bellard | static inline void cpu_physical_memory_set_dirty(ram_addr_t addr) |
970 | 1ccde1cb | bellard | { |
971 | 0a962c02 | bellard | phys_ram_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
|
972 | 1ccde1cb | bellard | } |
973 | 1ccde1cb | bellard | |
974 | 04c504cc | bellard | void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
|
975 | 0a962c02 | bellard | int dirty_flags);
|
976 | 04c504cc | bellard | void cpu_tlb_update_dirty(CPUState *env);
|
977 | 1ccde1cb | bellard | |
978 | 74576198 | aliguori | int cpu_physical_memory_set_dirty_tracking(int enable); |
979 | 74576198 | aliguori | |
980 | 74576198 | aliguori | int cpu_physical_memory_get_dirty_tracking(void); |
981 | 74576198 | aliguori | |
982 | 2bec46dc | aliguori | void cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr, target_phys_addr_t end_addr);
|
983 | 2bec46dc | aliguori | |
984 | e3db7226 | bellard | void dump_exec_info(FILE *f,
|
985 | e3db7226 | bellard | int (*cpu_fprintf)(FILE *f, const char *fmt, ...)); |
986 | e3db7226 | bellard | |
987 | f65ed4c1 | aliguori | /* Coalesced MMIO regions are areas where write operations can be reordered.
|
988 | f65ed4c1 | aliguori | * This usually implies that write operations are side-effect free. This allows
|
989 | f65ed4c1 | aliguori | * batching which can make a major impact on performance when using
|
990 | f65ed4c1 | aliguori | * virtualization.
|
991 | f65ed4c1 | aliguori | */
|
992 | f65ed4c1 | aliguori | void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
|
993 | f65ed4c1 | aliguori | |
994 | f65ed4c1 | aliguori | void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
|
995 | f65ed4c1 | aliguori | |
996 | effedbc9 | bellard | /*******************************************/
|
997 | effedbc9 | bellard | /* host CPU ticks (if available) */
|
998 | effedbc9 | bellard | |
999 | e58ffeb3 | malc | #if defined(_ARCH_PPC)
|
1000 | effedbc9 | bellard | |
1001 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
1002 | effedbc9 | bellard | { |
1003 | 5e10fc90 | malc | int64_t retval; |
1004 | 5e10fc90 | malc | #ifdef _ARCH_PPC64
|
1005 | 5e10fc90 | malc | /* This reads timebase in one 64bit go and includes Cell workaround from:
|
1006 | 5e10fc90 | malc | http://ozlabs.org/pipermail/linuxppc-dev/2006-October/027052.html
|
1007 | 5e10fc90 | malc | */
|
1008 | 5e10fc90 | malc | __asm__ __volatile__ ( |
1009 | 5e10fc90 | malc | "mftb %0\n\t"
|
1010 | 5e10fc90 | malc | "cmpwi %0,0\n\t"
|
1011 | 5e10fc90 | malc | "beq- $-8"
|
1012 | 5e10fc90 | malc | : "=r" (retval));
|
1013 | 5e10fc90 | malc | #else
|
1014 | 5e10fc90 | malc | /* http://ozlabs.org/pipermail/linuxppc-dev/1999-October/003889.html */
|
1015 | 5e10fc90 | malc | unsigned long junk; |
1016 | 5e10fc90 | malc | __asm__ __volatile__ ( |
1017 | 5e10fc90 | malc | "mftbu %1\n\t"
|
1018 | 5e10fc90 | malc | "mftb %L0\n\t"
|
1019 | 5e10fc90 | malc | "mftbu %0\n\t"
|
1020 | 5e10fc90 | malc | "cmpw %0,%1\n\t"
|
1021 | 5e10fc90 | malc | "bne $-16"
|
1022 | 5e10fc90 | malc | : "=r" (retval), "=r" (junk)); |
1023 | 5e10fc90 | malc | #endif
|
1024 | 5e10fc90 | malc | return retval;
|
1025 | effedbc9 | bellard | } |
1026 | effedbc9 | bellard | |
1027 | effedbc9 | bellard | #elif defined(__i386__)
|
1028 | effedbc9 | bellard | |
1029 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
1030 | 5f1ce948 | bellard | { |
1031 | 5f1ce948 | bellard | int64_t val; |
1032 | 5f1ce948 | bellard | asm volatile ("rdtsc" : "=A" (val)); |
1033 | 5f1ce948 | bellard | return val;
|
1034 | 5f1ce948 | bellard | } |
1035 | 5f1ce948 | bellard | |
1036 | effedbc9 | bellard | #elif defined(__x86_64__)
|
1037 | effedbc9 | bellard | |
1038 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
1039 | effedbc9 | bellard | { |
1040 | effedbc9 | bellard | uint32_t low,high; |
1041 | effedbc9 | bellard | int64_t val; |
1042 | effedbc9 | bellard | asm volatile("rdtsc" : "=a" (low), "=d" (high)); |
1043 | effedbc9 | bellard | val = high; |
1044 | effedbc9 | bellard | val <<= 32;
|
1045 | effedbc9 | bellard | val |= low; |
1046 | effedbc9 | bellard | return val;
|
1047 | effedbc9 | bellard | } |
1048 | effedbc9 | bellard | |
1049 | f54b3f92 | aurel32 | #elif defined(__hppa__)
|
1050 | f54b3f92 | aurel32 | |
1051 | f54b3f92 | aurel32 | static inline int64_t cpu_get_real_ticks(void) |
1052 | f54b3f92 | aurel32 | { |
1053 | f54b3f92 | aurel32 | int val;
|
1054 | f54b3f92 | aurel32 | asm volatile ("mfctl %%cr16, %0" : "=r"(val)); |
1055 | f54b3f92 | aurel32 | return val;
|
1056 | f54b3f92 | aurel32 | } |
1057 | f54b3f92 | aurel32 | |
1058 | effedbc9 | bellard | #elif defined(__ia64)
|
1059 | effedbc9 | bellard | |
1060 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
1061 | effedbc9 | bellard | { |
1062 | effedbc9 | bellard | int64_t val; |
1063 | effedbc9 | bellard | asm volatile ("mov %0 = ar.itc" : "=r"(val) :: "memory"); |
1064 | effedbc9 | bellard | return val;
|
1065 | effedbc9 | bellard | } |
1066 | effedbc9 | bellard | |
1067 | effedbc9 | bellard | #elif defined(__s390__)
|
1068 | effedbc9 | bellard | |
1069 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks(void) |
1070 | effedbc9 | bellard | { |
1071 | effedbc9 | bellard | int64_t val; |
1072 | effedbc9 | bellard | asm volatile("stck 0(%1)" : "=m" (val) : "a" (&val) : "cc"); |
1073 | effedbc9 | bellard | return val;
|
1074 | effedbc9 | bellard | } |
1075 | effedbc9 | bellard | |
1076 | 3142255c | blueswir1 | #elif defined(__sparc_v8plus__) || defined(__sparc_v8plusa__) || defined(__sparc_v9__)
|
1077 | effedbc9 | bellard | |
1078 | effedbc9 | bellard | static inline int64_t cpu_get_real_ticks (void) |
1079 | effedbc9 | bellard | { |
1080 | effedbc9 | bellard | #if defined(_LP64)
|
1081 | effedbc9 | bellard | uint64_t rval; |
1082 | effedbc9 | bellard | asm volatile("rd %%tick,%0" : "=r"(rval)); |
1083 | effedbc9 | bellard | return rval;
|
1084 | effedbc9 | bellard | #else
|
1085 | effedbc9 | bellard | union {
|
1086 | effedbc9 | bellard | uint64_t i64; |
1087 | effedbc9 | bellard | struct {
|
1088 | effedbc9 | bellard | uint32_t high; |
1089 | effedbc9 | bellard | uint32_t low; |
1090 | effedbc9 | bellard | } i32; |
1091 | effedbc9 | bellard | } rval; |
1092 | effedbc9 | bellard | asm volatile("rd %%tick,%1; srlx %1,32,%0" |
1093 | effedbc9 | bellard | : "=r"(rval.i32.high), "=r"(rval.i32.low)); |
1094 | effedbc9 | bellard | return rval.i64;
|
1095 | effedbc9 | bellard | #endif
|
1096 | effedbc9 | bellard | } |
1097 | c4b89d18 | ths | |
1098 | c4b89d18 | ths | #elif defined(__mips__)
|
1099 | c4b89d18 | ths | |
1100 | c4b89d18 | ths | static inline int64_t cpu_get_real_ticks(void) |
1101 | c4b89d18 | ths | { |
1102 | c4b89d18 | ths | #if __mips_isa_rev >= 2 |
1103 | c4b89d18 | ths | uint32_t count; |
1104 | c4b89d18 | ths | static uint32_t cyc_per_count = 0; |
1105 | c4b89d18 | ths | |
1106 | c4b89d18 | ths | if (!cyc_per_count)
|
1107 | c4b89d18 | ths | __asm__ __volatile__("rdhwr %0, $3" : "=r" (cyc_per_count)); |
1108 | c4b89d18 | ths | |
1109 | c4b89d18 | ths | __asm__ __volatile__("rdhwr %1, $2" : "=r" (count)); |
1110 | c4b89d18 | ths | return (int64_t)(count * cyc_per_count);
|
1111 | c4b89d18 | ths | #else
|
1112 | c4b89d18 | ths | /* FIXME */
|
1113 | c4b89d18 | ths | static int64_t ticks = 0; |
1114 | c4b89d18 | ths | return ticks++;
|
1115 | c4b89d18 | ths | #endif
|
1116 | c4b89d18 | ths | } |
1117 | c4b89d18 | ths | |
1118 | 46152182 | pbrook | #else
|
1119 | 46152182 | pbrook | /* The host CPU doesn't have an easily accessible cycle counter.
|
1120 | 85028e4d | ths | Just return a monotonically increasing value. This will be
|
1121 | 85028e4d | ths | totally wrong, but hopefully better than nothing. */
|
1122 | 46152182 | pbrook | static inline int64_t cpu_get_real_ticks (void) |
1123 | 46152182 | pbrook | { |
1124 | 46152182 | pbrook | static int64_t ticks = 0; |
1125 | 46152182 | pbrook | return ticks++;
|
1126 | 46152182 | pbrook | } |
1127 | effedbc9 | bellard | #endif
|
1128 | effedbc9 | bellard | |
1129 | effedbc9 | bellard | /* profiling */
|
1130 | effedbc9 | bellard | #ifdef CONFIG_PROFILER
|
1131 | effedbc9 | bellard | static inline int64_t profile_getclock(void) |
1132 | effedbc9 | bellard | { |
1133 | effedbc9 | bellard | return cpu_get_real_ticks();
|
1134 | effedbc9 | bellard | } |
1135 | effedbc9 | bellard | |
1136 | 5f1ce948 | bellard | extern int64_t kqemu_time, kqemu_time_start;
|
1137 | 5f1ce948 | bellard | extern int64_t qemu_time, qemu_time_start;
|
1138 | 5f1ce948 | bellard | extern int64_t tlb_flush_time;
|
1139 | 5f1ce948 | bellard | extern int64_t kqemu_exec_count;
|
1140 | 5f1ce948 | bellard | extern int64_t dev_time;
|
1141 | 5f1ce948 | bellard | extern int64_t kqemu_ret_int_count;
|
1142 | 5f1ce948 | bellard | extern int64_t kqemu_ret_excp_count;
|
1143 | 5f1ce948 | bellard | extern int64_t kqemu_ret_intr_count;
|
1144 | 5f1ce948 | bellard | #endif
|
1145 | 5f1ce948 | bellard | |
1146 | 5a9fdfec | bellard | #endif /* CPU_ALL_H */ |