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Replace local ADDRX/PADDRX macros with TARGET_FMT_lx/plx
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Replace always_inline with inline
We define inline as always_inline.
target-ppc: retain l{w,d}arx loaded value
We do this so we can check on the corresponding stc{w,d}x. whether thevalue has changed. It's a poor man's form of implementing atomicoperations and is valid only for NPTL usermode Linux emulation.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>...
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Update to a hopefully more future proof FSF address
Fix mingw32 build warnings
Work around buffer and ioctlsocket argument type signedness problemsSuppress a prototype which is unused on mingw32Expand a macro to avoid warnings from some GCC versions
Fix typo that leads to out of bounds array access on big endian systems
targe-ppc: optimize mfcr and mtcrf
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6793 c046a42c-6fe2-441c-8c8c-71466251a162
Fix RFI
The current implementation masks some MSR bits from SRR1 as it isgiven on rfi(d). This looks pretty wrong and breaks Altivec.
Signed-off-by: Alexander Graf <alex@csgraf.de>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6754 c046a42c-6fe2-441c-8c8c-71466251a162
Implement slbmte
In order to modify SLB entries on recent PPC64 machines, the slbmteinstruction is used.
This patch implements the slbmte instruction and makes the "bridge" mode code use the slb set functions, so we can move the SLB intothe CPU struct later....
target-ppc: Add vrsqrtefp instruction
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6574 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vrefp instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6573 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vct{u,s}xs instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6572 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vcmp{eq, ge, gt, b}fp{, .} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6571 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add vmaddfp and vnmsubfp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6570 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add v{add,sub}fp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6569 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: Add v{max,min}fp instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6568 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: change instruction name vrlogefp into vlogefp
Thanks to Nathan Froyd for noticing that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6532 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: add vrlogefp instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6519 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix previous commit
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6516 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use the new float constants
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6515 c046a42c-6fe2-441c-8c8c-71466251a162
Add vcf{u,s}x instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6513 c046a42c-6fe2-441c-8c8c-71466251a162
Add vrfi{m,n,p,z} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6512 c046a42c-6fe2-441c-8c8c-71466251a162
Add various NaN-handling macros
These simplify the implementation of the floating-point Altivecinstructions and reduce clutter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6511 c046a42c-6fe2-441c-8c8c-71466251a162
Make mtvscr use a helper
Do this so we can set float statuses once per mtvscr, rather than onceper Altivec instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6508 c046a42c-6fe2-441c-8c8c-71466251a162
Rename spe_status to vec_status
Only one of Altivec and SPE will be available on a given chip.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6506 c046a42c-6fe2-441c-8c8c-71466251a162
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.
This patch doesn't try to merge logging macros from different files,but just unify the debugging code #ifdefs onto a macro on each file. Afurther cleanup can unify the debugging macros on a common header, later...
Add v{add, sub}{s, u}{b, h, w}s instructions
Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6254 c046a42c-6fe2-441c-8c8c-71466251a162
Add vspltis{b,h,w} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6238 c046a42c-6fe2-441c-8c8c-71466251a162
Add vs{l,r} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6237 c046a42c-6fe2-441c-8c8c-71466251a162
Add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6236 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix compilation on BigEndian
This fixes BigEndian compilation for target-ppc.
(Michael Buesch)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6193 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsumsws, vsum2sws, and vsum4{sbs, shs,ubs} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6189 c046a42c-6fe2-441c-8c8c-71466251a162
Add {l,st}ve{b,h,w}x instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6188 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmladduhm instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6187 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsumsh{m,s} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6186 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsumuh{m,s} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6185 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmh{,r}addshs instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6184 c046a42c-6fe2-441c-8c8c-71466251a162
Add vpkpx instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6183 c046a42c-6fe2-441c-8c8c-71466251a162
Add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6182 c046a42c-6fe2-441c-8c8c-71466251a162
Add saturating arithmetic conversion functions for subsequent instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6181 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsel and vperm instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6180 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmsum{u,m}bm instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6179 c046a42c-6fe2-441c-8c8c-71466251a162
Add vupk{h,l}s{b,h} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6177 c046a42c-6fe2-441c-8c8c-71466251a162
Add vupk{h,l}px instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6176 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsplt{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6174 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsldoi instruction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6171 c046a42c-6fe2-441c-8c8c-71466251a162
Add vrl{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6170 c046a42c-6fe2-441c-8c8c-71466251a162
Add lvs{l,r} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6169 c046a42c-6fe2-441c-8c8c-71466251a162
Add v{add,sub}cuw instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6168 c046a42c-6fe2-441c-8c8c-71466251a162
Add vs{l,r}o instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6167 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsl{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6166 c046a42c-6fe2-441c-8c8c-71466251a162
Add vsr{,a}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6165 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmul{e,o}{s,u}{b,h} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6164 c046a42c-6fe2-441c-8c8c-71466251a162
Add vmrg{l,h}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6163 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Add v{min, max}{s, u}{b, h, w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6157 c046a42c-6fe2-441c-8c8c-71466251a162
Add vavg{s,u}{b,h,w} instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6156 c046a42c-6fe2-441c-8c8c-71466251a162
Add v{add,sub}u{b,h,w}m instructions.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6155 c046a42c-6fe2-441c-8c8c-71466251a162
Add helper macros for later patches.
Remove N_ELEMS, VECTOR_FOR, and VECTOR_FOR_I macros. Retain theVECTOR_FOR_INORDER_I macros as the clearest way of expressing the intentof iterating over elements in their stored target-endian order.
target-ppc: improve correctness of the fsel instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6139 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix stsw/stswi instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6138 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use float_flag_divbyzero instead of checking the operands
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6097 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix fres, fsqrte and remove useless code
- fres and fsqrte should not assign a float32 number to a float64 value.- fre, fres and fsqrte are checking for cases already taken into account by softfloat and softfloat native. Remove those useless tests....
target-ppc: add comments about constants introduced in revision 6046
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6069 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fmadd/fmsub/fmnadd/fmnsub can generate VXIMZ or VXIZI exceptions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6053 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fadd/fsub: correctly propagate NaN
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6052 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use the new fp functions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6051 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: correctly propagate NaN in division
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6048 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix fload_invalid_op_excp()
The argument is a value, not a flag. Update the tests accordingly. Alsoset a correct default value for NaN.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6047 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use a correct value to represent 1.0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6046 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix frsp instruction
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6036 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix mtfsf and mtfsfi instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6035 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix fcmp{o,u} instructions
The instructions are specified to update the condition register even ifan error is to be signaled because of NaN input.
Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-ppc: fix mtfsb0 and mtfsb1
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6032 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix fsel instruction
Fix fsel instruction. Eliminate unneeded temporaries while we're at it,too.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6026 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: keep only the table version for mfrom
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6007 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use accessors to access fp_status exception_flags
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6006 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix compilation with PRECISE_EMULATION
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6004 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: fix compilation with CONFIG_SOFTFLOAT
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6003 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove remaining warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5991 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: rework exception code
... also remove two warnings.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5989 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: kill a warning
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5952 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: cleanup op_helper.c after TCG conversion
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5951 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: memory load/store rework
Rework the memory load/store:- Unify load/store functions for 32-bit and 64-bit CPU- Don't swap values twice for bit-reverse load/store functions in little endian mode.- On a 64-bit CPU in 32-bit mode, do the address truncation for...
target-ppc: convert SPR accesses to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5910 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: remove dead code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5909 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert SLB/TLB instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5895 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert dcr load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5893 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert msr load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5892 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert POWER bridge instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5891 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: use ldl/ldub/stl/stub for load/store in op_helper.c
Should not give any performance penality given cpu_mmu_index() isan inline function returning a value from env.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5837 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert PPC 440 instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5836 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert return from interrupt instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5832 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert lscbx instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5829 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert load/store string instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5828 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert icbi instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5827 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert dcbz instruction to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5826 c046a42c-6fe2-441c-8c8c-71466251a162
target-ppc: convert load/store multiple instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5825 c046a42c-6fe2-441c-8c8c-71466251a162