root / tcg / i386 / tcg-target.c @ 075e36b8
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/*
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* Tiny Code Generator for QEMU
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*
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* Copyright (c) 2008 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#ifndef NDEBUG
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static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { |
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"%eax",
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"%ecx",
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"%edx",
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"%ebx",
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"%esp",
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"%ebp",
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"%esi",
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"%edi",
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}; |
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#endif
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static const int tcg_target_reg_alloc_order[] = { |
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TCG_REG_EAX, |
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TCG_REG_EDX, |
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TCG_REG_ECX, |
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TCG_REG_EBX, |
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TCG_REG_ESI, |
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TCG_REG_EDI, |
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TCG_REG_EBP, |
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}; |
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|
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static const int tcg_target_call_iarg_regs[3] = { TCG_REG_EAX, TCG_REG_EDX, TCG_REG_ECX }; |
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static const int tcg_target_call_oarg_regs[2] = { TCG_REG_EAX, TCG_REG_EDX }; |
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|
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static uint8_t *tb_ret_addr;
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|
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static void patch_reloc(uint8_t *code_ptr, int type, |
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tcg_target_long value, tcg_target_long addend) |
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{ |
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value += addend; |
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switch(type) {
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case R_386_32:
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*(uint32_t *)code_ptr = value; |
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break;
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case R_386_PC32:
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*(uint32_t *)code_ptr = value - (long)code_ptr;
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break;
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default:
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tcg_abort(); |
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} |
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} |
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|
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/* maximum number of register used for input function arguments */
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static inline int tcg_target_get_call_iarg_regs_count(int flags) |
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{ |
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flags &= TCG_CALL_TYPE_MASK; |
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switch(flags) {
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case TCG_CALL_TYPE_STD:
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return 0; |
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case TCG_CALL_TYPE_REGPARM_1:
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case TCG_CALL_TYPE_REGPARM_2:
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case TCG_CALL_TYPE_REGPARM:
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return flags - TCG_CALL_TYPE_REGPARM_1 + 1; |
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default:
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tcg_abort(); |
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} |
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} |
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|
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/* parse target specific constraints */
|
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static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) |
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{ |
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const char *ct_str; |
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|
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ct_str = *pct_str; |
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switch(ct_str[0]) { |
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case 'a': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); |
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break;
|
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case 'b': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); |
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break;
|
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case 'c': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); |
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break;
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case 'd': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); |
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break;
|
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case 'S': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); |
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break;
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case 'D': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); |
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break;
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case 'q': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xf); |
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break;
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case 'r': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xff); |
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break;
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|
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/* qemu_ld/st address constraint */
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case 'L': |
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ct->ct |= TCG_CT_REG; |
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tcg_regset_set32(ct->u.regs, 0, 0xff); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_EAX); |
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tcg_regset_reset_reg(ct->u.regs, TCG_REG_EDX); |
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break;
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default:
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return -1; |
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} |
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ct_str++; |
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*pct_str = ct_str; |
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return 0; |
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} |
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|
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/* test if a constant matches the constraint */
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static inline int tcg_target_const_match(tcg_target_long val, |
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const TCGArgConstraint *arg_ct)
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{ |
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int ct;
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ct = arg_ct->ct; |
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if (ct & TCG_CT_CONST)
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return 1; |
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else
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return 0; |
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} |
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#define ARITH_ADD 0 |
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#define ARITH_OR 1 |
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#define ARITH_ADC 2 |
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#define ARITH_SBB 3 |
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#define ARITH_AND 4 |
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#define ARITH_SUB 5 |
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#define ARITH_XOR 6 |
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#define ARITH_CMP 7 |
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|
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#define SHIFT_ROL 0 |
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#define SHIFT_ROR 1 |
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#define SHIFT_SHL 4 |
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#define SHIFT_SHR 5 |
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#define SHIFT_SAR 7 |
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#define JCC_JMP (-1) |
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#define JCC_JO 0x0 |
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#define JCC_JNO 0x1 |
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#define JCC_JB 0x2 |
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#define JCC_JAE 0x3 |
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#define JCC_JE 0x4 |
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#define JCC_JNE 0x5 |
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#define JCC_JBE 0x6 |
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#define JCC_JA 0x7 |
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#define JCC_JS 0x8 |
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#define JCC_JNS 0x9 |
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#define JCC_JP 0xa |
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#define JCC_JNP 0xb |
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#define JCC_JL 0xc |
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#define JCC_JGE 0xd |
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#define JCC_JLE 0xe |
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#define JCC_JG 0xf |
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#define P_EXT 0x100 /* 0x0f opcode prefix */ |
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static const uint8_t tcg_cond_to_jcc[10] = { |
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[TCG_COND_EQ] = JCC_JE, |
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[TCG_COND_NE] = JCC_JNE, |
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[TCG_COND_LT] = JCC_JL, |
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[TCG_COND_GE] = JCC_JGE, |
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[TCG_COND_LE] = JCC_JLE, |
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[TCG_COND_GT] = JCC_JG, |
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[TCG_COND_LTU] = JCC_JB, |
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[TCG_COND_GEU] = JCC_JAE, |
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[TCG_COND_LEU] = JCC_JBE, |
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[TCG_COND_GTU] = JCC_JA, |
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}; |
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static inline void tcg_out_opc(TCGContext *s, int opc) |
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{ |
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if (opc & P_EXT)
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tcg_out8(s, 0x0f);
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tcg_out8(s, opc); |
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} |
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static inline void tcg_out_modrm(TCGContext *s, int opc, int r, int rm) |
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{ |
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tcg_out_opc(s, opc); |
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tcg_out8(s, 0xc0 | (r << 3) | rm); |
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} |
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/* rm == -1 means no register index */
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static inline void tcg_out_modrm_offset(TCGContext *s, int opc, int r, int rm, |
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int32_t offset) |
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{ |
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tcg_out_opc(s, opc); |
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if (rm == -1) { |
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tcg_out8(s, 0x05 | (r << 3)); |
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tcg_out32(s, offset); |
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} else if (offset == 0 && rm != TCG_REG_EBP) { |
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if (rm == TCG_REG_ESP) {
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tcg_out8(s, 0x04 | (r << 3)); |
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tcg_out8(s, 0x24);
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} else {
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tcg_out8(s, 0x00 | (r << 3) | rm); |
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} |
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} else if ((int8_t)offset == offset) { |
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if (rm == TCG_REG_ESP) {
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tcg_out8(s, 0x44 | (r << 3)); |
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tcg_out8(s, 0x24);
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} else {
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tcg_out8(s, 0x40 | (r << 3) | rm); |
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} |
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tcg_out8(s, offset); |
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} else {
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if (rm == TCG_REG_ESP) {
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tcg_out8(s, 0x84 | (r << 3)); |
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tcg_out8(s, 0x24);
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} else {
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tcg_out8(s, 0x80 | (r << 3) | rm); |
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} |
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tcg_out32(s, offset); |
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} |
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} |
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static inline void tcg_out_mov(TCGContext *s, int ret, int arg) |
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{ |
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if (arg != ret)
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tcg_out_modrm(s, 0x8b, ret, arg);
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} |
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static inline void tcg_out_movi(TCGContext *s, TCGType type, |
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int ret, int32_t arg)
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{ |
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if (arg == 0) { |
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/* xor r0,r0 */
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tcg_out_modrm(s, 0x01 | (ARITH_XOR << 3), ret, ret); |
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} else {
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tcg_out8(s, 0xb8 + ret);
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tcg_out32(s, arg); |
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} |
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} |
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static inline void tcg_out_ld(TCGContext *s, TCGType type, int ret, |
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int arg1, tcg_target_long arg2)
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{ |
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/* movl */
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tcg_out_modrm_offset(s, 0x8b, ret, arg1, arg2);
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} |
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|
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static inline void tcg_out_st(TCGContext *s, TCGType type, int arg, |
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int arg1, tcg_target_long arg2)
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{ |
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/* movl */
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tcg_out_modrm_offset(s, 0x89, arg, arg1, arg2);
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} |
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|
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static inline void tgen_arithi(TCGContext *s, int c, int r0, int32_t val) |
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{ |
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if (val == (int8_t)val) {
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tcg_out_modrm(s, 0x83, c, r0);
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tcg_out8(s, val); |
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} else {
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tcg_out_modrm(s, 0x81, c, r0);
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tcg_out32(s, val); |
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} |
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} |
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|
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static void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val) |
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{ |
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if (val != 0) |
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tgen_arithi(s, ARITH_ADD, reg, val); |
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} |
295 |
|
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static void tcg_out_jxx(TCGContext *s, int opc, int label_index) |
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{ |
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int32_t val, val1; |
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TCGLabel *l = &s->labels[label_index]; |
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|
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if (l->has_value) {
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val = l->u.value - (tcg_target_long)s->code_ptr; |
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val1 = val - 2;
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if ((int8_t)val1 == val1) {
|
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if (opc == -1) |
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tcg_out8(s, 0xeb);
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else
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tcg_out8(s, 0x70 + opc);
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tcg_out8(s, val1); |
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} else {
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if (opc == -1) { |
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tcg_out8(s, 0xe9);
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tcg_out32(s, val - 5);
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} else {
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tcg_out8(s, 0x0f);
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tcg_out8(s, 0x80 + opc);
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tcg_out32(s, val - 6);
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} |
319 |
} |
320 |
} else {
|
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if (opc == -1) { |
322 |
tcg_out8(s, 0xe9);
|
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} else {
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tcg_out8(s, 0x0f);
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tcg_out8(s, 0x80 + opc);
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} |
327 |
tcg_out_reloc(s, s->code_ptr, R_386_PC32, label_index, -4);
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s->code_ptr += 4;
|
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} |
330 |
} |
331 |
|
332 |
static void tcg_out_brcond(TCGContext *s, int cond, |
333 |
TCGArg arg1, TCGArg arg2, int const_arg2,
|
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int label_index)
|
335 |
{ |
336 |
if (const_arg2) {
|
337 |
if (arg2 == 0) { |
338 |
/* test r, r */
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tcg_out_modrm(s, 0x85, arg1, arg1);
|
340 |
} else {
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tgen_arithi(s, ARITH_CMP, arg1, arg2); |
342 |
} |
343 |
} else {
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344 |
tcg_out_modrm(s, 0x01 | (ARITH_CMP << 3), arg2, arg1); |
345 |
} |
346 |
tcg_out_jxx(s, tcg_cond_to_jcc[cond], label_index); |
347 |
} |
348 |
|
349 |
/* XXX: we implement it at the target level to avoid having to
|
350 |
handle cross basic blocks temporaries */
|
351 |
static void tcg_out_brcond2(TCGContext *s, |
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const TCGArg *args, const int *const_args) |
353 |
{ |
354 |
int label_next;
|
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label_next = gen_new_label(); |
356 |
switch(args[4]) { |
357 |
case TCG_COND_EQ:
|
358 |
tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], label_next); |
359 |
tcg_out_brcond(s, TCG_COND_EQ, args[1], args[3], const_args[3], args[5]); |
360 |
break;
|
361 |
case TCG_COND_NE:
|
362 |
tcg_out_brcond(s, TCG_COND_NE, args[0], args[2], const_args[2], args[5]); |
363 |
tcg_out_brcond(s, TCG_COND_NE, args[1], args[3], const_args[3], args[5]); |
364 |
break;
|
365 |
case TCG_COND_LT:
|
366 |
tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]); |
367 |
tcg_out_jxx(s, JCC_JNE, label_next); |
368 |
tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]); |
369 |
break;
|
370 |
case TCG_COND_LE:
|
371 |
tcg_out_brcond(s, TCG_COND_LT, args[1], args[3], const_args[3], args[5]); |
372 |
tcg_out_jxx(s, JCC_JNE, label_next); |
373 |
tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]); |
374 |
break;
|
375 |
case TCG_COND_GT:
|
376 |
tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]); |
377 |
tcg_out_jxx(s, JCC_JNE, label_next); |
378 |
tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]); |
379 |
break;
|
380 |
case TCG_COND_GE:
|
381 |
tcg_out_brcond(s, TCG_COND_GT, args[1], args[3], const_args[3], args[5]); |
382 |
tcg_out_jxx(s, JCC_JNE, label_next); |
383 |
tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]); |
384 |
break;
|
385 |
case TCG_COND_LTU:
|
386 |
tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]); |
387 |
tcg_out_jxx(s, JCC_JNE, label_next); |
388 |
tcg_out_brcond(s, TCG_COND_LTU, args[0], args[2], const_args[2], args[5]); |
389 |
break;
|
390 |
case TCG_COND_LEU:
|
391 |
tcg_out_brcond(s, TCG_COND_LTU, args[1], args[3], const_args[3], args[5]); |
392 |
tcg_out_jxx(s, JCC_JNE, label_next); |
393 |
tcg_out_brcond(s, TCG_COND_LEU, args[0], args[2], const_args[2], args[5]); |
394 |
break;
|
395 |
case TCG_COND_GTU:
|
396 |
tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]); |
397 |
tcg_out_jxx(s, JCC_JNE, label_next); |
398 |
tcg_out_brcond(s, TCG_COND_GTU, args[0], args[2], const_args[2], args[5]); |
399 |
break;
|
400 |
case TCG_COND_GEU:
|
401 |
tcg_out_brcond(s, TCG_COND_GTU, args[1], args[3], const_args[3], args[5]); |
402 |
tcg_out_jxx(s, JCC_JNE, label_next); |
403 |
tcg_out_brcond(s, TCG_COND_GEU, args[0], args[2], const_args[2], args[5]); |
404 |
break;
|
405 |
default:
|
406 |
tcg_abort(); |
407 |
} |
408 |
tcg_out_label(s, label_next, (tcg_target_long)s->code_ptr); |
409 |
} |
410 |
|
411 |
#if defined(CONFIG_SOFTMMU)
|
412 |
|
413 |
#include "../../softmmu_defs.h" |
414 |
|
415 |
static void *qemu_ld_helpers[4] = { |
416 |
__ldb_mmu, |
417 |
__ldw_mmu, |
418 |
__ldl_mmu, |
419 |
__ldq_mmu, |
420 |
}; |
421 |
|
422 |
static void *qemu_st_helpers[4] = { |
423 |
__stb_mmu, |
424 |
__stw_mmu, |
425 |
__stl_mmu, |
426 |
__stq_mmu, |
427 |
}; |
428 |
#endif
|
429 |
|
430 |
#ifndef CONFIG_USER_ONLY
|
431 |
#define GUEST_BASE 0 |
432 |
#endif
|
433 |
|
434 |
/* XXX: qemu_ld and qemu_st could be modified to clobber only EDX and
|
435 |
EAX. It will be useful once fixed registers globals are less
|
436 |
common. */
|
437 |
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, |
438 |
int opc)
|
439 |
{ |
440 |
int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
|
441 |
#if defined(CONFIG_SOFTMMU)
|
442 |
uint8_t *label1_ptr, *label2_ptr; |
443 |
#endif
|
444 |
#if TARGET_LONG_BITS == 64 |
445 |
#if defined(CONFIG_SOFTMMU)
|
446 |
uint8_t *label3_ptr; |
447 |
#endif
|
448 |
int addr_reg2;
|
449 |
#endif
|
450 |
|
451 |
data_reg = *args++; |
452 |
if (opc == 3) |
453 |
data_reg2 = *args++; |
454 |
else
|
455 |
data_reg2 = 0;
|
456 |
addr_reg = *args++; |
457 |
#if TARGET_LONG_BITS == 64 |
458 |
addr_reg2 = *args++; |
459 |
#endif
|
460 |
mem_index = *args; |
461 |
s_bits = opc & 3;
|
462 |
|
463 |
r0 = TCG_REG_EAX; |
464 |
r1 = TCG_REG_EDX; |
465 |
|
466 |
#if defined(CONFIG_SOFTMMU)
|
467 |
tcg_out_mov(s, r1, addr_reg); |
468 |
|
469 |
tcg_out_mov(s, r0, addr_reg); |
470 |
|
471 |
tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */ |
472 |
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
473 |
|
474 |
tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */ |
475 |
tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
476 |
|
477 |
tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
478 |
tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
479 |
|
480 |
tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */ |
481 |
tcg_out8(s, 0x80 | (r1 << 3) | 0x04); |
482 |
tcg_out8(s, (5 << 3) | r1); |
483 |
tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_read));
|
484 |
|
485 |
/* cmp 0(r1), r0 */
|
486 |
tcg_out_modrm_offset(s, 0x3b, r0, r1, 0); |
487 |
|
488 |
tcg_out_mov(s, r0, addr_reg); |
489 |
|
490 |
#if TARGET_LONG_BITS == 32 |
491 |
/* je label1 */
|
492 |
tcg_out8(s, 0x70 + JCC_JE);
|
493 |
label1_ptr = s->code_ptr; |
494 |
s->code_ptr++; |
495 |
#else
|
496 |
/* jne label3 */
|
497 |
tcg_out8(s, 0x70 + JCC_JNE);
|
498 |
label3_ptr = s->code_ptr; |
499 |
s->code_ptr++; |
500 |
|
501 |
/* cmp 4(r1), addr_reg2 */
|
502 |
tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4); |
503 |
|
504 |
/* je label1 */
|
505 |
tcg_out8(s, 0x70 + JCC_JE);
|
506 |
label1_ptr = s->code_ptr; |
507 |
s->code_ptr++; |
508 |
|
509 |
/* label3: */
|
510 |
*label3_ptr = s->code_ptr - label3_ptr - 1;
|
511 |
#endif
|
512 |
|
513 |
/* XXX: move that code at the end of the TB */
|
514 |
#if TARGET_LONG_BITS == 32 |
515 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EDX, mem_index); |
516 |
#else
|
517 |
tcg_out_mov(s, TCG_REG_EDX, addr_reg2); |
518 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index); |
519 |
#endif
|
520 |
tcg_out8(s, 0xe8);
|
521 |
tcg_out32(s, (tcg_target_long)qemu_ld_helpers[s_bits] - |
522 |
(tcg_target_long)s->code_ptr - 4);
|
523 |
|
524 |
switch(opc) {
|
525 |
case 0 | 4: |
526 |
/* movsbl */
|
527 |
tcg_out_modrm(s, 0xbe | P_EXT, data_reg, TCG_REG_EAX);
|
528 |
break;
|
529 |
case 1 | 4: |
530 |
/* movswl */
|
531 |
tcg_out_modrm(s, 0xbf | P_EXT, data_reg, TCG_REG_EAX);
|
532 |
break;
|
533 |
case 0: |
534 |
/* movzbl */
|
535 |
tcg_out_modrm(s, 0xb6 | P_EXT, data_reg, TCG_REG_EAX);
|
536 |
break;
|
537 |
case 1: |
538 |
/* movzwl */
|
539 |
tcg_out_modrm(s, 0xb7 | P_EXT, data_reg, TCG_REG_EAX);
|
540 |
break;
|
541 |
case 2: |
542 |
default:
|
543 |
tcg_out_mov(s, data_reg, TCG_REG_EAX); |
544 |
break;
|
545 |
case 3: |
546 |
if (data_reg == TCG_REG_EDX) {
|
547 |
tcg_out_opc(s, 0x90 + TCG_REG_EDX); /* xchg %edx, %eax */ |
548 |
tcg_out_mov(s, data_reg2, TCG_REG_EAX); |
549 |
} else {
|
550 |
tcg_out_mov(s, data_reg, TCG_REG_EAX); |
551 |
tcg_out_mov(s, data_reg2, TCG_REG_EDX); |
552 |
} |
553 |
break;
|
554 |
} |
555 |
|
556 |
/* jmp label2 */
|
557 |
tcg_out8(s, 0xeb);
|
558 |
label2_ptr = s->code_ptr; |
559 |
s->code_ptr++; |
560 |
|
561 |
/* label1: */
|
562 |
*label1_ptr = s->code_ptr - label1_ptr - 1;
|
563 |
|
564 |
/* add x(r1), r0 */
|
565 |
tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
|
566 |
offsetof(CPUTLBEntry, addr_read)); |
567 |
#else
|
568 |
r0 = addr_reg; |
569 |
#endif
|
570 |
|
571 |
#ifdef TARGET_WORDS_BIGENDIAN
|
572 |
bswap = 1;
|
573 |
#else
|
574 |
bswap = 0;
|
575 |
#endif
|
576 |
switch(opc) {
|
577 |
case 0: |
578 |
/* movzbl */
|
579 |
tcg_out_modrm_offset(s, 0xb6 | P_EXT, data_reg, r0, GUEST_BASE);
|
580 |
break;
|
581 |
case 0 | 4: |
582 |
/* movsbl */
|
583 |
tcg_out_modrm_offset(s, 0xbe | P_EXT, data_reg, r0, GUEST_BASE);
|
584 |
break;
|
585 |
case 1: |
586 |
/* movzwl */
|
587 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, data_reg, r0, GUEST_BASE);
|
588 |
if (bswap) {
|
589 |
/* rolw $8, data_reg */
|
590 |
tcg_out8(s, 0x66);
|
591 |
tcg_out_modrm(s, 0xc1, 0, data_reg); |
592 |
tcg_out8(s, 8);
|
593 |
} |
594 |
break;
|
595 |
case 1 | 4: |
596 |
/* movswl */
|
597 |
tcg_out_modrm_offset(s, 0xbf | P_EXT, data_reg, r0, GUEST_BASE);
|
598 |
if (bswap) {
|
599 |
/* rolw $8, data_reg */
|
600 |
tcg_out8(s, 0x66);
|
601 |
tcg_out_modrm(s, 0xc1, 0, data_reg); |
602 |
tcg_out8(s, 8);
|
603 |
|
604 |
/* movswl data_reg, data_reg */
|
605 |
tcg_out_modrm(s, 0xbf | P_EXT, data_reg, data_reg);
|
606 |
} |
607 |
break;
|
608 |
case 2: |
609 |
/* movl (r0), data_reg */
|
610 |
tcg_out_modrm_offset(s, 0x8b, data_reg, r0, GUEST_BASE);
|
611 |
if (bswap) {
|
612 |
/* bswap */
|
613 |
tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
|
614 |
} |
615 |
break;
|
616 |
case 3: |
617 |
/* XXX: could be nicer */
|
618 |
if (r0 == data_reg) {
|
619 |
r1 = TCG_REG_EDX; |
620 |
if (r1 == data_reg)
|
621 |
r1 = TCG_REG_EAX; |
622 |
tcg_out_mov(s, r1, r0); |
623 |
r0 = r1; |
624 |
} |
625 |
if (!bswap) {
|
626 |
tcg_out_modrm_offset(s, 0x8b, data_reg, r0, GUEST_BASE);
|
627 |
tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, GUEST_BASE + 4); |
628 |
} else {
|
629 |
tcg_out_modrm_offset(s, 0x8b, data_reg, r0, GUEST_BASE + 4); |
630 |
tcg_out_opc(s, (0xc8 + data_reg) | P_EXT);
|
631 |
|
632 |
tcg_out_modrm_offset(s, 0x8b, data_reg2, r0, GUEST_BASE);
|
633 |
/* bswap */
|
634 |
tcg_out_opc(s, (0xc8 + data_reg2) | P_EXT);
|
635 |
} |
636 |
break;
|
637 |
default:
|
638 |
tcg_abort(); |
639 |
} |
640 |
|
641 |
#if defined(CONFIG_SOFTMMU)
|
642 |
/* label2: */
|
643 |
*label2_ptr = s->code_ptr - label2_ptr - 1;
|
644 |
#endif
|
645 |
} |
646 |
|
647 |
|
648 |
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, |
649 |
int opc)
|
650 |
{ |
651 |
int addr_reg, data_reg, data_reg2, r0, r1, mem_index, s_bits, bswap;
|
652 |
#if defined(CONFIG_SOFTMMU)
|
653 |
uint8_t *label1_ptr, *label2_ptr; |
654 |
#endif
|
655 |
#if TARGET_LONG_BITS == 64 |
656 |
#if defined(CONFIG_SOFTMMU)
|
657 |
uint8_t *label3_ptr; |
658 |
#endif
|
659 |
int addr_reg2;
|
660 |
#endif
|
661 |
|
662 |
data_reg = *args++; |
663 |
if (opc == 3) |
664 |
data_reg2 = *args++; |
665 |
else
|
666 |
data_reg2 = 0;
|
667 |
addr_reg = *args++; |
668 |
#if TARGET_LONG_BITS == 64 |
669 |
addr_reg2 = *args++; |
670 |
#endif
|
671 |
mem_index = *args; |
672 |
|
673 |
s_bits = opc; |
674 |
|
675 |
r0 = TCG_REG_EAX; |
676 |
r1 = TCG_REG_EDX; |
677 |
|
678 |
#if defined(CONFIG_SOFTMMU)
|
679 |
tcg_out_mov(s, r1, addr_reg); |
680 |
|
681 |
tcg_out_mov(s, r0, addr_reg); |
682 |
|
683 |
tcg_out_modrm(s, 0xc1, 5, r1); /* shr $x, r1 */ |
684 |
tcg_out8(s, TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); |
685 |
|
686 |
tcg_out_modrm(s, 0x81, 4, r0); /* andl $x, r0 */ |
687 |
tcg_out32(s, TARGET_PAGE_MASK | ((1 << s_bits) - 1)); |
688 |
|
689 |
tcg_out_modrm(s, 0x81, 4, r1); /* andl $x, r1 */ |
690 |
tcg_out32(s, (CPU_TLB_SIZE - 1) << CPU_TLB_ENTRY_BITS);
|
691 |
|
692 |
tcg_out_opc(s, 0x8d); /* lea offset(r1, %ebp), r1 */ |
693 |
tcg_out8(s, 0x80 | (r1 << 3) | 0x04); |
694 |
tcg_out8(s, (5 << 3) | r1); |
695 |
tcg_out32(s, offsetof(CPUState, tlb_table[mem_index][0].addr_write));
|
696 |
|
697 |
/* cmp 0(r1), r0 */
|
698 |
tcg_out_modrm_offset(s, 0x3b, r0, r1, 0); |
699 |
|
700 |
tcg_out_mov(s, r0, addr_reg); |
701 |
|
702 |
#if TARGET_LONG_BITS == 32 |
703 |
/* je label1 */
|
704 |
tcg_out8(s, 0x70 + JCC_JE);
|
705 |
label1_ptr = s->code_ptr; |
706 |
s->code_ptr++; |
707 |
#else
|
708 |
/* jne label3 */
|
709 |
tcg_out8(s, 0x70 + JCC_JNE);
|
710 |
label3_ptr = s->code_ptr; |
711 |
s->code_ptr++; |
712 |
|
713 |
/* cmp 4(r1), addr_reg2 */
|
714 |
tcg_out_modrm_offset(s, 0x3b, addr_reg2, r1, 4); |
715 |
|
716 |
/* je label1 */
|
717 |
tcg_out8(s, 0x70 + JCC_JE);
|
718 |
label1_ptr = s->code_ptr; |
719 |
s->code_ptr++; |
720 |
|
721 |
/* label3: */
|
722 |
*label3_ptr = s->code_ptr - label3_ptr - 1;
|
723 |
#endif
|
724 |
|
725 |
/* XXX: move that code at the end of the TB */
|
726 |
#if TARGET_LONG_BITS == 32 |
727 |
if (opc == 3) { |
728 |
tcg_out_mov(s, TCG_REG_EDX, data_reg); |
729 |
tcg_out_mov(s, TCG_REG_ECX, data_reg2); |
730 |
tcg_out8(s, 0x6a); /* push Ib */ |
731 |
tcg_out8(s, mem_index); |
732 |
tcg_out8(s, 0xe8);
|
733 |
tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
734 |
(tcg_target_long)s->code_ptr - 4);
|
735 |
tcg_out_addi(s, TCG_REG_ESP, 4);
|
736 |
} else {
|
737 |
switch(opc) {
|
738 |
case 0: |
739 |
/* movzbl */
|
740 |
tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_EDX, data_reg);
|
741 |
break;
|
742 |
case 1: |
743 |
/* movzwl */
|
744 |
tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_EDX, data_reg);
|
745 |
break;
|
746 |
case 2: |
747 |
tcg_out_mov(s, TCG_REG_EDX, data_reg); |
748 |
break;
|
749 |
} |
750 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_ECX, mem_index); |
751 |
tcg_out8(s, 0xe8);
|
752 |
tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
753 |
(tcg_target_long)s->code_ptr - 4);
|
754 |
} |
755 |
#else
|
756 |
if (opc == 3) { |
757 |
tcg_out_mov(s, TCG_REG_EDX, addr_reg2); |
758 |
tcg_out8(s, 0x6a); /* push Ib */ |
759 |
tcg_out8(s, mem_index); |
760 |
tcg_out_opc(s, 0x50 + data_reg2); /* push */ |
761 |
tcg_out_opc(s, 0x50 + data_reg); /* push */ |
762 |
tcg_out8(s, 0xe8);
|
763 |
tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
764 |
(tcg_target_long)s->code_ptr - 4);
|
765 |
tcg_out_addi(s, TCG_REG_ESP, 12);
|
766 |
} else {
|
767 |
tcg_out_mov(s, TCG_REG_EDX, addr_reg2); |
768 |
switch(opc) {
|
769 |
case 0: |
770 |
/* movzbl */
|
771 |
tcg_out_modrm(s, 0xb6 | P_EXT, TCG_REG_ECX, data_reg);
|
772 |
break;
|
773 |
case 1: |
774 |
/* movzwl */
|
775 |
tcg_out_modrm(s, 0xb7 | P_EXT, TCG_REG_ECX, data_reg);
|
776 |
break;
|
777 |
case 2: |
778 |
tcg_out_mov(s, TCG_REG_ECX, data_reg); |
779 |
break;
|
780 |
} |
781 |
tcg_out8(s, 0x6a); /* push Ib */ |
782 |
tcg_out8(s, mem_index); |
783 |
tcg_out8(s, 0xe8);
|
784 |
tcg_out32(s, (tcg_target_long)qemu_st_helpers[s_bits] - |
785 |
(tcg_target_long)s->code_ptr - 4);
|
786 |
tcg_out_addi(s, TCG_REG_ESP, 4);
|
787 |
} |
788 |
#endif
|
789 |
|
790 |
/* jmp label2 */
|
791 |
tcg_out8(s, 0xeb);
|
792 |
label2_ptr = s->code_ptr; |
793 |
s->code_ptr++; |
794 |
|
795 |
/* label1: */
|
796 |
*label1_ptr = s->code_ptr - label1_ptr - 1;
|
797 |
|
798 |
/* add x(r1), r0 */
|
799 |
tcg_out_modrm_offset(s, 0x03, r0, r1, offsetof(CPUTLBEntry, addend) -
|
800 |
offsetof(CPUTLBEntry, addr_write)); |
801 |
#else
|
802 |
r0 = addr_reg; |
803 |
#endif
|
804 |
|
805 |
#ifdef TARGET_WORDS_BIGENDIAN
|
806 |
bswap = 1;
|
807 |
#else
|
808 |
bswap = 0;
|
809 |
#endif
|
810 |
switch(opc) {
|
811 |
case 0: |
812 |
/* movb */
|
813 |
tcg_out_modrm_offset(s, 0x88, data_reg, r0, GUEST_BASE);
|
814 |
break;
|
815 |
case 1: |
816 |
if (bswap) {
|
817 |
tcg_out_mov(s, r1, data_reg); |
818 |
tcg_out8(s, 0x66); /* rolw $8, %ecx */ |
819 |
tcg_out_modrm(s, 0xc1, 0, r1); |
820 |
tcg_out8(s, 8);
|
821 |
data_reg = r1; |
822 |
} |
823 |
/* movw */
|
824 |
tcg_out8(s, 0x66);
|
825 |
tcg_out_modrm_offset(s, 0x89, data_reg, r0, GUEST_BASE);
|
826 |
break;
|
827 |
case 2: |
828 |
if (bswap) {
|
829 |
tcg_out_mov(s, r1, data_reg); |
830 |
/* bswap data_reg */
|
831 |
tcg_out_opc(s, (0xc8 + r1) | P_EXT);
|
832 |
data_reg = r1; |
833 |
} |
834 |
/* movl */
|
835 |
tcg_out_modrm_offset(s, 0x89, data_reg, r0, GUEST_BASE);
|
836 |
break;
|
837 |
case 3: |
838 |
if (bswap) {
|
839 |
tcg_out_mov(s, r1, data_reg2); |
840 |
/* bswap data_reg */
|
841 |
tcg_out_opc(s, (0xc8 + r1) | P_EXT);
|
842 |
tcg_out_modrm_offset(s, 0x89, r1, r0, GUEST_BASE);
|
843 |
tcg_out_mov(s, r1, data_reg); |
844 |
/* bswap data_reg */
|
845 |
tcg_out_opc(s, (0xc8 + r1) | P_EXT);
|
846 |
tcg_out_modrm_offset(s, 0x89, r1, r0, GUEST_BASE + 4); |
847 |
} else {
|
848 |
tcg_out_modrm_offset(s, 0x89, data_reg, r0, GUEST_BASE);
|
849 |
tcg_out_modrm_offset(s, 0x89, data_reg2, r0, GUEST_BASE + 4); |
850 |
} |
851 |
break;
|
852 |
default:
|
853 |
tcg_abort(); |
854 |
} |
855 |
|
856 |
#if defined(CONFIG_SOFTMMU)
|
857 |
/* label2: */
|
858 |
*label2_ptr = s->code_ptr - label2_ptr - 1;
|
859 |
#endif
|
860 |
} |
861 |
|
862 |
static inline void tcg_out_op(TCGContext *s, int opc, |
863 |
const TCGArg *args, const int *const_args) |
864 |
{ |
865 |
int c;
|
866 |
|
867 |
switch(opc) {
|
868 |
case INDEX_op_exit_tb:
|
869 |
tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_EAX, args[0]);
|
870 |
tcg_out8(s, 0xe9); /* jmp tb_ret_addr */ |
871 |
tcg_out32(s, tb_ret_addr - s->code_ptr - 4);
|
872 |
break;
|
873 |
case INDEX_op_goto_tb:
|
874 |
if (s->tb_jmp_offset) {
|
875 |
/* direct jump method */
|
876 |
tcg_out8(s, 0xe9); /* jmp im */ |
877 |
s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
|
878 |
tcg_out32(s, 0);
|
879 |
} else {
|
880 |
/* indirect jump method */
|
881 |
/* jmp Ev */
|
882 |
tcg_out_modrm_offset(s, 0xff, 4, -1, |
883 |
(tcg_target_long)(s->tb_next + args[0]));
|
884 |
} |
885 |
s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
|
886 |
break;
|
887 |
case INDEX_op_call:
|
888 |
if (const_args[0]) { |
889 |
tcg_out8(s, 0xe8);
|
890 |
tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
891 |
} else {
|
892 |
tcg_out_modrm(s, 0xff, 2, args[0]); |
893 |
} |
894 |
break;
|
895 |
case INDEX_op_jmp:
|
896 |
if (const_args[0]) { |
897 |
tcg_out8(s, 0xe9);
|
898 |
tcg_out32(s, args[0] - (tcg_target_long)s->code_ptr - 4); |
899 |
} else {
|
900 |
tcg_out_modrm(s, 0xff, 4, args[0]); |
901 |
} |
902 |
break;
|
903 |
case INDEX_op_br:
|
904 |
tcg_out_jxx(s, JCC_JMP, args[0]);
|
905 |
break;
|
906 |
case INDEX_op_movi_i32:
|
907 |
tcg_out_movi(s, TCG_TYPE_I32, args[0], args[1]); |
908 |
break;
|
909 |
case INDEX_op_ld8u_i32:
|
910 |
/* movzbl */
|
911 |
tcg_out_modrm_offset(s, 0xb6 | P_EXT, args[0], args[1], args[2]); |
912 |
break;
|
913 |
case INDEX_op_ld8s_i32:
|
914 |
/* movsbl */
|
915 |
tcg_out_modrm_offset(s, 0xbe | P_EXT, args[0], args[1], args[2]); |
916 |
break;
|
917 |
case INDEX_op_ld16u_i32:
|
918 |
/* movzwl */
|
919 |
tcg_out_modrm_offset(s, 0xb7 | P_EXT, args[0], args[1], args[2]); |
920 |
break;
|
921 |
case INDEX_op_ld16s_i32:
|
922 |
/* movswl */
|
923 |
tcg_out_modrm_offset(s, 0xbf | P_EXT, args[0], args[1], args[2]); |
924 |
break;
|
925 |
case INDEX_op_ld_i32:
|
926 |
/* movl */
|
927 |
tcg_out_modrm_offset(s, 0x8b, args[0], args[1], args[2]); |
928 |
break;
|
929 |
case INDEX_op_st8_i32:
|
930 |
/* movb */
|
931 |
tcg_out_modrm_offset(s, 0x88, args[0], args[1], args[2]); |
932 |
break;
|
933 |
case INDEX_op_st16_i32:
|
934 |
/* movw */
|
935 |
tcg_out8(s, 0x66);
|
936 |
tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
937 |
break;
|
938 |
case INDEX_op_st_i32:
|
939 |
/* movl */
|
940 |
tcg_out_modrm_offset(s, 0x89, args[0], args[1], args[2]); |
941 |
break;
|
942 |
case INDEX_op_sub_i32:
|
943 |
c = ARITH_SUB; |
944 |
goto gen_arith;
|
945 |
case INDEX_op_and_i32:
|
946 |
c = ARITH_AND; |
947 |
goto gen_arith;
|
948 |
case INDEX_op_or_i32:
|
949 |
c = ARITH_OR; |
950 |
goto gen_arith;
|
951 |
case INDEX_op_xor_i32:
|
952 |
c = ARITH_XOR; |
953 |
goto gen_arith;
|
954 |
case INDEX_op_add_i32:
|
955 |
c = ARITH_ADD; |
956 |
gen_arith:
|
957 |
if (const_args[2]) { |
958 |
tgen_arithi(s, c, args[0], args[2]); |
959 |
} else {
|
960 |
tcg_out_modrm(s, 0x01 | (c << 3), args[2], args[0]); |
961 |
} |
962 |
break;
|
963 |
case INDEX_op_mul_i32:
|
964 |
if (const_args[2]) { |
965 |
int32_t val; |
966 |
val = args[2];
|
967 |
if (val == (int8_t)val) {
|
968 |
tcg_out_modrm(s, 0x6b, args[0], args[0]); |
969 |
tcg_out8(s, val); |
970 |
} else {
|
971 |
tcg_out_modrm(s, 0x69, args[0], args[0]); |
972 |
tcg_out32(s, val); |
973 |
} |
974 |
} else {
|
975 |
tcg_out_modrm(s, 0xaf | P_EXT, args[0], args[2]); |
976 |
} |
977 |
break;
|
978 |
case INDEX_op_mulu2_i32:
|
979 |
tcg_out_modrm(s, 0xf7, 4, args[3]); |
980 |
break;
|
981 |
case INDEX_op_div2_i32:
|
982 |
tcg_out_modrm(s, 0xf7, 7, args[4]); |
983 |
break;
|
984 |
case INDEX_op_divu2_i32:
|
985 |
tcg_out_modrm(s, 0xf7, 6, args[4]); |
986 |
break;
|
987 |
case INDEX_op_shl_i32:
|
988 |
c = SHIFT_SHL; |
989 |
gen_shift32:
|
990 |
if (const_args[2]) { |
991 |
if (args[2] == 1) { |
992 |
tcg_out_modrm(s, 0xd1, c, args[0]); |
993 |
} else {
|
994 |
tcg_out_modrm(s, 0xc1, c, args[0]); |
995 |
tcg_out8(s, args[2]);
|
996 |
} |
997 |
} else {
|
998 |
tcg_out_modrm(s, 0xd3, c, args[0]); |
999 |
} |
1000 |
break;
|
1001 |
case INDEX_op_shr_i32:
|
1002 |
c = SHIFT_SHR; |
1003 |
goto gen_shift32;
|
1004 |
case INDEX_op_sar_i32:
|
1005 |
c = SHIFT_SAR; |
1006 |
goto gen_shift32;
|
1007 |
case INDEX_op_rotl_i32:
|
1008 |
c = SHIFT_ROL; |
1009 |
goto gen_shift32;
|
1010 |
case INDEX_op_rotr_i32:
|
1011 |
c = SHIFT_ROR; |
1012 |
goto gen_shift32;
|
1013 |
|
1014 |
case INDEX_op_add2_i32:
|
1015 |
if (const_args[4]) |
1016 |
tgen_arithi(s, ARITH_ADD, args[0], args[4]); |
1017 |
else
|
1018 |
tcg_out_modrm(s, 0x01 | (ARITH_ADD << 3), args[4], args[0]); |
1019 |
if (const_args[5]) |
1020 |
tgen_arithi(s, ARITH_ADC, args[1], args[5]); |
1021 |
else
|
1022 |
tcg_out_modrm(s, 0x01 | (ARITH_ADC << 3), args[5], args[1]); |
1023 |
break;
|
1024 |
case INDEX_op_sub2_i32:
|
1025 |
if (const_args[4]) |
1026 |
tgen_arithi(s, ARITH_SUB, args[0], args[4]); |
1027 |
else
|
1028 |
tcg_out_modrm(s, 0x01 | (ARITH_SUB << 3), args[4], args[0]); |
1029 |
if (const_args[5]) |
1030 |
tgen_arithi(s, ARITH_SBB, args[1], args[5]); |
1031 |
else
|
1032 |
tcg_out_modrm(s, 0x01 | (ARITH_SBB << 3), args[5], args[1]); |
1033 |
break;
|
1034 |
case INDEX_op_brcond_i32:
|
1035 |
tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], args[3]); |
1036 |
break;
|
1037 |
case INDEX_op_brcond2_i32:
|
1038 |
tcg_out_brcond2(s, args, const_args); |
1039 |
break;
|
1040 |
|
1041 |
case INDEX_op_bswap16_i32:
|
1042 |
tcg_out8(s, 0x66);
|
1043 |
tcg_out_modrm(s, 0xc1, SHIFT_ROL, args[0]); |
1044 |
tcg_out8(s, 8);
|
1045 |
break;
|
1046 |
case INDEX_op_bswap32_i32:
|
1047 |
tcg_out_opc(s, (0xc8 + args[0]) | P_EXT); |
1048 |
break;
|
1049 |
|
1050 |
case INDEX_op_neg_i32:
|
1051 |
tcg_out_modrm(s, 0xf7, 3, args[0]); |
1052 |
break;
|
1053 |
|
1054 |
case INDEX_op_not_i32:
|
1055 |
tcg_out_modrm(s, 0xf7, 2, args[0]); |
1056 |
break;
|
1057 |
|
1058 |
case INDEX_op_ext8s_i32:
|
1059 |
tcg_out_modrm(s, 0xbe | P_EXT, args[0], args[1]); |
1060 |
break;
|
1061 |
case INDEX_op_ext16s_i32:
|
1062 |
tcg_out_modrm(s, 0xbf | P_EXT, args[0], args[1]); |
1063 |
break;
|
1064 |
|
1065 |
case INDEX_op_qemu_ld8u:
|
1066 |
tcg_out_qemu_ld(s, args, 0);
|
1067 |
break;
|
1068 |
case INDEX_op_qemu_ld8s:
|
1069 |
tcg_out_qemu_ld(s, args, 0 | 4); |
1070 |
break;
|
1071 |
case INDEX_op_qemu_ld16u:
|
1072 |
tcg_out_qemu_ld(s, args, 1);
|
1073 |
break;
|
1074 |
case INDEX_op_qemu_ld16s:
|
1075 |
tcg_out_qemu_ld(s, args, 1 | 4); |
1076 |
break;
|
1077 |
case INDEX_op_qemu_ld32u:
|
1078 |
tcg_out_qemu_ld(s, args, 2);
|
1079 |
break;
|
1080 |
case INDEX_op_qemu_ld64:
|
1081 |
tcg_out_qemu_ld(s, args, 3);
|
1082 |
break;
|
1083 |
|
1084 |
case INDEX_op_qemu_st8:
|
1085 |
tcg_out_qemu_st(s, args, 0);
|
1086 |
break;
|
1087 |
case INDEX_op_qemu_st16:
|
1088 |
tcg_out_qemu_st(s, args, 1);
|
1089 |
break;
|
1090 |
case INDEX_op_qemu_st32:
|
1091 |
tcg_out_qemu_st(s, args, 2);
|
1092 |
break;
|
1093 |
case INDEX_op_qemu_st64:
|
1094 |
tcg_out_qemu_st(s, args, 3);
|
1095 |
break;
|
1096 |
|
1097 |
default:
|
1098 |
tcg_abort(); |
1099 |
} |
1100 |
} |
1101 |
|
1102 |
static const TCGTargetOpDef x86_op_defs[] = { |
1103 |
{ INDEX_op_exit_tb, { } }, |
1104 |
{ INDEX_op_goto_tb, { } }, |
1105 |
{ INDEX_op_call, { "ri" } },
|
1106 |
{ INDEX_op_jmp, { "ri" } },
|
1107 |
{ INDEX_op_br, { } }, |
1108 |
{ INDEX_op_mov_i32, { "r", "r" } }, |
1109 |
{ INDEX_op_movi_i32, { "r" } },
|
1110 |
{ INDEX_op_ld8u_i32, { "r", "r" } }, |
1111 |
{ INDEX_op_ld8s_i32, { "r", "r" } }, |
1112 |
{ INDEX_op_ld16u_i32, { "r", "r" } }, |
1113 |
{ INDEX_op_ld16s_i32, { "r", "r" } }, |
1114 |
{ INDEX_op_ld_i32, { "r", "r" } }, |
1115 |
{ INDEX_op_st8_i32, { "q", "r" } }, |
1116 |
{ INDEX_op_st16_i32, { "r", "r" } }, |
1117 |
{ INDEX_op_st_i32, { "r", "r" } }, |
1118 |
|
1119 |
{ INDEX_op_add_i32, { "r", "0", "ri" } }, |
1120 |
{ INDEX_op_sub_i32, { "r", "0", "ri" } }, |
1121 |
{ INDEX_op_mul_i32, { "r", "0", "ri" } }, |
1122 |
{ INDEX_op_mulu2_i32, { "a", "d", "a", "r" } }, |
1123 |
{ INDEX_op_div2_i32, { "a", "d", "0", "1", "r" } }, |
1124 |
{ INDEX_op_divu2_i32, { "a", "d", "0", "1", "r" } }, |
1125 |
{ INDEX_op_and_i32, { "r", "0", "ri" } }, |
1126 |
{ INDEX_op_or_i32, { "r", "0", "ri" } }, |
1127 |
{ INDEX_op_xor_i32, { "r", "0", "ri" } }, |
1128 |
|
1129 |
{ INDEX_op_shl_i32, { "r", "0", "ci" } }, |
1130 |
{ INDEX_op_shr_i32, { "r", "0", "ci" } }, |
1131 |
{ INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1132 |
{ INDEX_op_sar_i32, { "r", "0", "ci" } }, |
1133 |
{ INDEX_op_rotl_i32, { "r", "0", "ci" } }, |
1134 |
{ INDEX_op_rotr_i32, { "r", "0", "ci" } }, |
1135 |
|
1136 |
{ INDEX_op_brcond_i32, { "r", "ri" } }, |
1137 |
|
1138 |
{ INDEX_op_add2_i32, { "r", "r", "0", "1", "ri", "ri" } }, |
1139 |
{ INDEX_op_sub2_i32, { "r", "r", "0", "1", "ri", "ri" } }, |
1140 |
{ INDEX_op_brcond2_i32, { "r", "r", "ri", "ri" } }, |
1141 |
|
1142 |
{ INDEX_op_bswap16_i32, { "r", "0" } }, |
1143 |
{ INDEX_op_bswap32_i32, { "r", "0" } }, |
1144 |
|
1145 |
{ INDEX_op_neg_i32, { "r", "0" } }, |
1146 |
|
1147 |
{ INDEX_op_not_i32, { "r", "0" } }, |
1148 |
|
1149 |
{ INDEX_op_ext8s_i32, { "r", "q" } }, |
1150 |
{ INDEX_op_ext16s_i32, { "r", "r" } }, |
1151 |
|
1152 |
#if TARGET_LONG_BITS == 32 |
1153 |
{ INDEX_op_qemu_ld8u, { "r", "L" } }, |
1154 |
{ INDEX_op_qemu_ld8s, { "r", "L" } }, |
1155 |
{ INDEX_op_qemu_ld16u, { "r", "L" } }, |
1156 |
{ INDEX_op_qemu_ld16s, { "r", "L" } }, |
1157 |
{ INDEX_op_qemu_ld32u, { "r", "L" } }, |
1158 |
{ INDEX_op_qemu_ld64, { "r", "r", "L" } }, |
1159 |
|
1160 |
{ INDEX_op_qemu_st8, { "cb", "L" } }, |
1161 |
{ INDEX_op_qemu_st16, { "L", "L" } }, |
1162 |
{ INDEX_op_qemu_st32, { "L", "L" } }, |
1163 |
{ INDEX_op_qemu_st64, { "L", "L", "L" } }, |
1164 |
#else
|
1165 |
{ INDEX_op_qemu_ld8u, { "r", "L", "L" } }, |
1166 |
{ INDEX_op_qemu_ld8s, { "r", "L", "L" } }, |
1167 |
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } }, |
1168 |
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } }, |
1169 |
{ INDEX_op_qemu_ld32u, { "r", "L", "L" } }, |
1170 |
{ INDEX_op_qemu_ld64, { "r", "r", "L", "L" } }, |
1171 |
|
1172 |
{ INDEX_op_qemu_st8, { "cb", "L", "L" } }, |
1173 |
{ INDEX_op_qemu_st16, { "L", "L", "L" } }, |
1174 |
{ INDEX_op_qemu_st32, { "L", "L", "L" } }, |
1175 |
{ INDEX_op_qemu_st64, { "L", "L", "L", "L" } }, |
1176 |
#endif
|
1177 |
{ -1 },
|
1178 |
}; |
1179 |
|
1180 |
static int tcg_target_callee_save_regs[] = { |
1181 |
/* TCG_REG_EBP, */ /* currently used for the global env, so no |
1182 |
need to save */
|
1183 |
TCG_REG_EBX, |
1184 |
TCG_REG_ESI, |
1185 |
TCG_REG_EDI, |
1186 |
}; |
1187 |
|
1188 |
static inline void tcg_out_push(TCGContext *s, int reg) |
1189 |
{ |
1190 |
tcg_out_opc(s, 0x50 + reg);
|
1191 |
} |
1192 |
|
1193 |
static inline void tcg_out_pop(TCGContext *s, int reg) |
1194 |
{ |
1195 |
tcg_out_opc(s, 0x58 + reg);
|
1196 |
} |
1197 |
|
1198 |
/* Generate global QEMU prologue and epilogue code */
|
1199 |
void tcg_target_qemu_prologue(TCGContext *s)
|
1200 |
{ |
1201 |
int i, frame_size, push_size, stack_addend;
|
1202 |
|
1203 |
/* TB prologue */
|
1204 |
/* save all callee saved registers */
|
1205 |
for(i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { |
1206 |
tcg_out_push(s, tcg_target_callee_save_regs[i]); |
1207 |
} |
1208 |
/* reserve some stack space */
|
1209 |
push_size = 4 + ARRAY_SIZE(tcg_target_callee_save_regs) * 4; |
1210 |
frame_size = push_size + TCG_STATIC_CALL_ARGS_SIZE; |
1211 |
frame_size = (frame_size + TCG_TARGET_STACK_ALIGN - 1) &
|
1212 |
~(TCG_TARGET_STACK_ALIGN - 1);
|
1213 |
stack_addend = frame_size - push_size; |
1214 |
tcg_out_addi(s, TCG_REG_ESP, -stack_addend); |
1215 |
|
1216 |
tcg_out_modrm(s, 0xff, 4, TCG_REG_EAX); /* jmp *%eax */ |
1217 |
|
1218 |
/* TB epilogue */
|
1219 |
tb_ret_addr = s->code_ptr; |
1220 |
tcg_out_addi(s, TCG_REG_ESP, stack_addend); |
1221 |
for(i = ARRAY_SIZE(tcg_target_callee_save_regs) - 1; i >= 0; i--) { |
1222 |
tcg_out_pop(s, tcg_target_callee_save_regs[i]); |
1223 |
} |
1224 |
tcg_out8(s, 0xc3); /* ret */ |
1225 |
} |
1226 |
|
1227 |
void tcg_target_init(TCGContext *s)
|
1228 |
{ |
1229 |
/* fail safe */
|
1230 |
if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) |
1231 |
tcg_abort(); |
1232 |
|
1233 |
tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); |
1234 |
tcg_regset_set32(tcg_target_call_clobber_regs, 0,
|
1235 |
(1 << TCG_REG_EAX) |
|
1236 |
(1 << TCG_REG_EDX) |
|
1237 |
(1 << TCG_REG_ECX));
|
1238 |
|
1239 |
tcg_regset_clear(s->reserved_regs); |
1240 |
tcg_regset_set_reg(s->reserved_regs, TCG_REG_ESP); |
1241 |
|
1242 |
tcg_add_target_add_op_defs(x86_op_defs); |
1243 |
} |