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Name Size
Makefile.objs 319 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 31.8 kB
cpu.h 32.5 kB
cpu64.c 3.2 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper.c 132.1 kB
helper.h 17.3 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 1.9 kB
kvm-stub.c 437 Bytes
kvm.c 24.5 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.8 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 3.8 kB
translate.c 366 kB
translate.h 1.1 kB

Latest revisions

# Date Author Comment
d8ba780b 12/17/2013 09:42 pm Peter Crosthwaite

target-arm: Define and use ARM_FEATURE_CBAR

Some processors (notably A9 within Highbank) define and use the
CP15 configuration base address (CBAR). This is vendor specific
so its best implemented as a CPU property (otherwise we would need
vendor specific child classes for every ARM implementation)....
07a5b0d2 12/17/2013 09:42 pm Peter Crosthwaite

target-arm/cpu: Convert reset CBAR to a property

The reset value of the CP15 CBAR is a vendor (machine) configurable
property. If ARM_FEATURE_CBAR is set, add it as a property at
post_init time.

Signed-off-by: Peter Crosthwaite <>...
3671cd87 12/17/2013 09:42 pm Peter Crosthwaite

target-arm/helper.c: Allow cp15.c15 dummy override

The cp15.c15 space is implementation defined. Currently there is a
dummy placeholder register RAZing it. Allow overriding of this RAZ
so implementations of specific registers can take precedence.

Signed-off-by: Peter Crosthwaite <>...
9d935509 12/17/2013 09:42 pm Ard Biesheuvel

target-arm: add support for v8 AES instructions

This adds support for the AESE/AESD/AESMC/AESIMC instructions that
are available on some v8 implementations of Aarch32.

Signed-off-by: Ard Biesheuvel <>
Message-id: ...
6a57f3eb 12/10/2013 03:28 pm Will Newton

target-arm: Move call to disas_vfp_insn out of disas_coproc_insn.

Floating point is an extension to the instruction set rather than
a coprocessor, so call it directly from the ARM and Thumb decode
functions.

Signed-off-by: Will Newton <>...
04731fb5 12/10/2013 03:28 pm Will Newton

target-arm: Implement ARMv8 VSEL instruction.

This adds support for the VSEL floating point selection instruction
which was added in ARMv8.

Signed-off-by: Will Newton <>
Reviewed-by: Peter Maydell <>
Message-id: ...
40cfacdd 12/10/2013 03:28 pm Will Newton

target-arm: Implement ARMv8 FP VMAXNM and VMINNM instructions.

This adds support for the ARMv8 floating point VMAXNM and VMINNM
instructions.

Signed-off-by: Will Newton <>
Reviewed-by: Peter Maydell <>
Message-id: ...
505935fc 12/10/2013 03:28 pm Will Newton

target-arm: Implement ARMv8 SIMD VMAXNM and VMINNM instructions.

This adds support for the ARMv8 Advanced SIMD VMAXNM and VMINNM
instructions.

Signed-off-by: Will Newton <>
Message-id: ...
09f78135 12/10/2013 03:28 pm Richard Henderson

target-arm: Use new qemu_ld/st opcodes

Retain the existing gen_aa32_* inlines, to aid compilation for A64.

Cc: Peter Maydell <>
Signed-off-by: Richard Henderson <>
Message-id: ...
74f1c6dd 12/10/2013 03:28 pm Sergey Fedorov

target-arm: fix TTBCR write masking

Current implementation is not accurate according to ARMv7-AR reference
manual. See "B4.1.153 TTBCR, Translation Table Base Control Register,
VMSA | TTBCR format when using the Long-descriptor translation table
format". When LPAE feature is supported, EAE, bit31 selects...

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