root / target-ppc / helper.c @ 07ad1b93
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/*
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* PPC emulation helpers for qemu.
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*
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* Copyright (c) 2003 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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extern FILE *logfile;
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void cpu_loop_exit(void) |
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{ |
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longjmp(env->jmp_env, 1);
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} |
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/* shortcuts to generate exceptions */
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void raise_exception_err (int exception_index, int error_code) |
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{ |
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env->exception_index = exception_index; |
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env->error_code = error_code; |
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cpu_loop_exit(); |
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} |
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void raise_exception (int exception_index) |
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{ |
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env->exception_index = exception_index; |
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env->error_code = 0;
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cpu_loop_exit(); |
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} |
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/* Helpers for "fat" micro operations */
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uint32_t do_load_cr (void)
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{ |
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return (env->crf[0] << 28) | |
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(env->crf[1] << 24) | |
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(env->crf[2] << 20) | |
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(env->crf[3] << 16) | |
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(env->crf[4] << 12) | |
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(env->crf[5] << 8) | |
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(env->crf[6] << 4) | |
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(env->crf[7] << 0); |
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} |
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void do_store_cr (uint32_t crn, uint32_t value)
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{ |
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int i, sh;
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for (i = 0, sh = 7; i < 8; i++, sh --) { |
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if (crn & (1 << sh)) |
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env->crf[i] = (value >> (sh * 4)) & 0xF; |
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} |
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} |
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uint32_t do_load_xer (void)
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{ |
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return (xer_so << XER_SO) |
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(xer_ov << XER_OV) | |
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(xer_ca << XER_CA) | |
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(xer_bc << XER_BC); |
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} |
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void do_store_xer (uint32_t value)
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{ |
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xer_so = (value >> XER_SO) & 0x01;
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xer_ov = (value >> XER_OV) & 0x01;
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xer_ca = (value >> XER_CA) & 0x01;
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xer_bc = (value >> XER_BC) & 0x1f;
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} |
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uint32_t do_load_msr (void)
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{ |
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return (msr_pow << MSR_POW) |
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(msr_ile << MSR_ILE) | |
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(msr_ee << MSR_EE) | |
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(msr_pr << MSR_PR) | |
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(msr_fp << MSR_FP) | |
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(msr_me << MSR_ME) | |
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(msr_fe0 << MSR_FE0) | |
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(msr_se << MSR_SE) | |
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(msr_be << MSR_BE) | |
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(msr_fe1 << MSR_FE1) | |
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(msr_ip << MSR_IP) | |
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(msr_ir << MSR_IR) | |
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(msr_dr << MSR_DR) | |
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(msr_ri << MSR_RI) | |
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(msr_le << MSR_LE); |
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} |
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void do_store_msr (uint32_t msr_value)
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{ |
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msr_pow = (msr_value >> MSR_POW) & 0x03;
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msr_ile = (msr_value >> MSR_ILE) & 0x01;
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msr_ee = (msr_value >> MSR_EE) & 0x01;
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msr_pr = (msr_value >> MSR_PR) & 0x01;
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msr_fp = (msr_value >> MSR_FP) & 0x01;
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msr_me = (msr_value >> MSR_ME) & 0x01;
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msr_fe0 = (msr_value >> MSR_FE0) & 0x01;
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msr_se = (msr_value >> MSR_SE) & 0x01;
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msr_be = (msr_value >> MSR_BE) & 0x01;
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msr_fe1 = (msr_value >> MSR_FE1) & 0x01;
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msr_ip = (msr_value >> MSR_IP) & 0x01;
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msr_ir = (msr_value >> MSR_IR) & 0x01;
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msr_dr = (msr_value >> MSR_DR) & 0x01;
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msr_ri = (msr_value >> MSR_RI) & 0x01;
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msr_le = (msr_value >> MSR_LE) & 0x01;
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} |
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/* The 32 MSB of the target fpr are undefined. They'll be zero... */
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uint32_t do_load_fpscr (void)
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{ |
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return (fpscr_fx << FPSCR_FX) |
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(fpscr_fex << FPSCR_FEX) | |
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(fpscr_vx << FPSCR_VX) | |
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(fpscr_ox << FPSCR_OX) | |
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(fpscr_ux << FPSCR_UX) | |
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(fpscr_zx << FPSCR_ZX) | |
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(fpscr_xx << FPSCR_XX) | |
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(fpscr_vsxnan << FPSCR_VXSNAN) | |
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(fpscr_vxisi << FPSCR_VXISI) | |
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(fpscr_vxidi << FPSCR_VXIDI) | |
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(fpscr_vxzdz << FPSCR_VXZDZ) | |
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(fpscr_vximz << FPSCR_VXIMZ) | |
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(fpscr_fr << FPSCR_FR) | |
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(fpscr_fi << FPSCR_FI) | |
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(fpscr_fprf << FPSCR_FPRF) | |
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(fpscr_vxsoft << FPSCR_VXSOFT) | |
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(fpscr_vxsqrt << FPSCR_VXSQRT) | |
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(fpscr_oe << FPSCR_OE) | |
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(fpscr_ue << FPSCR_UE) | |
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(fpscr_ze << FPSCR_ZE) | |
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(fpscr_xe << FPSCR_XE) | |
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(fpscr_ni << FPSCR_NI) | |
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(fpscr_rn << FPSCR_RN); |
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} |
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/* We keep only 32 bits of input... */
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/* For now, this is COMPLETELY BUGGY ! */
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void do_store_fpscr (uint8_t mask, uint32_t fp)
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{ |
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int i;
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for (i = 0; i < 7; i++) { |
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if ((mask & (1 << i)) == 0) |
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fp &= ~(0xf << (4 * i)); |
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} |
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if ((mask & 80) != 0) |
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fpscr_fx = (fp >> FPSCR_FX) & 0x01;
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fpscr_fex = (fp >> FPSCR_FEX) & 0x01;
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fpscr_vx = (fp >> FPSCR_VX) & 0x01;
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fpscr_ox = (fp >> FPSCR_OX) & 0x01;
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fpscr_ux = (fp >> FPSCR_UX) & 0x01;
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fpscr_zx = (fp >> FPSCR_ZX) & 0x01;
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fpscr_xx = (fp >> FPSCR_XX) & 0x01;
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fpscr_vsxnan = (fp >> FPSCR_VXSNAN) & 0x01;
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fpscr_vxisi = (fp >> FPSCR_VXISI) & 0x01;
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fpscr_vxidi = (fp >> FPSCR_VXIDI) & 0x01;
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fpscr_vxzdz = (fp >> FPSCR_VXZDZ) & 0x01;
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fpscr_vximz = (fp >> FPSCR_VXIMZ) & 0x01;
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fpscr_fr = (fp >> FPSCR_FR) & 0x01;
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fpscr_fi = (fp >> FPSCR_FI) & 0x01;
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fpscr_fprf = (fp >> FPSCR_FPRF) & 0x1F;
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fpscr_vxsoft = (fp >> FPSCR_VXSOFT) & 0x01;
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fpscr_vxsqrt = (fp >> FPSCR_VXSQRT) & 0x01;
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fpscr_oe = (fp >> FPSCR_OE) & 0x01;
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fpscr_ue = (fp >> FPSCR_UE) & 0x01;
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fpscr_ze = (fp >> FPSCR_ZE) & 0x01;
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fpscr_xe = (fp >> FPSCR_XE) & 0x01;
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fpscr_ni = (fp >> FPSCR_NI) & 0x01;
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fpscr_rn = (fp >> FPSCR_RN) & 0x03;
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} |
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int32_t do_sraw(int32_t value, uint32_t shift) |
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{ |
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int32_t ret; |
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xer_ca = 0;
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if (shift & 0x20) { |
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ret = (-1) * ((uint32_t)value >> 31); |
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if (ret < 0) |
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xer_ca = 1;
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} else {
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ret = value >> (shift & 0x1f);
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if (ret < 0 && (value & ((1 << shift) - 1)) != 0) |
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xer_ca = 1;
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} |
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return ret;
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} |
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void do_lmw (int reg, uint32_t src) |
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{ |
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for (; reg <= 31; reg++, src += 4) |
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ugpr(reg) = ld32(src); |
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} |
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void do_stmw (int reg, uint32_t dest) |
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{ |
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for (; reg <= 31; reg++, dest += 4) |
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st32(dest, ugpr(reg)); |
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} |
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void do_lsw (uint32_t reg, int count, uint32_t src) |
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{ |
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uint32_t tmp; |
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int sh;
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for (; count > 3; count -= 4, src += 4) { |
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if (reg == 32) |
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reg = 0;
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ugpr(reg++) = ld32(src); |
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} |
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if (count > 0) { |
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for (sh = 24, tmp = 0; count > 0; count--, src++, sh -= 8) { |
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if (reg == 32) |
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reg = 0;
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tmp |= ld8(src) << sh; |
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if (sh == 0) { |
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sh = 32;
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ugpr(reg++) = tmp; |
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tmp = 0;
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} |
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} |
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ugpr(reg) = tmp; |
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} |
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} |
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void do_stsw (uint32_t reg, int count, uint32_t dest) |
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{ |
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int sh;
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for (; count > 3; count -= 4, dest += 4) { |
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if (reg == 32) |
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reg = 0;
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st32(dest, ugpr(reg++)); |
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} |
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if (count > 0) { |
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for (sh = 24; count > 0; count--, dest++, sh -= 8) { |
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if (reg == 32) |
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reg = 0;
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st8(dest, (ugpr(reg) >> sh) & 0xFF);
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if (sh == 0) { |
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sh = 32;
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reg++; |
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} |
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} |
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} |
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} |