root / target-sparc / exec.h @ 0828b448
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1 | 7a3f1944 | bellard | #ifndef EXEC_SPARC_H
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2 | 7a3f1944 | bellard | #define EXEC_SPARC_H 1 |
3 | 3475187d | bellard | #include "config.h" |
4 | 8294eba1 | ths | #include "dyngen-exec.h" |
5 | 7a3f1944 | bellard | |
6 | 7a3f1944 | bellard | register struct CPUSPARCState *env asm(AREG0); |
7 | 01d6a890 | ths | |
8 | af7bf89b | bellard | #ifdef TARGET_SPARC64
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9 | af7bf89b | bellard | #define T0 (env->t0)
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10 | af7bf89b | bellard | #define T2 (env->t2)
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11 | 3475187d | bellard | #define REGWPTR env->regwptr
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12 | af7bf89b | bellard | #else
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13 | 7a3f1944 | bellard | register uint32_t T0 asm(AREG1); |
14 | 3475187d | bellard | |
15 | 3475187d | bellard | #undef REG_REGWPTR // Broken |
16 | 3475187d | bellard | #ifdef REG_REGWPTR
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17 | 01d6a890 | ths | #if defined(__sparc__)
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18 | 01d6a890 | ths | register uint32_t *REGWPTR asm(AREG4); |
19 | 01d6a890 | ths | #else
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20 | 3475187d | bellard | register uint32_t *REGWPTR asm(AREG3); |
21 | 01d6a890 | ths | #endif
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22 | 3475187d | bellard | #define reg_REGWPTR
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23 | 3475187d | bellard | |
24 | 3475187d | bellard | #ifdef AREG4
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25 | 3475187d | bellard | register uint32_t T2 asm(AREG4); |
26 | 3475187d | bellard | #define reg_T2
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27 | 3475187d | bellard | #else
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28 | 3475187d | bellard | #define T2 (env->t2)
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29 | 3475187d | bellard | #endif
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30 | 3475187d | bellard | |
31 | 3475187d | bellard | #else
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32 | 3475187d | bellard | #define REGWPTR env->regwptr
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33 | 7a3f1944 | bellard | register uint32_t T2 asm(AREG3); |
34 | 01d6a890 | ths | #endif
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35 | 3475187d | bellard | #define reg_T2
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36 | 3475187d | bellard | #endif
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37 | 3475187d | bellard | |
38 | e8af50a3 | bellard | #define FT0 (env->ft0)
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39 | e8af50a3 | bellard | #define FT1 (env->ft1)
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40 | e8af50a3 | bellard | #define DT0 (env->dt0)
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41 | e8af50a3 | bellard | #define DT1 (env->dt1)
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42 | 1f587329 | blueswir1 | #if defined(CONFIG_USER_ONLY)
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43 | 1f587329 | blueswir1 | #define QT0 (env->qt0)
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44 | 1f587329 | blueswir1 | #define QT1 (env->qt1)
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45 | 1f587329 | blueswir1 | #endif
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46 | 7a3f1944 | bellard | |
47 | 7a3f1944 | bellard | #include "cpu.h" |
48 | 7a3f1944 | bellard | #include "exec-all.h" |
49 | 7a3f1944 | bellard | |
50 | 7a3f1944 | bellard | void cpu_lock(void); |
51 | 7a3f1944 | bellard | void cpu_unlock(void); |
52 | 7a3f1944 | bellard | void cpu_loop_exit(void); |
53 | e8af50a3 | bellard | void set_cwp(int new_cwp); |
54 | 878d3096 | bellard | void do_interrupt(int intno); |
55 | af7bf89b | bellard | void memcpy32(target_ulong *dst, const target_ulong *src); |
56 | ee5bbe38 | bellard | target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev);
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57 | ee5bbe38 | bellard | void dump_mmu(CPUState *env);
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58 | e8af50a3 | bellard | |
59 | 0d1a29f9 | bellard | static inline void env_to_regs(void) |
60 | 0d1a29f9 | bellard | { |
61 | aea3ce4c | bellard | #if defined(reg_REGWPTR)
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62 | aea3ce4c | bellard | REGWPTR = env->regbase + (env->cwp * 16);
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63 | aea3ce4c | bellard | env->regwptr = REGWPTR; |
64 | aea3ce4c | bellard | #endif
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65 | 0d1a29f9 | bellard | } |
66 | 0d1a29f9 | bellard | |
67 | 0d1a29f9 | bellard | static inline void regs_to_env(void) |
68 | 0d1a29f9 | bellard | { |
69 | 0d1a29f9 | bellard | } |
70 | 0d1a29f9 | bellard | |
71 | 9d893301 | bellard | int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
72 | 6ebbf390 | j_mayer | int mmu_idx, int is_softmmu); |
73 | 9d893301 | bellard | |
74 | bfed01fc | ths | static inline int cpu_halted(CPUState *env) { |
75 | bfed01fc | ths | if (!env->halted)
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76 | bfed01fc | ths | return 0; |
77 | bfed01fc | ths | if ((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->psret != 0)) { |
78 | bfed01fc | ths | env->halted = 0;
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79 | bfed01fc | ths | return 0; |
80 | bfed01fc | ths | } |
81 | bfed01fc | ths | return EXCP_HALTED;
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82 | bfed01fc | ths | } |
83 | bfed01fc | ths | |
84 | 7a3f1944 | bellard | #endif |