root / target-arm / machine.c @ 0834c9ea
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1 | 8dd3dca3 | aurel32 | #include "hw/hw.h" |
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2 | 8dd3dca3 | aurel32 | #include "hw/boards.h" |
3 | 8dd3dca3 | aurel32 | |
4 | 8dd3dca3 | aurel32 | void cpu_save(QEMUFile *f, void *opaque) |
5 | 8dd3dca3 | aurel32 | { |
6 | 8dd3dca3 | aurel32 | int i;
|
7 | 8dd3dca3 | aurel32 | CPUARMState *env = (CPUARMState *)opaque; |
8 | 8dd3dca3 | aurel32 | |
9 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
10 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->regs[i]); |
11 | 8dd3dca3 | aurel32 | } |
12 | 8dd3dca3 | aurel32 | qemu_put_be32(f, cpsr_read(env)); |
13 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->spsr); |
14 | 8dd3dca3 | aurel32 | for (i = 0; i < 6; i++) { |
15 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_spsr[i]); |
16 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_r13[i]); |
17 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->banked_r14[i]); |
18 | 8dd3dca3 | aurel32 | } |
19 | 8dd3dca3 | aurel32 | for (i = 0; i < 5; i++) { |
20 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->usr_regs[i]); |
21 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->fiq_regs[i]); |
22 | 8dd3dca3 | aurel32 | } |
23 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c0_cpuid); |
24 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->cp15.c0_cssel); |
25 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_sys); |
26 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_coproc); |
27 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c1_xscaleauxcr); |
28 | 2be27624 | Rob Herring | qemu_put_be32(f, env->cp15.c1_scr); |
29 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_base0); |
30 | 891a2fe7 | Peter Maydell | qemu_put_be32(f, env->cp15.c2_base0_hi); |
31 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_base1); |
32 | 891a2fe7 | Peter Maydell | qemu_put_be32(f, env->cp15.c2_base1_hi); |
33 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->cp15.c2_control); |
34 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_mask); |
35 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->cp15.c2_base_mask); |
36 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_data); |
37 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c2_insn); |
38 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c3); |
39 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c5_insn); |
40 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c5_data); |
41 | 8dd3dca3 | aurel32 | for (i = 0; i < 8; i++) { |
42 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_region[i]); |
43 | 8dd3dca3 | aurel32 | } |
44 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_insn); |
45 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c6_data); |
46 | f8bf8606 | Adam Lackorzynski | qemu_put_be32(f, env->cp15.c7_par); |
47 | 891a2fe7 | Peter Maydell | qemu_put_be32(f, env->cp15.c7_par_hi); |
48 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c9_insn); |
49 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c9_data); |
50 | 74594c9d | Peter Maydell | qemu_put_be32(f, env->cp15.c9_pmcr); |
51 | 74594c9d | Peter Maydell | qemu_put_be32(f, env->cp15.c9_pmcnten); |
52 | 74594c9d | Peter Maydell | qemu_put_be32(f, env->cp15.c9_pmovsr); |
53 | 74594c9d | Peter Maydell | qemu_put_be32(f, env->cp15.c9_pmxevtyper); |
54 | 74594c9d | Peter Maydell | qemu_put_be32(f, env->cp15.c9_pmuserenr); |
55 | 74594c9d | Peter Maydell | qemu_put_be32(f, env->cp15.c9_pminten); |
56 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_fcse); |
57 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_context); |
58 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls1); |
59 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls2); |
60 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c13_tls3); |
61 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->cp15.c15_cpar); |
62 | 7da362d0 | Mark Langsdorf | qemu_put_be32(f, env->cp15.c15_power_control); |
63 | 7da362d0 | Mark Langsdorf | qemu_put_be32(f, env->cp15.c15_diagnostic); |
64 | 7da362d0 | Mark Langsdorf | qemu_put_be32(f, env->cp15.c15_power_diagnostic); |
65 | 8dd3dca3 | aurel32 | |
66 | 918f5dca | Peter Maydell | qemu_put_be64(f, env->features); |
67 | 8dd3dca3 | aurel32 | |
68 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP)) {
|
69 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
70 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
71 | 8dd3dca3 | aurel32 | u.d = env->vfp.regs[i]; |
72 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.upper); |
73 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.lower); |
74 | 8dd3dca3 | aurel32 | } |
75 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
76 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.xregs[i]); |
77 | 8dd3dca3 | aurel32 | } |
78 | 8dd3dca3 | aurel32 | |
79 | 8dd3dca3 | aurel32 | /* TODO: Should use proper FPSCR access functions. */
|
80 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.vec_len); |
81 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->vfp.vec_stride); |
82 | 8dd3dca3 | aurel32 | |
83 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP3)) {
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84 | 8dd3dca3 | aurel32 | for (i = 16; i < 32; i++) { |
85 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
86 | 8dd3dca3 | aurel32 | u.d = env->vfp.regs[i]; |
87 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.upper); |
88 | 8dd3dca3 | aurel32 | qemu_put_be32(f, u.l.lower); |
89 | 8dd3dca3 | aurel32 | } |
90 | 8dd3dca3 | aurel32 | } |
91 | 8dd3dca3 | aurel32 | } |
92 | 8dd3dca3 | aurel32 | |
93 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
94 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
95 | 8dd3dca3 | aurel32 | qemu_put_be64(f, env->iwmmxt.regs[i]); |
96 | 8dd3dca3 | aurel32 | } |
97 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
98 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->iwmmxt.cregs[i]); |
99 | 8dd3dca3 | aurel32 | } |
100 | 8dd3dca3 | aurel32 | } |
101 | 8dd3dca3 | aurel32 | |
102 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_M)) {
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103 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.other_sp); |
104 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.vecbase); |
105 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.basepri); |
106 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.control); |
107 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.current_sp); |
108 | 8dd3dca3 | aurel32 | qemu_put_be32(f, env->v7m.exception); |
109 | 8dd3dca3 | aurel32 | } |
110 | ffe47d33 | Paul Brook | |
111 | ffe47d33 | Paul Brook | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
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112 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->teecr); |
113 | ffe47d33 | Paul Brook | qemu_put_be32(f, env->teehbr); |
114 | ffe47d33 | Paul Brook | } |
115 | 8dd3dca3 | aurel32 | } |
116 | 8dd3dca3 | aurel32 | |
117 | 8dd3dca3 | aurel32 | int cpu_load(QEMUFile *f, void *opaque, int version_id) |
118 | 8dd3dca3 | aurel32 | { |
119 | 8dd3dca3 | aurel32 | CPUARMState *env = (CPUARMState *)opaque; |
120 | 8dd3dca3 | aurel32 | int i;
|
121 | ffe47d33 | Paul Brook | uint32_t val; |
122 | 8dd3dca3 | aurel32 | |
123 | b3c7724c | pbrook | if (version_id != CPU_SAVE_VERSION)
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124 | 8dd3dca3 | aurel32 | return -EINVAL;
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125 | 8dd3dca3 | aurel32 | |
126 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
127 | 8dd3dca3 | aurel32 | env->regs[i] = qemu_get_be32(f); |
128 | 8dd3dca3 | aurel32 | } |
129 | ffe47d33 | Paul Brook | val = qemu_get_be32(f); |
130 | ffe47d33 | Paul Brook | /* Avoid mode switch when restoring CPSR. */
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131 | ffe47d33 | Paul Brook | env->uncached_cpsr = val & CPSR_M; |
132 | ffe47d33 | Paul Brook | cpsr_write(env, val, 0xffffffff);
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133 | 8dd3dca3 | aurel32 | env->spsr = qemu_get_be32(f); |
134 | 8dd3dca3 | aurel32 | for (i = 0; i < 6; i++) { |
135 | 8dd3dca3 | aurel32 | env->banked_spsr[i] = qemu_get_be32(f); |
136 | 8dd3dca3 | aurel32 | env->banked_r13[i] = qemu_get_be32(f); |
137 | 8dd3dca3 | aurel32 | env->banked_r14[i] = qemu_get_be32(f); |
138 | 8dd3dca3 | aurel32 | } |
139 | 8dd3dca3 | aurel32 | for (i = 0; i < 5; i++) { |
140 | 8dd3dca3 | aurel32 | env->usr_regs[i] = qemu_get_be32(f); |
141 | 8dd3dca3 | aurel32 | env->fiq_regs[i] = qemu_get_be32(f); |
142 | 8dd3dca3 | aurel32 | } |
143 | 8dd3dca3 | aurel32 | env->cp15.c0_cpuid = qemu_get_be32(f); |
144 | ffe47d33 | Paul Brook | env->cp15.c0_cssel = qemu_get_be32(f); |
145 | 8dd3dca3 | aurel32 | env->cp15.c1_sys = qemu_get_be32(f); |
146 | 8dd3dca3 | aurel32 | env->cp15.c1_coproc = qemu_get_be32(f); |
147 | 8dd3dca3 | aurel32 | env->cp15.c1_xscaleauxcr = qemu_get_be32(f); |
148 | 2be27624 | Rob Herring | env->cp15.c1_scr = qemu_get_be32(f); |
149 | 8dd3dca3 | aurel32 | env->cp15.c2_base0 = qemu_get_be32(f); |
150 | 891a2fe7 | Peter Maydell | env->cp15.c2_base0_hi = qemu_get_be32(f); |
151 | 8dd3dca3 | aurel32 | env->cp15.c2_base1 = qemu_get_be32(f); |
152 | 891a2fe7 | Peter Maydell | env->cp15.c2_base1_hi = qemu_get_be32(f); |
153 | ffe47d33 | Paul Brook | env->cp15.c2_control = qemu_get_be32(f); |
154 | 8dd3dca3 | aurel32 | env->cp15.c2_mask = qemu_get_be32(f); |
155 | ffe47d33 | Paul Brook | env->cp15.c2_base_mask = qemu_get_be32(f); |
156 | 8dd3dca3 | aurel32 | env->cp15.c2_data = qemu_get_be32(f); |
157 | 8dd3dca3 | aurel32 | env->cp15.c2_insn = qemu_get_be32(f); |
158 | 8dd3dca3 | aurel32 | env->cp15.c3 = qemu_get_be32(f); |
159 | 8dd3dca3 | aurel32 | env->cp15.c5_insn = qemu_get_be32(f); |
160 | 8dd3dca3 | aurel32 | env->cp15.c5_data = qemu_get_be32(f); |
161 | 8dd3dca3 | aurel32 | for (i = 0; i < 8; i++) { |
162 | 8dd3dca3 | aurel32 | env->cp15.c6_region[i] = qemu_get_be32(f); |
163 | 8dd3dca3 | aurel32 | } |
164 | 8dd3dca3 | aurel32 | env->cp15.c6_insn = qemu_get_be32(f); |
165 | 8dd3dca3 | aurel32 | env->cp15.c6_data = qemu_get_be32(f); |
166 | f8bf8606 | Adam Lackorzynski | env->cp15.c7_par = qemu_get_be32(f); |
167 | 891a2fe7 | Peter Maydell | env->cp15.c7_par_hi = qemu_get_be32(f); |
168 | 8dd3dca3 | aurel32 | env->cp15.c9_insn = qemu_get_be32(f); |
169 | 8dd3dca3 | aurel32 | env->cp15.c9_data = qemu_get_be32(f); |
170 | 74594c9d | Peter Maydell | env->cp15.c9_pmcr = qemu_get_be32(f); |
171 | 74594c9d | Peter Maydell | env->cp15.c9_pmcnten = qemu_get_be32(f); |
172 | 74594c9d | Peter Maydell | env->cp15.c9_pmovsr = qemu_get_be32(f); |
173 | 74594c9d | Peter Maydell | env->cp15.c9_pmxevtyper = qemu_get_be32(f); |
174 | 74594c9d | Peter Maydell | env->cp15.c9_pmuserenr = qemu_get_be32(f); |
175 | 74594c9d | Peter Maydell | env->cp15.c9_pminten = qemu_get_be32(f); |
176 | 8dd3dca3 | aurel32 | env->cp15.c13_fcse = qemu_get_be32(f); |
177 | 8dd3dca3 | aurel32 | env->cp15.c13_context = qemu_get_be32(f); |
178 | 8dd3dca3 | aurel32 | env->cp15.c13_tls1 = qemu_get_be32(f); |
179 | 8dd3dca3 | aurel32 | env->cp15.c13_tls2 = qemu_get_be32(f); |
180 | 8dd3dca3 | aurel32 | env->cp15.c13_tls3 = qemu_get_be32(f); |
181 | 8dd3dca3 | aurel32 | env->cp15.c15_cpar = qemu_get_be32(f); |
182 | 7da362d0 | Mark Langsdorf | env->cp15.c15_power_control = qemu_get_be32(f); |
183 | 7da362d0 | Mark Langsdorf | env->cp15.c15_diagnostic = qemu_get_be32(f); |
184 | 7da362d0 | Mark Langsdorf | env->cp15.c15_power_diagnostic = qemu_get_be32(f); |
185 | 8dd3dca3 | aurel32 | |
186 | 918f5dca | Peter Maydell | env->features = qemu_get_be64(f); |
187 | 8dd3dca3 | aurel32 | |
188 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP)) {
|
189 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
190 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
191 | 8dd3dca3 | aurel32 | u.l.upper = qemu_get_be32(f); |
192 | 8dd3dca3 | aurel32 | u.l.lower = qemu_get_be32(f); |
193 | 8dd3dca3 | aurel32 | env->vfp.regs[i] = u.d; |
194 | 8dd3dca3 | aurel32 | } |
195 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
196 | 8dd3dca3 | aurel32 | env->vfp.xregs[i] = qemu_get_be32(f); |
197 | 8dd3dca3 | aurel32 | } |
198 | 8dd3dca3 | aurel32 | |
199 | 8dd3dca3 | aurel32 | /* TODO: Should use proper FPSCR access functions. */
|
200 | 8dd3dca3 | aurel32 | env->vfp.vec_len = qemu_get_be32(f); |
201 | 8dd3dca3 | aurel32 | env->vfp.vec_stride = qemu_get_be32(f); |
202 | 8dd3dca3 | aurel32 | |
203 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
204 | 15180256 | Dmitry Koshelev | for (i = 16; i < 32; i++) { |
205 | 8dd3dca3 | aurel32 | CPU_DoubleU u; |
206 | 8dd3dca3 | aurel32 | u.l.upper = qemu_get_be32(f); |
207 | 8dd3dca3 | aurel32 | u.l.lower = qemu_get_be32(f); |
208 | 8dd3dca3 | aurel32 | env->vfp.regs[i] = u.d; |
209 | 8dd3dca3 | aurel32 | } |
210 | 8dd3dca3 | aurel32 | } |
211 | 8dd3dca3 | aurel32 | } |
212 | 8dd3dca3 | aurel32 | |
213 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
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214 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
215 | 8dd3dca3 | aurel32 | env->iwmmxt.regs[i] = qemu_get_be64(f); |
216 | 8dd3dca3 | aurel32 | } |
217 | 8dd3dca3 | aurel32 | for (i = 0; i < 16; i++) { |
218 | 8dd3dca3 | aurel32 | env->iwmmxt.cregs[i] = qemu_get_be32(f); |
219 | 8dd3dca3 | aurel32 | } |
220 | 8dd3dca3 | aurel32 | } |
221 | 8dd3dca3 | aurel32 | |
222 | 8dd3dca3 | aurel32 | if (arm_feature(env, ARM_FEATURE_M)) {
|
223 | 8dd3dca3 | aurel32 | env->v7m.other_sp = qemu_get_be32(f); |
224 | 8dd3dca3 | aurel32 | env->v7m.vecbase = qemu_get_be32(f); |
225 | 8dd3dca3 | aurel32 | env->v7m.basepri = qemu_get_be32(f); |
226 | 8dd3dca3 | aurel32 | env->v7m.control = qemu_get_be32(f); |
227 | 8dd3dca3 | aurel32 | env->v7m.current_sp = qemu_get_be32(f); |
228 | 8dd3dca3 | aurel32 | env->v7m.exception = qemu_get_be32(f); |
229 | 8dd3dca3 | aurel32 | } |
230 | 8dd3dca3 | aurel32 | |
231 | ffe47d33 | Paul Brook | if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
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232 | ffe47d33 | Paul Brook | env->teecr = qemu_get_be32(f); |
233 | ffe47d33 | Paul Brook | env->teehbr = qemu_get_be32(f); |
234 | ffe47d33 | Paul Brook | } |
235 | ffe47d33 | Paul Brook | |
236 | 8dd3dca3 | aurel32 | return 0; |
237 | 8dd3dca3 | aurel32 | } |