root / target-arm / machine.c @ 0834c9ea
History | View | Annotate | Download (7.8 kB)
| 1 |
#include "hw/hw.h" |
|---|---|
| 2 |
#include "hw/boards.h" |
| 3 |
|
| 4 |
void cpu_save(QEMUFile *f, void *opaque) |
| 5 |
{
|
| 6 |
int i;
|
| 7 |
CPUARMState *env = (CPUARMState *)opaque; |
| 8 |
|
| 9 |
for (i = 0; i < 16; i++) { |
| 10 |
qemu_put_be32(f, env->regs[i]); |
| 11 |
} |
| 12 |
qemu_put_be32(f, cpsr_read(env)); |
| 13 |
qemu_put_be32(f, env->spsr); |
| 14 |
for (i = 0; i < 6; i++) { |
| 15 |
qemu_put_be32(f, env->banked_spsr[i]); |
| 16 |
qemu_put_be32(f, env->banked_r13[i]); |
| 17 |
qemu_put_be32(f, env->banked_r14[i]); |
| 18 |
} |
| 19 |
for (i = 0; i < 5; i++) { |
| 20 |
qemu_put_be32(f, env->usr_regs[i]); |
| 21 |
qemu_put_be32(f, env->fiq_regs[i]); |
| 22 |
} |
| 23 |
qemu_put_be32(f, env->cp15.c0_cpuid); |
| 24 |
qemu_put_be32(f, env->cp15.c0_cssel); |
| 25 |
qemu_put_be32(f, env->cp15.c1_sys); |
| 26 |
qemu_put_be32(f, env->cp15.c1_coproc); |
| 27 |
qemu_put_be32(f, env->cp15.c1_xscaleauxcr); |
| 28 |
qemu_put_be32(f, env->cp15.c1_scr); |
| 29 |
qemu_put_be32(f, env->cp15.c2_base0); |
| 30 |
qemu_put_be32(f, env->cp15.c2_base0_hi); |
| 31 |
qemu_put_be32(f, env->cp15.c2_base1); |
| 32 |
qemu_put_be32(f, env->cp15.c2_base1_hi); |
| 33 |
qemu_put_be32(f, env->cp15.c2_control); |
| 34 |
qemu_put_be32(f, env->cp15.c2_mask); |
| 35 |
qemu_put_be32(f, env->cp15.c2_base_mask); |
| 36 |
qemu_put_be32(f, env->cp15.c2_data); |
| 37 |
qemu_put_be32(f, env->cp15.c2_insn); |
| 38 |
qemu_put_be32(f, env->cp15.c3); |
| 39 |
qemu_put_be32(f, env->cp15.c5_insn); |
| 40 |
qemu_put_be32(f, env->cp15.c5_data); |
| 41 |
for (i = 0; i < 8; i++) { |
| 42 |
qemu_put_be32(f, env->cp15.c6_region[i]); |
| 43 |
} |
| 44 |
qemu_put_be32(f, env->cp15.c6_insn); |
| 45 |
qemu_put_be32(f, env->cp15.c6_data); |
| 46 |
qemu_put_be32(f, env->cp15.c7_par); |
| 47 |
qemu_put_be32(f, env->cp15.c7_par_hi); |
| 48 |
qemu_put_be32(f, env->cp15.c9_insn); |
| 49 |
qemu_put_be32(f, env->cp15.c9_data); |
| 50 |
qemu_put_be32(f, env->cp15.c9_pmcr); |
| 51 |
qemu_put_be32(f, env->cp15.c9_pmcnten); |
| 52 |
qemu_put_be32(f, env->cp15.c9_pmovsr); |
| 53 |
qemu_put_be32(f, env->cp15.c9_pmxevtyper); |
| 54 |
qemu_put_be32(f, env->cp15.c9_pmuserenr); |
| 55 |
qemu_put_be32(f, env->cp15.c9_pminten); |
| 56 |
qemu_put_be32(f, env->cp15.c13_fcse); |
| 57 |
qemu_put_be32(f, env->cp15.c13_context); |
| 58 |
qemu_put_be32(f, env->cp15.c13_tls1); |
| 59 |
qemu_put_be32(f, env->cp15.c13_tls2); |
| 60 |
qemu_put_be32(f, env->cp15.c13_tls3); |
| 61 |
qemu_put_be32(f, env->cp15.c15_cpar); |
| 62 |
qemu_put_be32(f, env->cp15.c15_power_control); |
| 63 |
qemu_put_be32(f, env->cp15.c15_diagnostic); |
| 64 |
qemu_put_be32(f, env->cp15.c15_power_diagnostic); |
| 65 |
|
| 66 |
qemu_put_be64(f, env->features); |
| 67 |
|
| 68 |
if (arm_feature(env, ARM_FEATURE_VFP)) {
|
| 69 |
for (i = 0; i < 16; i++) { |
| 70 |
CPU_DoubleU u; |
| 71 |
u.d = env->vfp.regs[i]; |
| 72 |
qemu_put_be32(f, u.l.upper); |
| 73 |
qemu_put_be32(f, u.l.lower); |
| 74 |
} |
| 75 |
for (i = 0; i < 16; i++) { |
| 76 |
qemu_put_be32(f, env->vfp.xregs[i]); |
| 77 |
} |
| 78 |
|
| 79 |
/* TODO: Should use proper FPSCR access functions. */
|
| 80 |
qemu_put_be32(f, env->vfp.vec_len); |
| 81 |
qemu_put_be32(f, env->vfp.vec_stride); |
| 82 |
|
| 83 |
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
| 84 |
for (i = 16; i < 32; i++) { |
| 85 |
CPU_DoubleU u; |
| 86 |
u.d = env->vfp.regs[i]; |
| 87 |
qemu_put_be32(f, u.l.upper); |
| 88 |
qemu_put_be32(f, u.l.lower); |
| 89 |
} |
| 90 |
} |
| 91 |
} |
| 92 |
|
| 93 |
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
| 94 |
for (i = 0; i < 16; i++) { |
| 95 |
qemu_put_be64(f, env->iwmmxt.regs[i]); |
| 96 |
} |
| 97 |
for (i = 0; i < 16; i++) { |
| 98 |
qemu_put_be32(f, env->iwmmxt.cregs[i]); |
| 99 |
} |
| 100 |
} |
| 101 |
|
| 102 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
| 103 |
qemu_put_be32(f, env->v7m.other_sp); |
| 104 |
qemu_put_be32(f, env->v7m.vecbase); |
| 105 |
qemu_put_be32(f, env->v7m.basepri); |
| 106 |
qemu_put_be32(f, env->v7m.control); |
| 107 |
qemu_put_be32(f, env->v7m.current_sp); |
| 108 |
qemu_put_be32(f, env->v7m.exception); |
| 109 |
} |
| 110 |
|
| 111 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
| 112 |
qemu_put_be32(f, env->teecr); |
| 113 |
qemu_put_be32(f, env->teehbr); |
| 114 |
} |
| 115 |
} |
| 116 |
|
| 117 |
int cpu_load(QEMUFile *f, void *opaque, int version_id) |
| 118 |
{
|
| 119 |
CPUARMState *env = (CPUARMState *)opaque; |
| 120 |
int i;
|
| 121 |
uint32_t val; |
| 122 |
|
| 123 |
if (version_id != CPU_SAVE_VERSION)
|
| 124 |
return -EINVAL;
|
| 125 |
|
| 126 |
for (i = 0; i < 16; i++) { |
| 127 |
env->regs[i] = qemu_get_be32(f); |
| 128 |
} |
| 129 |
val = qemu_get_be32(f); |
| 130 |
/* Avoid mode switch when restoring CPSR. */
|
| 131 |
env->uncached_cpsr = val & CPSR_M; |
| 132 |
cpsr_write(env, val, 0xffffffff);
|
| 133 |
env->spsr = qemu_get_be32(f); |
| 134 |
for (i = 0; i < 6; i++) { |
| 135 |
env->banked_spsr[i] = qemu_get_be32(f); |
| 136 |
env->banked_r13[i] = qemu_get_be32(f); |
| 137 |
env->banked_r14[i] = qemu_get_be32(f); |
| 138 |
} |
| 139 |
for (i = 0; i < 5; i++) { |
| 140 |
env->usr_regs[i] = qemu_get_be32(f); |
| 141 |
env->fiq_regs[i] = qemu_get_be32(f); |
| 142 |
} |
| 143 |
env->cp15.c0_cpuid = qemu_get_be32(f); |
| 144 |
env->cp15.c0_cssel = qemu_get_be32(f); |
| 145 |
env->cp15.c1_sys = qemu_get_be32(f); |
| 146 |
env->cp15.c1_coproc = qemu_get_be32(f); |
| 147 |
env->cp15.c1_xscaleauxcr = qemu_get_be32(f); |
| 148 |
env->cp15.c1_scr = qemu_get_be32(f); |
| 149 |
env->cp15.c2_base0 = qemu_get_be32(f); |
| 150 |
env->cp15.c2_base0_hi = qemu_get_be32(f); |
| 151 |
env->cp15.c2_base1 = qemu_get_be32(f); |
| 152 |
env->cp15.c2_base1_hi = qemu_get_be32(f); |
| 153 |
env->cp15.c2_control = qemu_get_be32(f); |
| 154 |
env->cp15.c2_mask = qemu_get_be32(f); |
| 155 |
env->cp15.c2_base_mask = qemu_get_be32(f); |
| 156 |
env->cp15.c2_data = qemu_get_be32(f); |
| 157 |
env->cp15.c2_insn = qemu_get_be32(f); |
| 158 |
env->cp15.c3 = qemu_get_be32(f); |
| 159 |
env->cp15.c5_insn = qemu_get_be32(f); |
| 160 |
env->cp15.c5_data = qemu_get_be32(f); |
| 161 |
for (i = 0; i < 8; i++) { |
| 162 |
env->cp15.c6_region[i] = qemu_get_be32(f); |
| 163 |
} |
| 164 |
env->cp15.c6_insn = qemu_get_be32(f); |
| 165 |
env->cp15.c6_data = qemu_get_be32(f); |
| 166 |
env->cp15.c7_par = qemu_get_be32(f); |
| 167 |
env->cp15.c7_par_hi = qemu_get_be32(f); |
| 168 |
env->cp15.c9_insn = qemu_get_be32(f); |
| 169 |
env->cp15.c9_data = qemu_get_be32(f); |
| 170 |
env->cp15.c9_pmcr = qemu_get_be32(f); |
| 171 |
env->cp15.c9_pmcnten = qemu_get_be32(f); |
| 172 |
env->cp15.c9_pmovsr = qemu_get_be32(f); |
| 173 |
env->cp15.c9_pmxevtyper = qemu_get_be32(f); |
| 174 |
env->cp15.c9_pmuserenr = qemu_get_be32(f); |
| 175 |
env->cp15.c9_pminten = qemu_get_be32(f); |
| 176 |
env->cp15.c13_fcse = qemu_get_be32(f); |
| 177 |
env->cp15.c13_context = qemu_get_be32(f); |
| 178 |
env->cp15.c13_tls1 = qemu_get_be32(f); |
| 179 |
env->cp15.c13_tls2 = qemu_get_be32(f); |
| 180 |
env->cp15.c13_tls3 = qemu_get_be32(f); |
| 181 |
env->cp15.c15_cpar = qemu_get_be32(f); |
| 182 |
env->cp15.c15_power_control = qemu_get_be32(f); |
| 183 |
env->cp15.c15_diagnostic = qemu_get_be32(f); |
| 184 |
env->cp15.c15_power_diagnostic = qemu_get_be32(f); |
| 185 |
|
| 186 |
env->features = qemu_get_be64(f); |
| 187 |
|
| 188 |
if (arm_feature(env, ARM_FEATURE_VFP)) {
|
| 189 |
for (i = 0; i < 16; i++) { |
| 190 |
CPU_DoubleU u; |
| 191 |
u.l.upper = qemu_get_be32(f); |
| 192 |
u.l.lower = qemu_get_be32(f); |
| 193 |
env->vfp.regs[i] = u.d; |
| 194 |
} |
| 195 |
for (i = 0; i < 16; i++) { |
| 196 |
env->vfp.xregs[i] = qemu_get_be32(f); |
| 197 |
} |
| 198 |
|
| 199 |
/* TODO: Should use proper FPSCR access functions. */
|
| 200 |
env->vfp.vec_len = qemu_get_be32(f); |
| 201 |
env->vfp.vec_stride = qemu_get_be32(f); |
| 202 |
|
| 203 |
if (arm_feature(env, ARM_FEATURE_VFP3)) {
|
| 204 |
for (i = 16; i < 32; i++) { |
| 205 |
CPU_DoubleU u; |
| 206 |
u.l.upper = qemu_get_be32(f); |
| 207 |
u.l.lower = qemu_get_be32(f); |
| 208 |
env->vfp.regs[i] = u.d; |
| 209 |
} |
| 210 |
} |
| 211 |
} |
| 212 |
|
| 213 |
if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
|
| 214 |
for (i = 0; i < 16; i++) { |
| 215 |
env->iwmmxt.regs[i] = qemu_get_be64(f); |
| 216 |
} |
| 217 |
for (i = 0; i < 16; i++) { |
| 218 |
env->iwmmxt.cregs[i] = qemu_get_be32(f); |
| 219 |
} |
| 220 |
} |
| 221 |
|
| 222 |
if (arm_feature(env, ARM_FEATURE_M)) {
|
| 223 |
env->v7m.other_sp = qemu_get_be32(f); |
| 224 |
env->v7m.vecbase = qemu_get_be32(f); |
| 225 |
env->v7m.basepri = qemu_get_be32(f); |
| 226 |
env->v7m.control = qemu_get_be32(f); |
| 227 |
env->v7m.current_sp = qemu_get_be32(f); |
| 228 |
env->v7m.exception = qemu_get_be32(f); |
| 229 |
} |
| 230 |
|
| 231 |
if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
|
| 232 |
env->teecr = qemu_get_be32(f); |
| 233 |
env->teehbr = qemu_get_be32(f); |
| 234 |
} |
| 235 |
|
| 236 |
return 0; |
| 237 |
} |