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Name Size
Makefile.objs 96 Bytes
TODO 1.9 kB
cpu-qom.h 1.8 kB
cpu.c 1.8 kB
cpu.h 23.4 kB
helper.c 22.1 kB
helper.h 13.6 kB
lmi_helper.c 14 kB
machine.c 10.6 kB
mips-defs.h 2.1 kB
op_helper.c 111.1 kB
translate.c 381 kB
translate_init.c 22.3 kB

Latest revisions

# Date Author Comment
bd277fa1 09/19/2012 10:40 pm Richard Henderson

target-mips: Implement Loongson Multimedia Instructions

Implements all of the COP2 instructions except for the S<cond>
family of comparisons. The documentation is unclear for those.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
e1050a76 09/19/2012 10:40 pm Richard Henderson

target-mips: Set opn in gen_ldst_multiple.

Used by MIPS_DEBUG, when enabled.

Signed-off-by: Richard Henderson <>
Acked-by: Aurelien Jarno <>
Signed-off-by: Aurelien Jarno <>
9fa77488 09/19/2012 10:40 pm Richard Henderson

target-mips: Fix MIPS_DEBUG.

The macro uses the DisasContext. Pass it around as needed.

Signed-off-by: Richard Henderson <>
Acked-by: Aurelien Jarno <>
Signed-off-by: Aurelien Jarno <>
fb7729e2 09/19/2012 10:40 pm Richard Henderson

target-mips: Always evaluate debugging macro arguments

this will prevent some of the compilation errors with debugging
enabled from creeping back in.

Signed-off-by: Richard Henderson <>
Signed-off-by: Aurelien Jarno <>
895c2d04 09/15/2012 08:51 pm Blue Swirl

target-mips: switch to AREG0 free mode

Add an explicit CPUState parameter instead of relying on AREG0
and switch to AREG0 free mode.

Signed-off-by: Blue Swirl <>
Acked-by: Aurelien Jarno <>
03e6e501 09/08/2012 02:37 am Maciej W. Rozycki

MIPS/user: Fix reset CPU state initialization

This change updates the CPU reset sequence to use a common piece of code
that figures out CPU state flags, fixing the problem with MIPS_HFLAG_COP1X
not being set where applicable that causes floating-point MADD family...
36c6711b 08/27/2012 11:18 pm Eric Johnson

target-mips: allow microMIPS SWP and SDP to have RD equal to BASE

The microMIPS SWP and SDP instructions do not modify GPRs. So their
behavior is well defined when RD equals BASE. The MIPS Architecture
Verification Programs (AVPs) check that they work as expected. This...
2e15497c 08/27/2012 11:17 pm Eric Johnson

target-mips: add privilege level check to several Cop0 instructions

The MIPS Architecture Verification Programs (AVPs) check privileged
instructions for the required privilege level. These changes are needed
to pass the AVP suite.

Signed-off-by: Eric Johnson <>...
b3167288 08/27/2012 01:17 pm Richard Henderson

mips-linux-user: Always support rdhwr.

The kernel will emulate this instruction if it's not supported
natively. This insn is used for TLS, among other things, and
so is required by modern glibc.

Signed-off-by: Richard Henderson <>
Cc: Riku Voipio <>...
05168674 08/27/2012 01:17 pm Richard Henderson

target-mips: Streamline indexed cp1 memory addressing.

We've already eliminated both base and index being zero.

Signed-off-by: Aurelien Jarno <>

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