Archipelago » qemu

/*

 *  i386 CPUID helper functions

 *

 *  Copyright (c) 2003 Fabrice Bellard

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include "cpu.h"

#include "kvm.h"

#include "qemu-option.h"

#include "qemu-config.h"

#include "qapi/qapi-visit-core.h"

#include "hyperv.h"

/* feature flags taken from "Intel Processor Identification and the CPUID

 * Instruction" and AMD's "CPUID Specification".  In cases of disagreement

 * between feature naming conventions, aliases may be added.

 */

static const char *feature_name[] = {

    "fpu", "vme", "de", "pse",

    "tsc", "msr", "pae", "mce",

    "cx8", "apic", NULL, "sep",

    "mtrr", "pge", "mca", "cmov",

    "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,

    NULL, "ds" /* Intel dts */, "acpi", "mmx",

    "fxsr", "sse", "sse2", "ss",

    "ht" /* Intel htt */, "tm", "ia64", "pbe",

};

static const char *ext_feature_name[] = {

    "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",

    "ds_cpl", "vmx", "smx", "est",

    "tm2", "ssse3", "cid", NULL,

    "fma", "cx16", "xtpr", "pdcm",

    NULL, NULL, "dca", "sse4.1|sse4_1",

    "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",

    "tsc-deadline", "aes", "xsave", "osxsave",

    "avx", NULL, NULL, "hypervisor",

};

static const char *ext2_feature_name[] = {

    "fpu", "vme", "de", "pse",

    "tsc", "msr", "pae", "mce",

    "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",

    "mtrr", "pge", "mca", "cmov",

    "pat", "pse36", NULL, NULL /* Linux mp */,

    "nx|xd", NULL, "mmxext", "mmx",

    "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",

    NULL, "lm|i64", "3dnowext", "3dnow",

};

static const char *ext3_feature_name[] = {

    "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,

    "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",

    "3dnowprefetch", "osvw", "ibs", "xop",

    "skinit", "wdt", NULL, NULL,

    "fma4", NULL, "cvt16", "nodeid_msr",

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

};

static const char *kvm_feature_name[] = {

    "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL,

    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,

};

static const char *svm_feature_name[] = {

    "npt", "lbrv", "svm_lock", "nrip_save",

    "tsc_scale", "vmcb_clean",  "flushbyasid", "decodeassists",

    NULL, NULL, "pause_filter", NULL,

    "pfthreshold", NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

    NULL, NULL, NULL, NULL,

};

/* collects per-function cpuid data

 */

typedef struct model_features_t {

    uint32_t *guest_feat;

    uint32_t *host_feat;

    uint32_t check_feat;

    const char **flag_names;

    uint32_t cpuid;

    } model_features_t;

int check_cpuid = 0;

int enforce_cpuid = 0;

void host_cpuid(uint32_t function, uint32_t count,

                uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)

{

#if defined(CONFIG_KVM)

    uint32_t vec[4];

#ifdef __x86_64__

    asm volatile("cpuid"

                 : "=a"(vec[0]), "=b"(vec[1]),

                   "=c"(vec[2]), "=d"(vec[3])

                 : "0"(function), "c"(count) : "cc");

#else

    asm volatile("pusha \n\t"

                 "cpuid \n\t"

                 "mov %%eax, 0(%2) \n\t"

                 "mov %%ebx, 4(%2) \n\t"

                 "mov %%ecx, 8(%2) \n\t"

                 "mov %%edx, 12(%2) \n\t"

                 "popa"

                 : : "a"(function), "c"(count), "S"(vec)

                 : "memory", "cc");

#endif

    if (eax)

        *eax = vec[0];

    if (ebx)

        *ebx = vec[1];

    if (ecx)

        *ecx = vec[2];

    if (edx)

        *edx = vec[3];

#endif

}

#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))

/* general substring compare of *[s1..e1) and *[s2..e2).  sx is start of

 * a substring.  ex if !NULL points to the first char after a substring,

 * otherwise the string is assumed to sized by a terminating nul.

 * Return lexical ordering of *s1:*s2.

 */

static int sstrcmp(const char *s1, const char *e1, const char *s2,

    const char *e2)

{

    for (;;) {

        if (!*s1 || !*s2 || *s1 != *s2)

            return (*s1 - *s2);

        ++s1, ++s2;

        if (s1 == e1 && s2 == e2)

            return (0);

        else if (s1 == e1)

            return (*s2);

        else if (s2 == e2)

            return (*s1);

    }

}

/* compare *[s..e) to *altstr.  *altstr may be a simple string or multiple

 * '|' delimited (possibly empty) strings in which case search for a match

 * within the alternatives proceeds left to right.  Return 0 for success,

 * non-zero otherwise.

 */

static int altcmp(const char *s, const char *e, const char *altstr)

{

    const char *p, *q;

    for (q = p = altstr; ; ) {

        while (*p && *p != '|')

            ++p;

        if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))

            return (0);

        if (!*p)

            return (1);

        else

            q = ++p;

    }

}

/* search featureset for flag *[s..e), if found set corresponding bit in

 * *pval and return true, otherwise return false

 */

static bool lookup_feature(uint32_t *pval, const char *s, const char *e,

                           const char **featureset)

{

    uint32_t mask;

    const char **ppc;

    bool found = false;

    for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {

        if (*ppc && !altcmp(s, e, *ppc)) {

            *pval |= mask;

            found = true;

        }

    }

    return found;

}

static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,

                                    uint32_t *ext_features,

                                    uint32_t *ext2_features,

                                    uint32_t *ext3_features,

                                    uint32_t *kvm_features,

                                    uint32_t *svm_features)

{

    if (!lookup_feature(features, flagname, NULL, feature_name) &&

        !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&

        !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&

        !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&

        !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&

        !lookup_feature(svm_features, flagname, NULL, svm_feature_name))

            fprintf(stderr, "CPU feature %s not found\n", flagname);

}

typedef struct x86_def_t {

    struct x86_def_t *next;

    const char *name;

    uint32_t level;

    uint32_t vendor1, vendor2, vendor3;

    int family;

    int model;

    int stepping;

    int tsc_khz;

    uint32_t features, ext_features, ext2_features, ext3_features;

    uint32_t kvm_features, svm_features;

    uint32_t xlevel;

    char model_id[48];

    int vendor_override;

    uint32_t flags;

    /* Store the results of Centaur's CPUID instructions */

    uint32_t ext4_features;

    uint32_t xlevel2;

    /* The feature bits on CPUID[EAX=7,ECX=0].EBX */

    uint32_t cpuid_7_0_ebx_features;

} x86_def_t;

#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)

#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \

          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)

#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \

          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \

          CPUID_PSE36 | CPUID_FXSR)

#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)

#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \

          CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \

          CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \

          CPUID_PAE | CPUID_SEP | CPUID_APIC)

#define EXT2_FEATURE_MASK 0x0183F3FF

#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \

          CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \

          CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \

          CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \

          CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)

          /* partly implemented:

          CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)

          CPUID_PSE36 (needed for Solaris) */

          /* missing:

          CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */

#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \

          CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \

          CPUID_EXT_HYPERVISOR)

          /* missing:

          CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,

          CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */

#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \

          CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \

          CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)

          /* missing:

          CPUID_EXT2_PDPE1GB */

#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \

          CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)

#define TCG_SVM_FEATURES 0

/* maintains list of cpu model definitions

 */

static x86_def_t *x86_defs = {NULL};

/* built-in cpu model definitions (deprecated)

 */

static x86_def_t builtin_x86_defs[] = {

    {

        .name = "qemu64",

        .level = 4,

        .vendor1 = CPUID_VENDOR_AMD_1,

        .vendor2 = CPUID_VENDOR_AMD_2,

        .vendor3 = CPUID_VENDOR_AMD_3,

        .family = 6,

        .model = 2,

        .stepping = 3,

        .features = PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36,

        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,

        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |

            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,

        .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |

            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,

        .xlevel = 0x8000000A,

    },

    {

        .name = "phenom",

        .level = 5,

        .vendor1 = CPUID_VENDOR_AMD_1,

        .vendor2 = CPUID_VENDOR_AMD_2,

        .vendor3 = CPUID_VENDOR_AMD_3,

        .family = 16,

        .model = 2,

        .stepping = 3,

        .features = PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36 | CPUID_VME | CPUID_HT,

        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |

            CPUID_EXT_POPCNT,

        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |

            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |

            CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |

            CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,

        /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,

                    CPUID_EXT3_CR8LEG,

                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,

                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS */

        .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |

            CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,

        .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,

        .xlevel = 0x8000001A,

        .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"

    },

    {

        .name = "core2duo",

        .level = 10,

        .family = 6,

        .model = 15,

        .stepping = 11,

        .features = PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |

            CPUID_HT | CPUID_TM | CPUID_PBE,

        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |

            CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |

            CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,

        .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,

        .ext3_features = CPUID_EXT3_LAHF_LM,

        .xlevel = 0x80000008,

        .model_id = "Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz",

    },

    {

        .name = "kvm64",

        .level = 5,

        .vendor1 = CPUID_VENDOR_INTEL_1,

        .vendor2 = CPUID_VENDOR_INTEL_2,

        .vendor3 = CPUID_VENDOR_INTEL_3,

        .family = 15,

        .model = 6,

        .stepping = 1,

        /* Missing: CPUID_VME, CPUID_HT */

        .features = PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |

            CPUID_PSE36,

        /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */

        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,

        /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */

        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |

            CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,

        /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,

                    CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,

                    CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,

                    CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */

        .ext3_features = 0,

        .xlevel = 0x80000008,

        .model_id = "Common KVM processor"

    },

    {

        .name = "qemu32",

        .level = 4,

        .family = 6,

        .model = 3,

        .stepping = 3,

        .features = PPRO_FEATURES,

        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,

        .xlevel = 0x80000004,

    },

    {

        .name = "kvm32",

        .level = 5,

        .family = 15,

        .model = 6,

        .stepping = 1,

        .features = PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,

        .ext_features = CPUID_EXT_SSE3,

        .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,

        .ext3_features = 0,

        .xlevel = 0x80000008,

        .model_id = "Common 32-bit KVM processor"

    },

    {

        .name = "coreduo",

        .level = 10,

        .family = 6,

        .model = 14,

        .stepping = 8,

        .features = PPRO_FEATURES | CPUID_VME |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |

            CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,

        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |

            CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,

        .ext2_features = CPUID_EXT2_NX,

        .xlevel = 0x80000008,

        .model_id = "Genuine Intel(R) CPU           T2600  @ 2.16GHz",

    },

    {

        .name = "486",

        .level = 1,

        .family = 4,

        .model = 0,

        .stepping = 0,

        .features = I486_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "pentium",

        .level = 1,

        .family = 5,

        .model = 4,

        .stepping = 3,

        .features = PENTIUM_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "pentium2",

        .level = 2,

        .family = 6,

        .model = 5,

        .stepping = 2,

        .features = PENTIUM2_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "pentium3",

        .level = 2,

        .family = 6,

        .model = 7,

        .stepping = 3,

        .features = PENTIUM3_FEATURES,

        .xlevel = 0,

    },

    {

        .name = "athlon",

        .level = 2,

        .vendor1 = CPUID_VENDOR_AMD_1,

        .vendor2 = CPUID_VENDOR_AMD_2,

        .vendor3 = CPUID_VENDOR_AMD_3,

        .family = 6,

        .model = 2,

        .stepping = 3,

        .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,

        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,

        .xlevel = 0x80000008,

    },

    {

        .name = "n270",

        /* original is on level 10 */

        .level = 5,

        .family = 6,

        .model = 28,

        .stepping = 2,

        .features = PPRO_FEATURES |

            CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |

            CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,

            /* Some CPUs got no CPUID_SEP */

        .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |

            CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,

        .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,

        .ext3_features = CPUID_EXT3_LAHF_LM,

        .xlevel = 0x8000000A,

        .model_id = "Intel(R) Atom(TM) CPU N270   @ 1.60GHz",

    },

};

static int cpu_x86_fill_model_id(char *str)

{

    uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;

    int i;

    for (i = 0; i < 3; i++) {

        host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);

        memcpy(str + i * 16 +  0, &eax, 4);

        memcpy(str + i * 16 +  4, &ebx, 4);

        memcpy(str + i * 16 +  8, &ecx, 4);

        memcpy(str + i * 16 + 12, &edx, 4);

    }

    return 0;

}

static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)

{

    uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;

    x86_cpu_def->name = "host";

    host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);

    x86_cpu_def->level = eax;

    x86_cpu_def->vendor1 = ebx;

    x86_cpu_def->vendor2 = edx;

    x86_cpu_def->vendor3 = ecx;

    host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);

    x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);

    x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);

    x86_cpu_def->stepping = eax & 0x0F;

    x86_cpu_def->ext_features = ecx;

    x86_cpu_def->features = edx;

    if (kvm_enabled() && x86_cpu_def->level >= 7) {

        x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);

    } else {

        x86_cpu_def->cpuid_7_0_ebx_features = 0;

    }

    host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);

    x86_cpu_def->xlevel = eax;

    host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);

    x86_cpu_def->ext2_features = edx;

    x86_cpu_def->ext3_features = ecx;

    cpu_x86_fill_model_id(x86_cpu_def->model_id);

    x86_cpu_def->vendor_override = 0;

    /* Call Centaur's CPUID instruction. */

    if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&

        x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&

        x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {

        host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);

        if (eax >= 0xC0000001) {

            /* Support VIA max extended level */

            x86_cpu_def->xlevel2 = eax;

            host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);

            x86_cpu_def->ext4_features = edx;

        }

    }

    /*

     * Every SVM feature requires emulation support in KVM - so we can't just

     * read the host features here. KVM might even support SVM features not

     * available on the host hardware. Just set all bits and mask out the

     * unsupported ones later.

     */

    x86_cpu_def->svm_features = -1;

    return 0;

}

static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)

{

    int i;

    for (i = 0; i < 32; ++i)

        if (1 << i & mask) {

            fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"

                " flag '%s' [0x%08x]\n",

                f->cpuid >> 16, f->cpuid & 0xffff,

                f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);

            break;

        }

    return 0;

}

/* best effort attempt to inform user requested cpu flags aren't making

 * their way to the guest.  Note: ft[].check_feat ideally should be

 * specified via a guest_def field to suppress report of extraneous flags.

 */

static int check_features_against_host(x86_def_t *guest_def)

{

    x86_def_t host_def;

    uint32_t mask;

    int rv, i;

    struct model_features_t ft[] = {

        {&guest_def->features, &host_def.features,

            ~0, feature_name, 0x00000000},

        {&guest_def->ext_features, &host_def.ext_features,

            ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},

        {&guest_def->ext2_features, &host_def.ext2_features,

            ~PPRO_FEATURES, ext2_feature_name, 0x80000000},

        {&guest_def->ext3_features, &host_def.ext3_features,

            ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};

    cpu_x86_fill_host(&host_def);

    for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)

        for (mask = 1; mask; mask <<= 1)

            if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&

                !(*ft[i].host_feat & mask)) {

                    unavailable_host_feature(&ft[i], mask);

                    rv = 1;

                }

    return rv;

}

static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,

                                         const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    int64_t value;

    value = (env->cpuid_version >> 8) & 0xf;

    if (value == 0xf) {

        value += (env->cpuid_version >> 20) & 0xff;

    }

    visit_type_int(v, &value, name, errp);

}

static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,

                                         const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    const int64_t min = 0;

    const int64_t max = 0xff + 0xf;

    int64_t value;

    visit_type_int(v, &value, name, errp);

    if (error_is_set(errp)) {

        return;

    }

    if (value < min || value > max) {

        error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",

                  name ? name : "null", value, min, max);

        return;

    }

    env->cpuid_version &= ~0xff00f00;

    if (value > 0x0f) {

        env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);

    } else {

        env->cpuid_version |= value << 8;

    }

}

static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,

                                        const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    int64_t value;

    value = (env->cpuid_version >> 4) & 0xf;

    value |= ((env->cpuid_version >> 16) & 0xf) << 4;

    visit_type_int(v, &value, name, errp);

}

static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,

                                        const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    const int64_t min = 0;

    const int64_t max = 0xff;

    int64_t value;

    visit_type_int(v, &value, name, errp);

    if (error_is_set(errp)) {

        return;

    }

    if (value < min || value > max) {

        error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",

                  name ? name : "null", value, min, max);

        return;

    }

    env->cpuid_version &= ~0xf00f0;

    env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);

}

static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,

                                           void *opaque, const char *name,

                                           Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    int64_t value;

    value = env->cpuid_version & 0xf;

    visit_type_int(v, &value, name, errp);

}

static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,

                                           void *opaque, const char *name,

                                           Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    const int64_t min = 0;

    const int64_t max = 0xf;

    int64_t value;

    visit_type_int(v, &value, name, errp);

    if (error_is_set(errp)) {

        return;

    }

    if (value < min || value > max) {

        error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",

                  name ? name : "null", value, min, max);

        return;

    }

    env->cpuid_version &= ~0xf;

    env->cpuid_version |= value & 0xf;

}

static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,

                                const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);

}

static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,

                                const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);

}

static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,

                                 const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);

}

static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,

                                 const char *name, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);

}

static char *x86_cpuid_get_vendor(Object *obj, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    char *value;

    int i;

    value = (char *)g_malloc(12 + 1);

    for (i = 0; i < 4; i++) {

        value[i    ] = env->cpuid_vendor1 >> (8 * i);

        value[i + 4] = env->cpuid_vendor2 >> (8 * i);

        value[i + 8] = env->cpuid_vendor3 >> (8 * i);

    }

    value[12] = '\0';

    return value;

}

static void x86_cpuid_set_vendor(Object *obj, const char *value,

                                 Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    int i;

    if (strlen(value) != 12) {

        error_set(errp, QERR_PROPERTY_VALUE_BAD, "",

                  "vendor", value);

        return;

    }

    env->cpuid_vendor1 = 0;

    env->cpuid_vendor2 = 0;

    env->cpuid_vendor3 = 0;

    for (i = 0; i < 4; i++) {

        env->cpuid_vendor1 |= ((uint8_t)value[i    ]) << (8 * i);

        env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);

        env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);

    }

    env->cpuid_vendor_override = 1;

}

static char *x86_cpuid_get_model_id(Object *obj, Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    char *value;

    int i;

    value = g_malloc(48 + 1);

    for (i = 0; i < 48; i++) {

        value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));

    }

    value[48] = '\0';

    return value;

}

static void x86_cpuid_set_model_id(Object *obj, const char *model_id,

                                   Error **errp)

{

    X86CPU *cpu = X86_CPU(obj);

    CPUX86State *env = &cpu->env;

    int c, len, i;

    if (model_id == NULL) {

        model_id = "";

    }

    len = strlen(model_id);

    memset(env->cpuid_model, 0, 48);

    for (i = 0; i < 48; i++) {

        if (i >= len) {

            c = '\0';

        } else {