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/*
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* i386 CPUID helper functions
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <string.h> |
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#include <inttypes.h> |
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#include "cpu.h" |
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#include "kvm.h" |
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#include "qemu-option.h" |
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#include "qemu-config.h" |
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#include "qapi/qapi-visit-core.h" |
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#include "hyperv.h" |
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/* feature flags taken from "Intel Processor Identification and the CPUID
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* Instruction" and AMD's "CPUID Specification". In cases of disagreement
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* between feature naming conventions, aliases may be added.
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*/
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static const char *feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8", "apic", NULL, "sep", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */, |
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NULL, "ds" /* Intel dts */, "acpi", "mmx", |
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"fxsr", "sse", "sse2", "ss", |
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"ht" /* Intel htt */, "tm", "ia64", "pbe", |
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}; |
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static const char *ext_feature_name[] = { |
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"pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor", |
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"ds_cpl", "vmx", "smx", "est", |
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"tm2", "ssse3", "cid", NULL, |
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"fma", "cx16", "xtpr", "pdcm", |
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NULL, NULL, "dca", "sse4.1|sse4_1", |
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"sse4.2|sse4_2", "x2apic", "movbe", "popcnt", |
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"tsc-deadline", "aes", "xsave", "osxsave", |
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"avx", NULL, NULL, "hypervisor", |
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}; |
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static const char *ext2_feature_name[] = { |
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"fpu", "vme", "de", "pse", |
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"tsc", "msr", "pae", "mce", |
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"cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", |
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"mtrr", "pge", "mca", "cmov", |
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"pat", "pse36", NULL, NULL /* Linux mp */, |
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"nx|xd", NULL, "mmxext", "mmx", |
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"fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp", |
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NULL, "lm|i64", "3dnowext", "3dnow", |
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}; |
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static const char *ext3_feature_name[] = { |
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"lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, |
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"cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse", |
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"3dnowprefetch", "osvw", "ibs", "xop", |
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"skinit", "wdt", NULL, NULL, |
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"fma4", NULL, "cvt16", "nodeid_msr", |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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}; |
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static const char *kvm_feature_name[] = { |
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"kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, |
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}; |
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static const char *svm_feature_name[] = { |
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"npt", "lbrv", "svm_lock", "nrip_save", |
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"tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists", |
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NULL, NULL, "pause_filter", NULL, |
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"pfthreshold", NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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NULL, NULL, NULL, NULL, |
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}; |
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/* collects per-function cpuid data
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*/
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typedef struct model_features_t { |
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uint32_t *guest_feat; |
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uint32_t *host_feat; |
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uint32_t check_feat; |
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const char **flag_names; |
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uint32_t cpuid; |
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} model_features_t; |
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int check_cpuid = 0; |
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int enforce_cpuid = 0; |
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void host_cpuid(uint32_t function, uint32_t count,
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uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) |
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{ |
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#if defined(CONFIG_KVM)
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uint32_t vec[4];
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#ifdef __x86_64__
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asm volatile("cpuid" |
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: "=a"(vec[0]), "=b"(vec[1]), |
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"=c"(vec[2]), "=d"(vec[3]) |
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: "0"(function), "c"(count) : "cc"); |
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#else
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asm volatile("pusha \n\t" |
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"cpuid \n\t"
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"mov %%eax, 0(%2) \n\t"
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"mov %%ebx, 4(%2) \n\t"
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"mov %%ecx, 8(%2) \n\t"
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"mov %%edx, 12(%2) \n\t"
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"popa"
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: : "a"(function), "c"(count), "S"(vec) |
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: "memory", "cc"); |
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#endif
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if (eax)
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*eax = vec[0];
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if (ebx)
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*ebx = vec[1];
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if (ecx)
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*ecx = vec[2];
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if (edx)
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*edx = vec[3];
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#endif
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} |
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#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c))) |
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/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
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* a substring. ex if !NULL points to the first char after a substring,
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* otherwise the string is assumed to sized by a terminating nul.
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* Return lexical ordering of *s1:*s2.
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*/
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static int sstrcmp(const char *s1, const char *e1, const char *s2, |
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const char *e2) |
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{ |
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for (;;) {
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if (!*s1 || !*s2 || *s1 != *s2)
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return (*s1 - *s2);
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++s1, ++s2; |
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if (s1 == e1 && s2 == e2)
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return (0); |
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else if (s1 == e1) |
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return (*s2);
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else if (s2 == e2) |
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return (*s1);
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} |
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} |
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/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
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* '|' delimited (possibly empty) strings in which case search for a match
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* within the alternatives proceeds left to right. Return 0 for success,
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* non-zero otherwise.
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*/
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static int altcmp(const char *s, const char *e, const char *altstr) |
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{ |
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const char *p, *q; |
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for (q = p = altstr; ; ) {
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while (*p && *p != '|') |
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++p; |
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if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
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return (0); |
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if (!*p)
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return (1); |
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else
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q = ++p; |
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} |
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} |
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/* search featureset for flag *[s..e), if found set corresponding bit in
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* *pval and return true, otherwise return false
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*/
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static bool lookup_feature(uint32_t *pval, const char *s, const char *e, |
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const char **featureset) |
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{ |
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uint32_t mask; |
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const char **ppc; |
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bool found = false; |
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for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) { |
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if (*ppc && !altcmp(s, e, *ppc)) {
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*pval |= mask; |
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found = true;
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} |
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} |
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return found;
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} |
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static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features, |
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uint32_t *ext_features, |
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uint32_t *ext2_features, |
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uint32_t *ext3_features, |
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uint32_t *kvm_features, |
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uint32_t *svm_features) |
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{ |
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if (!lookup_feature(features, flagname, NULL, feature_name) && |
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!lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
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!lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
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!lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
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!lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
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!lookup_feature(svm_features, flagname, NULL, svm_feature_name))
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fprintf(stderr, "CPU feature %s not found\n", flagname);
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} |
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typedef struct x86_def_t { |
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struct x86_def_t *next;
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const char *name; |
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uint32_t level; |
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uint32_t vendor1, vendor2, vendor3; |
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int family;
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int model;
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int stepping;
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int tsc_khz;
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uint32_t features, ext_features, ext2_features, ext3_features; |
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uint32_t kvm_features, svm_features; |
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uint32_t xlevel; |
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char model_id[48]; |
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int vendor_override;
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uint32_t flags; |
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/* Store the results of Centaur's CPUID instructions */
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uint32_t ext4_features; |
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uint32_t xlevel2; |
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/* The feature bits on CPUID[EAX=7,ECX=0].EBX */
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uint32_t cpuid_7_0_ebx_features; |
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} x86_def_t; |
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#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
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#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC) |
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#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
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CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ |
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CPUID_PSE36 | CPUID_FXSR) |
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#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
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#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
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CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \ |
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CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \ |
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CPUID_PAE | CPUID_SEP | CPUID_APIC) |
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#define EXT2_FEATURE_MASK 0x0183F3FF |
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#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
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CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \ |
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CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \ |
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CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \ |
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CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS) |
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/* partly implemented:
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CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
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CPUID_PSE36 (needed for Solaris) */
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/* missing:
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CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
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#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
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CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \ |
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CPUID_EXT_HYPERVISOR) |
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/* missing:
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CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
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CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
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#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
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CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \ |
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT) |
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/* missing:
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CPUID_EXT2_PDPE1GB */
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#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
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CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A) |
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#define TCG_SVM_FEATURES 0 |
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/* maintains list of cpu model definitions
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*/
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static x86_def_t *x86_defs = {NULL}; |
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/* built-in cpu model definitions (deprecated)
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*/
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static x86_def_t builtin_x86_defs[] = {
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{ |
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.name = "qemu64",
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.level = 4,
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 6,
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.model = 2,
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.stepping = 3,
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, |
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
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.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
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.xlevel = 0x8000000A,
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}, |
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{ |
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.name = "phenom",
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.level = 5,
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.vendor1 = CPUID_VENDOR_AMD_1, |
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.vendor2 = CPUID_VENDOR_AMD_2, |
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.vendor3 = CPUID_VENDOR_AMD_3, |
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.family = 16,
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.model = 2,
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.stepping = 3,
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36 | CPUID_VME | CPUID_HT, |
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | |
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CPUID_EXT_POPCNT, |
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
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CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | |
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CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | |
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CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, |
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/* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
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CPUID_EXT3_CR8LEG,
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CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
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CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
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.ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | |
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CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, |
333 |
.svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV, |
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.xlevel = 0x8000001A,
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.model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
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}, |
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{ |
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.name = "core2duo",
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.level = 10,
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.family = 6,
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.model = 15,
|
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.stepping = 11,
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.features = PPRO_FEATURES | |
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CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
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CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS | |
346 |
CPUID_HT | CPUID_TM | CPUID_PBE, |
347 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
348 |
CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST | |
349 |
CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, |
350 |
.ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
351 |
.ext3_features = CPUID_EXT3_LAHF_LM, |
352 |
.xlevel = 0x80000008,
|
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.model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
|
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}, |
355 |
{ |
356 |
.name = "kvm64",
|
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.level = 5,
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.vendor1 = CPUID_VENDOR_INTEL_1, |
359 |
.vendor2 = CPUID_VENDOR_INTEL_2, |
360 |
.vendor3 = CPUID_VENDOR_INTEL_3, |
361 |
.family = 15,
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.model = 6,
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363 |
.stepping = 1,
|
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/* Missing: CPUID_VME, CPUID_HT */
|
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.features = PPRO_FEATURES | |
366 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | |
367 |
CPUID_PSE36, |
368 |
/* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
|
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.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16, |
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/* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
|
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.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | |
372 |
CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, |
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/* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
|
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CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
|
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CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
|
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CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
|
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.ext3_features = 0,
|
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.xlevel = 0x80000008,
|
379 |
.model_id = "Common KVM processor"
|
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}, |
381 |
{ |
382 |
.name = "qemu32",
|
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.level = 4,
|
384 |
.family = 6,
|
385 |
.model = 3,
|
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.stepping = 3,
|
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.features = PPRO_FEATURES, |
388 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, |
389 |
.xlevel = 0x80000004,
|
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}, |
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{ |
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.name = "kvm32",
|
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.level = 5,
|
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.family = 15,
|
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.model = 6,
|
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.stepping = 1,
|
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.features = PPRO_FEATURES | |
398 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, |
399 |
.ext_features = CPUID_EXT_SSE3, |
400 |
.ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK, |
401 |
.ext3_features = 0,
|
402 |
.xlevel = 0x80000008,
|
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.model_id = "Common 32-bit KVM processor"
|
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}, |
405 |
{ |
406 |
.name = "coreduo",
|
407 |
.level = 10,
|
408 |
.family = 6,
|
409 |
.model = 14,
|
410 |
.stepping = 8,
|
411 |
.features = PPRO_FEATURES | CPUID_VME | |
412 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI | |
413 |
CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, |
414 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX | |
415 |
CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, |
416 |
.ext2_features = CPUID_EXT2_NX, |
417 |
.xlevel = 0x80000008,
|
418 |
.model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
|
419 |
}, |
420 |
{ |
421 |
.name = "486",
|
422 |
.level = 1,
|
423 |
.family = 4,
|
424 |
.model = 0,
|
425 |
.stepping = 0,
|
426 |
.features = I486_FEATURES, |
427 |
.xlevel = 0,
|
428 |
}, |
429 |
{ |
430 |
.name = "pentium",
|
431 |
.level = 1,
|
432 |
.family = 5,
|
433 |
.model = 4,
|
434 |
.stepping = 3,
|
435 |
.features = PENTIUM_FEATURES, |
436 |
.xlevel = 0,
|
437 |
}, |
438 |
{ |
439 |
.name = "pentium2",
|
440 |
.level = 2,
|
441 |
.family = 6,
|
442 |
.model = 5,
|
443 |
.stepping = 2,
|
444 |
.features = PENTIUM2_FEATURES, |
445 |
.xlevel = 0,
|
446 |
}, |
447 |
{ |
448 |
.name = "pentium3",
|
449 |
.level = 2,
|
450 |
.family = 6,
|
451 |
.model = 7,
|
452 |
.stepping = 3,
|
453 |
.features = PENTIUM3_FEATURES, |
454 |
.xlevel = 0,
|
455 |
}, |
456 |
{ |
457 |
.name = "athlon",
|
458 |
.level = 2,
|
459 |
.vendor1 = CPUID_VENDOR_AMD_1, |
460 |
.vendor2 = CPUID_VENDOR_AMD_2, |
461 |
.vendor3 = CPUID_VENDOR_AMD_3, |
462 |
.family = 6,
|
463 |
.model = 2,
|
464 |
.stepping = 3,
|
465 |
.features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, |
466 |
.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, |
467 |
.xlevel = 0x80000008,
|
468 |
}, |
469 |
{ |
470 |
.name = "n270",
|
471 |
/* original is on level 10 */
|
472 |
.level = 5,
|
473 |
.family = 6,
|
474 |
.model = 28,
|
475 |
.stepping = 2,
|
476 |
.features = PPRO_FEATURES | |
477 |
CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS | |
478 |
CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, |
479 |
/* Some CPUs got no CPUID_SEP */
|
480 |
.ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | |
481 |
CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR, |
482 |
.ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX, |
483 |
.ext3_features = CPUID_EXT3_LAHF_LM, |
484 |
.xlevel = 0x8000000A,
|
485 |
.model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
|
486 |
}, |
487 |
}; |
488 |
|
489 |
static int cpu_x86_fill_model_id(char *str) |
490 |
{ |
491 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
492 |
int i;
|
493 |
|
494 |
for (i = 0; i < 3; i++) { |
495 |
host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx); |
496 |
memcpy(str + i * 16 + 0, &eax, 4); |
497 |
memcpy(str + i * 16 + 4, &ebx, 4); |
498 |
memcpy(str + i * 16 + 8, &ecx, 4); |
499 |
memcpy(str + i * 16 + 12, &edx, 4); |
500 |
} |
501 |
return 0; |
502 |
} |
503 |
|
504 |
static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) |
505 |
{ |
506 |
uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; |
507 |
|
508 |
x86_cpu_def->name = "host";
|
509 |
host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); |
510 |
x86_cpu_def->level = eax; |
511 |
x86_cpu_def->vendor1 = ebx; |
512 |
x86_cpu_def->vendor2 = edx; |
513 |
x86_cpu_def->vendor3 = ecx; |
514 |
|
515 |
host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx); |
516 |
x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); |
517 |
x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); |
518 |
x86_cpu_def->stepping = eax & 0x0F;
|
519 |
x86_cpu_def->ext_features = ecx; |
520 |
x86_cpu_def->features = edx; |
521 |
|
522 |
if (kvm_enabled() && x86_cpu_def->level >= 7) { |
523 |
x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX); |
524 |
} else {
|
525 |
x86_cpu_def->cpuid_7_0_ebx_features = 0;
|
526 |
} |
527 |
|
528 |
host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx); |
529 |
x86_cpu_def->xlevel = eax; |
530 |
|
531 |
host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx); |
532 |
x86_cpu_def->ext2_features = edx; |
533 |
x86_cpu_def->ext3_features = ecx; |
534 |
cpu_x86_fill_model_id(x86_cpu_def->model_id); |
535 |
x86_cpu_def->vendor_override = 0;
|
536 |
|
537 |
/* Call Centaur's CPUID instruction. */
|
538 |
if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
|
539 |
x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 && |
540 |
x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) { |
541 |
host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); |
542 |
if (eax >= 0xC0000001) { |
543 |
/* Support VIA max extended level */
|
544 |
x86_cpu_def->xlevel2 = eax; |
545 |
host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); |
546 |
x86_cpu_def->ext4_features = edx; |
547 |
} |
548 |
} |
549 |
|
550 |
/*
|
551 |
* Every SVM feature requires emulation support in KVM - so we can't just
|
552 |
* read the host features here. KVM might even support SVM features not
|
553 |
* available on the host hardware. Just set all bits and mask out the
|
554 |
* unsupported ones later.
|
555 |
*/
|
556 |
x86_cpu_def->svm_features = -1;
|
557 |
|
558 |
return 0; |
559 |
} |
560 |
|
561 |
static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) |
562 |
{ |
563 |
int i;
|
564 |
|
565 |
for (i = 0; i < 32; ++i) |
566 |
if (1 << i & mask) { |
567 |
fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
|
568 |
" flag '%s' [0x%08x]\n",
|
569 |
f->cpuid >> 16, f->cpuid & 0xffff, |
570 |
f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
|
571 |
break;
|
572 |
} |
573 |
return 0; |
574 |
} |
575 |
|
576 |
/* best effort attempt to inform user requested cpu flags aren't making
|
577 |
* their way to the guest. Note: ft[].check_feat ideally should be
|
578 |
* specified via a guest_def field to suppress report of extraneous flags.
|
579 |
*/
|
580 |
static int check_features_against_host(x86_def_t *guest_def) |
581 |
{ |
582 |
x86_def_t host_def; |
583 |
uint32_t mask; |
584 |
int rv, i;
|
585 |
struct model_features_t ft[] = {
|
586 |
{&guest_def->features, &host_def.features, |
587 |
~0, feature_name, 0x00000000}, |
588 |
{&guest_def->ext_features, &host_def.ext_features, |
589 |
~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
|
590 |
{&guest_def->ext2_features, &host_def.ext2_features, |
591 |
~PPRO_FEATURES, ext2_feature_name, 0x80000000},
|
592 |
{&guest_def->ext3_features, &host_def.ext3_features, |
593 |
~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
|
594 |
|
595 |
cpu_x86_fill_host(&host_def); |
596 |
for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) |
597 |
for (mask = 1; mask; mask <<= 1) |
598 |
if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
|
599 |
!(*ft[i].host_feat & mask)) { |
600 |
unavailable_host_feature(&ft[i], mask); |
601 |
rv = 1;
|
602 |
} |
603 |
return rv;
|
604 |
} |
605 |
|
606 |
static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque, |
607 |
const char *name, Error **errp) |
608 |
{ |
609 |
X86CPU *cpu = X86_CPU(obj); |
610 |
CPUX86State *env = &cpu->env; |
611 |
int64_t value; |
612 |
|
613 |
value = (env->cpuid_version >> 8) & 0xf; |
614 |
if (value == 0xf) { |
615 |
value += (env->cpuid_version >> 20) & 0xff; |
616 |
} |
617 |
visit_type_int(v, &value, name, errp); |
618 |
} |
619 |
|
620 |
static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque, |
621 |
const char *name, Error **errp) |
622 |
{ |
623 |
X86CPU *cpu = X86_CPU(obj); |
624 |
CPUX86State *env = &cpu->env; |
625 |
const int64_t min = 0; |
626 |
const int64_t max = 0xff + 0xf; |
627 |
int64_t value; |
628 |
|
629 |
visit_type_int(v, &value, name, errp); |
630 |
if (error_is_set(errp)) {
|
631 |
return;
|
632 |
} |
633 |
if (value < min || value > max) {
|
634 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
635 |
name ? name : "null", value, min, max);
|
636 |
return;
|
637 |
} |
638 |
|
639 |
env->cpuid_version &= ~0xff00f00;
|
640 |
if (value > 0x0f) { |
641 |
env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20); |
642 |
} else {
|
643 |
env->cpuid_version |= value << 8;
|
644 |
} |
645 |
} |
646 |
|
647 |
static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque, |
648 |
const char *name, Error **errp) |
649 |
{ |
650 |
X86CPU *cpu = X86_CPU(obj); |
651 |
CPUX86State *env = &cpu->env; |
652 |
int64_t value; |
653 |
|
654 |
value = (env->cpuid_version >> 4) & 0xf; |
655 |
value |= ((env->cpuid_version >> 16) & 0xf) << 4; |
656 |
visit_type_int(v, &value, name, errp); |
657 |
} |
658 |
|
659 |
static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque, |
660 |
const char *name, Error **errp) |
661 |
{ |
662 |
X86CPU *cpu = X86_CPU(obj); |
663 |
CPUX86State *env = &cpu->env; |
664 |
const int64_t min = 0; |
665 |
const int64_t max = 0xff; |
666 |
int64_t value; |
667 |
|
668 |
visit_type_int(v, &value, name, errp); |
669 |
if (error_is_set(errp)) {
|
670 |
return;
|
671 |
} |
672 |
if (value < min || value > max) {
|
673 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
674 |
name ? name : "null", value, min, max);
|
675 |
return;
|
676 |
} |
677 |
|
678 |
env->cpuid_version &= ~0xf00f0;
|
679 |
env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16); |
680 |
} |
681 |
|
682 |
static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v, |
683 |
void *opaque, const char *name, |
684 |
Error **errp) |
685 |
{ |
686 |
X86CPU *cpu = X86_CPU(obj); |
687 |
CPUX86State *env = &cpu->env; |
688 |
int64_t value; |
689 |
|
690 |
value = env->cpuid_version & 0xf;
|
691 |
visit_type_int(v, &value, name, errp); |
692 |
} |
693 |
|
694 |
static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v, |
695 |
void *opaque, const char *name, |
696 |
Error **errp) |
697 |
{ |
698 |
X86CPU *cpu = X86_CPU(obj); |
699 |
CPUX86State *env = &cpu->env; |
700 |
const int64_t min = 0; |
701 |
const int64_t max = 0xf; |
702 |
int64_t value; |
703 |
|
704 |
visit_type_int(v, &value, name, errp); |
705 |
if (error_is_set(errp)) {
|
706 |
return;
|
707 |
} |
708 |
if (value < min || value > max) {
|
709 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
710 |
name ? name : "null", value, min, max);
|
711 |
return;
|
712 |
} |
713 |
|
714 |
env->cpuid_version &= ~0xf;
|
715 |
env->cpuid_version |= value & 0xf;
|
716 |
} |
717 |
|
718 |
static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque, |
719 |
const char *name, Error **errp) |
720 |
{ |
721 |
X86CPU *cpu = X86_CPU(obj); |
722 |
|
723 |
visit_type_uint32(v, &cpu->env.cpuid_level, name, errp); |
724 |
} |
725 |
|
726 |
static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque, |
727 |
const char *name, Error **errp) |
728 |
{ |
729 |
X86CPU *cpu = X86_CPU(obj); |
730 |
|
731 |
visit_type_uint32(v, &cpu->env.cpuid_level, name, errp); |
732 |
} |
733 |
|
734 |
static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque, |
735 |
const char *name, Error **errp) |
736 |
{ |
737 |
X86CPU *cpu = X86_CPU(obj); |
738 |
|
739 |
visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp); |
740 |
} |
741 |
|
742 |
static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque, |
743 |
const char *name, Error **errp) |
744 |
{ |
745 |
X86CPU *cpu = X86_CPU(obj); |
746 |
|
747 |
visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp); |
748 |
} |
749 |
|
750 |
static char *x86_cpuid_get_vendor(Object *obj, Error **errp) |
751 |
{ |
752 |
X86CPU *cpu = X86_CPU(obj); |
753 |
CPUX86State *env = &cpu->env; |
754 |
char *value;
|
755 |
int i;
|
756 |
|
757 |
value = (char *)g_malloc(12 + 1); |
758 |
for (i = 0; i < 4; i++) { |
759 |
value[i ] = env->cpuid_vendor1 >> (8 * i);
|
760 |
value[i + 4] = env->cpuid_vendor2 >> (8 * i); |
761 |
value[i + 8] = env->cpuid_vendor3 >> (8 * i); |
762 |
} |
763 |
value[12] = '\0'; |
764 |
return value;
|
765 |
} |
766 |
|
767 |
static void x86_cpuid_set_vendor(Object *obj, const char *value, |
768 |
Error **errp) |
769 |
{ |
770 |
X86CPU *cpu = X86_CPU(obj); |
771 |
CPUX86State *env = &cpu->env; |
772 |
int i;
|
773 |
|
774 |
if (strlen(value) != 12) { |
775 |
error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
|
776 |
"vendor", value);
|
777 |
return;
|
778 |
} |
779 |
|
780 |
env->cpuid_vendor1 = 0;
|
781 |
env->cpuid_vendor2 = 0;
|
782 |
env->cpuid_vendor3 = 0;
|
783 |
for (i = 0; i < 4; i++) { |
784 |
env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
|
785 |
env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i); |
786 |
env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i); |
787 |
} |
788 |
env->cpuid_vendor_override = 1;
|
789 |
} |
790 |
|
791 |
static char *x86_cpuid_get_model_id(Object *obj, Error **errp) |
792 |
{ |
793 |
X86CPU *cpu = X86_CPU(obj); |
794 |
CPUX86State *env = &cpu->env; |
795 |
char *value;
|
796 |
int i;
|
797 |
|
798 |
value = g_malloc(48 + 1); |
799 |
for (i = 0; i < 48; i++) { |
800 |
value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3)); |
801 |
} |
802 |
value[48] = '\0'; |
803 |
return value;
|
804 |
} |
805 |
|
806 |
static void x86_cpuid_set_model_id(Object *obj, const char *model_id, |
807 |
Error **errp) |
808 |
{ |
809 |
X86CPU *cpu = X86_CPU(obj); |
810 |
CPUX86State *env = &cpu->env; |
811 |
int c, len, i;
|
812 |
|
813 |
if (model_id == NULL) { |
814 |
model_id = "";
|
815 |
} |
816 |
len = strlen(model_id); |
817 |
memset(env->cpuid_model, 0, 48); |
818 |
for (i = 0; i < 48; i++) { |
819 |
if (i >= len) {
|
820 |
c = '\0';
|
821 |
} else {
|
822 |
c = (uint8_t)model_id[i]; |
823 |
} |
824 |
env->cpuid_model[i >> 2] |= c << (8 * (i & 3)); |
825 |
} |
826 |
} |
827 |
|
828 |
static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque, |
829 |
const char *name, Error **errp) |
830 |
{ |
831 |
X86CPU *cpu = X86_CPU(obj); |
832 |
int64_t value; |
833 |
|
834 |
value = cpu->env.tsc_khz * 1000;
|
835 |
visit_type_int(v, &value, name, errp); |
836 |
} |
837 |
|
838 |
static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque, |
839 |
const char *name, Error **errp) |
840 |
{ |
841 |
X86CPU *cpu = X86_CPU(obj); |
842 |
const int64_t min = 0; |
843 |
const int64_t max = INT_MAX;
|
844 |
int64_t value; |
845 |
|
846 |
visit_type_int(v, &value, name, errp); |
847 |
if (error_is_set(errp)) {
|
848 |
return;
|
849 |
} |
850 |
if (value < min || value > max) {
|
851 |
error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
|
852 |
name ? name : "null", value, min, max);
|
853 |
return;
|
854 |
} |
855 |
|
856 |
cpu->env.tsc_khz = value / 1000;
|
857 |
} |
858 |
|
859 |
static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) |
860 |
{ |
861 |
unsigned int i; |
862 |
x86_def_t *def; |
863 |
|
864 |
char *s = g_strdup(cpu_model);
|
865 |
char *featurestr, *name = strtok(s, ","); |
866 |
/* Features to be added*/
|
867 |
uint32_t plus_features = 0, plus_ext_features = 0; |
868 |
uint32_t plus_ext2_features = 0, plus_ext3_features = 0; |
869 |
uint32_t plus_kvm_features = 0, plus_svm_features = 0; |
870 |
/* Features to be removed */
|
871 |
uint32_t minus_features = 0, minus_ext_features = 0; |
872 |
uint32_t minus_ext2_features = 0, minus_ext3_features = 0; |
873 |
uint32_t minus_kvm_features = 0, minus_svm_features = 0; |
874 |
uint32_t numvalue; |
875 |
|
876 |
for (def = x86_defs; def; def = def->next)
|
877 |
if (name && !strcmp(name, def->name))
|
878 |
break;
|
879 |
if (kvm_enabled() && name && strcmp(name, "host") == 0) { |
880 |
cpu_x86_fill_host(x86_cpu_def); |
881 |
} else if (!def) { |
882 |
goto error;
|
883 |
} else {
|
884 |
memcpy(x86_cpu_def, def, sizeof(*def));
|
885 |
} |
886 |
|
887 |
plus_kvm_features = ~0; /* not supported bits will be filtered out later */ |
888 |
|
889 |
add_flagname_to_bitmaps("hypervisor", &plus_features,
|
890 |
&plus_ext_features, &plus_ext2_features, &plus_ext3_features, |
891 |
&plus_kvm_features, &plus_svm_features); |
892 |
|
893 |
featurestr = strtok(NULL, ","); |
894 |
|
895 |
while (featurestr) {
|
896 |
char *val;
|
897 |
if (featurestr[0] == '+') { |
898 |
add_flagname_to_bitmaps(featurestr + 1, &plus_features,
|
899 |
&plus_ext_features, &plus_ext2_features, |
900 |
&plus_ext3_features, &plus_kvm_features, |
901 |
&plus_svm_features); |
902 |
} else if (featurestr[0] == '-') { |
903 |
add_flagname_to_bitmaps(featurestr + 1, &minus_features,
|
904 |
&minus_ext_features, &minus_ext2_features, |
905 |
&minus_ext3_features, &minus_kvm_features, |
906 |
&minus_svm_features); |
907 |
} else if ((val = strchr(featurestr, '='))) { |
908 |
*val = 0; val++;
|
909 |
if (!strcmp(featurestr, "family")) { |
910 |
char *err;
|
911 |
numvalue = strtoul(val, &err, 0);
|
912 |
if (!*val || *err || numvalue > 0xff + 0xf) { |
913 |
fprintf(stderr, "bad numerical value %s\n", val);
|
914 |
goto error;
|
915 |
} |
916 |
x86_cpu_def->family = numvalue; |
917 |
} else if (!strcmp(featurestr, "model")) { |
918 |
char *err;
|
919 |
numvalue = strtoul(val, &err, 0);
|
920 |
if (!*val || *err || numvalue > 0xff) { |
921 |
fprintf(stderr, "bad numerical value %s\n", val);
|
922 |
goto error;
|
923 |
} |
924 |
x86_cpu_def->model = numvalue; |
925 |
} else if (!strcmp(featurestr, "stepping")) { |
926 |
char *err;
|
927 |
numvalue = strtoul(val, &err, 0);
|
928 |
if (!*val || *err || numvalue > 0xf) { |
929 |
fprintf(stderr, "bad numerical value %s\n", val);
|
930 |
goto error;
|
931 |
} |
932 |
x86_cpu_def->stepping = numvalue ; |
933 |
} else if (!strcmp(featurestr, "level")) { |
934 |
char *err;
|
935 |
numvalue = strtoul(val, &err, 0);
|
936 |
if (!*val || *err) {
|
937 |
fprintf(stderr, "bad numerical value %s\n", val);
|
938 |
goto error;
|
939 |
} |
940 |
x86_cpu_def->level = numvalue; |
941 |
} else if (!strcmp(featurestr, "xlevel")) { |
942 |
char *err;
|
943 |
numvalue = strtoul(val, &err, 0);
|
944 |
if (!*val || *err) {
|
945 |
fprintf(stderr, "bad numerical value %s\n", val);
|
946 |
goto error;
|
947 |
} |
948 |
if (numvalue < 0x80000000) { |
949 |
numvalue += 0x80000000;
|
950 |
} |
951 |
x86_cpu_def->xlevel = numvalue; |
952 |
} else if (!strcmp(featurestr, "vendor")) { |
953 |
if (strlen(val) != 12) { |
954 |
fprintf(stderr, "vendor string must be 12 chars long\n");
|
955 |
goto error;
|
956 |
} |
957 |
x86_cpu_def->vendor1 = 0;
|
958 |
x86_cpu_def->vendor2 = 0;
|
959 |
x86_cpu_def->vendor3 = 0;
|
960 |
for(i = 0; i < 4; i++) { |
961 |
x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
|
962 |
x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i); |
963 |
x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i); |
964 |
} |
965 |
x86_cpu_def->vendor_override = 1;
|
966 |
} else if (!strcmp(featurestr, "model_id")) { |
967 |
pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
|
968 |
val); |
969 |
} else if (!strcmp(featurestr, "tsc_freq")) { |
970 |
int64_t tsc_freq; |
971 |
char *err;
|
972 |
|
973 |
tsc_freq = strtosz_suffix_unit(val, &err, |
974 |
STRTOSZ_DEFSUFFIX_B, 1000);
|
975 |
if (tsc_freq < 0 || *err) { |
976 |
fprintf(stderr, "bad numerical value %s\n", val);
|
977 |
goto error;
|
978 |
} |
979 |
x86_cpu_def->tsc_khz = tsc_freq / 1000;
|
980 |
} else if (!strcmp(featurestr, "hv_spinlocks")) { |
981 |
char *err;
|
982 |
numvalue = strtoul(val, &err, 0);
|
983 |
if (!*val || *err) {
|
984 |
fprintf(stderr, "bad numerical value %s\n", val);
|
985 |
goto error;
|
986 |
} |
987 |
hyperv_set_spinlock_retries(numvalue); |
988 |
} else {
|
989 |
fprintf(stderr, "unrecognized feature %s\n", featurestr);
|
990 |
goto error;
|
991 |
} |
992 |
} else if (!strcmp(featurestr, "check")) { |
993 |
check_cpuid = 1;
|
994 |
} else if (!strcmp(featurestr, "enforce")) { |
995 |
check_cpuid = enforce_cpuid = 1;
|
996 |
} else if (!strcmp(featurestr, "hv_relaxed")) { |
997 |
hyperv_enable_relaxed_timing(true);
|
998 |
} else if (!strcmp(featurestr, "hv_vapic")) { |
999 |
hyperv_enable_vapic_recommended(true);
|
1000 |
} else {
|
1001 |
fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
|
1002 |
goto error;
|
1003 |
} |
1004 |
featurestr = strtok(NULL, ","); |
1005 |
} |
1006 |
x86_cpu_def->features |= plus_features; |
1007 |
x86_cpu_def->ext_features |= plus_ext_features; |
1008 |
x86_cpu_def->ext2_features |= plus_ext2_features; |
1009 |
x86_cpu_def->ext3_features |= plus_ext3_features; |
1010 |
x86_cpu_def->kvm_features |= plus_kvm_features; |
1011 |
x86_cpu_def->svm_features |= plus_svm_features; |
1012 |
x86_cpu_def->features &= ~minus_features; |
1013 |
x86_cpu_def->ext_features &= ~minus_ext_features; |
1014 |
x86_cpu_def->ext2_features &= ~minus_ext2_features; |
1015 |
x86_cpu_def->ext3_features &= ~minus_ext3_features; |
1016 |
x86_cpu_def->kvm_features &= ~minus_kvm_features; |
1017 |
x86_cpu_def->svm_features &= ~minus_svm_features; |
1018 |
if (check_cpuid) {
|
1019 |
if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
|
1020 |
goto error;
|
1021 |
} |
1022 |
g_free(s); |
1023 |
return 0; |
1024 |
|
1025 |
error:
|
1026 |
g_free(s); |
1027 |
return -1; |
1028 |
} |
1029 |
|
1030 |
/* generate a composite string into buf of all cpuid names in featureset
|
1031 |
* selected by fbits. indicate truncation at bufsize in the event of overflow.
|
1032 |
* if flags, suppress names undefined in featureset.
|
1033 |
*/
|
1034 |
static void listflags(char *buf, int bufsize, uint32_t fbits, |
1035 |
const char **featureset, uint32_t flags) |
1036 |
{ |
1037 |
const char **p = &featureset[31]; |
1038 |
char *q, *b, bit;
|
1039 |
int nc;
|
1040 |
|
1041 |
b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL; |
1042 |
*buf = '\0';
|
1043 |
for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit) |
1044 |
if (fbits & 1 << bit && (*p || !flags)) { |
1045 |
if (*p)
|
1046 |
nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p); |
1047 |
else
|
1048 |
nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit); |
1049 |
if (bufsize <= nc) {
|
1050 |
if (b) {
|
1051 |
memcpy(b, "...", sizeof("...")); |
1052 |
} |
1053 |
return;
|
1054 |
} |
1055 |
q += nc; |
1056 |
bufsize -= nc; |
1057 |
} |
1058 |
} |
1059 |
|
1060 |
/* generate CPU information:
|
1061 |
* -? list model names
|
1062 |
* -?model list model names/IDs
|
1063 |
* -?dump output all model (x86_def_t) data
|
1064 |
* -?cpuid list all recognized cpuid flag names
|
1065 |
*/
|
1066 |
void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg) |
1067 |
{ |
1068 |
unsigned char model = !strcmp("?model", optarg); |
1069 |
unsigned char dump = !strcmp("?dump", optarg); |
1070 |
unsigned char cpuid = !strcmp("?cpuid", optarg); |
1071 |
x86_def_t *def; |
1072 |
char buf[256]; |
1073 |
|
1074 |
if (cpuid) {
|
1075 |
(*cpu_fprintf)(f, "Recognized CPUID flags:\n");
|
1076 |
listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1); |
1077 |
(*cpu_fprintf)(f, " f_edx: %s\n", buf);
|
1078 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1); |
1079 |
(*cpu_fprintf)(f, " f_ecx: %s\n", buf);
|
1080 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1); |
1081 |
(*cpu_fprintf)(f, " extf_edx: %s\n", buf);
|
1082 |
listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1); |
1083 |
(*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
|
1084 |
return;
|
1085 |
} |
1086 |
for (def = x86_defs; def; def = def->next) {
|
1087 |
snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name); |
1088 |
if (model || dump) {
|
1089 |
(*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
|
1090 |
} else {
|
1091 |
(*cpu_fprintf)(f, "x86 %16s\n", buf);
|
1092 |
} |
1093 |
if (dump) {
|
1094 |
memcpy(buf, &def->vendor1, sizeof (def->vendor1));
|
1095 |
memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2)); |
1096 |
memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3)); |
1097 |
buf[12] = '\0'; |
1098 |
(*cpu_fprintf)(f, |
1099 |
" family %d model %d stepping %d level %d xlevel 0x%x"
|
1100 |
" vendor \"%s\"\n",
|
1101 |
def->family, def->model, def->stepping, def->level, |
1102 |
def->xlevel, buf); |
1103 |
listflags(buf, sizeof (buf), def->features, feature_name, 0); |
1104 |
(*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
|
1105 |
buf); |
1106 |
listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
|
1107 |
0);
|
1108 |
(*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
|
1109 |
buf); |
1110 |
listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
|
1111 |
0);
|
1112 |
(*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
|
1113 |
def->ext2_features, buf); |
1114 |
listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
|
1115 |
0);
|
1116 |
(*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
|
1117 |
def->ext3_features, buf); |
1118 |
(*cpu_fprintf)(f, "\n");
|
1119 |
} |
1120 |
} |
1121 |
if (kvm_enabled()) {
|
1122 |
(*cpu_fprintf)(f, "x86 %16s\n", "[host]"); |
1123 |
} |
1124 |
} |
1125 |
|
1126 |
int cpu_x86_register(X86CPU *cpu, const char *cpu_model) |
1127 |
{ |
1128 |
CPUX86State *env = &cpu->env; |
1129 |
x86_def_t def1, *def = &def1; |
1130 |
Error *error = NULL;
|
1131 |
|
1132 |
memset(def, 0, sizeof(*def)); |
1133 |
|
1134 |
if (cpu_x86_find_by_name(def, cpu_model) < 0) |
1135 |
return -1; |
1136 |
if (def->vendor1) {
|
1137 |
env->cpuid_vendor1 = def->vendor1; |
1138 |
env->cpuid_vendor2 = def->vendor2; |
1139 |
env->cpuid_vendor3 = def->vendor3; |
1140 |
} else {
|
1141 |
env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1; |
1142 |
env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2; |
1143 |
env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3; |
1144 |
} |
1145 |
env->cpuid_vendor_override = def->vendor_override; |
1146 |
object_property_set_int(OBJECT(cpu), def->level, "level", &error);
|
1147 |
object_property_set_int(OBJECT(cpu), def->family, "family", &error);
|
1148 |
object_property_set_int(OBJECT(cpu), def->model, "model", &error);
|
1149 |
object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
|
1150 |
env->cpuid_features = def->features; |
1151 |
env->cpuid_ext_features = def->ext_features; |
1152 |
env->cpuid_ext2_features = def->ext2_features; |
1153 |
env->cpuid_ext3_features = def->ext3_features; |
1154 |
object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
|
1155 |
env->cpuid_kvm_features = def->kvm_features; |
1156 |
env->cpuid_svm_features = def->svm_features; |
1157 |
env->cpuid_ext4_features = def->ext4_features; |
1158 |
env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features; |
1159 |
env->cpuid_xlevel2 = def->xlevel2; |
1160 |
object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
|
1161 |
"tsc-frequency", &error);
|
1162 |
if (!kvm_enabled()) {
|
1163 |
env->cpuid_features &= TCG_FEATURES; |
1164 |
env->cpuid_ext_features &= TCG_EXT_FEATURES; |
1165 |
env->cpuid_ext2_features &= (TCG_EXT2_FEATURES |
1166 |
#ifdef TARGET_X86_64
|
1167 |
| CPUID_EXT2_SYSCALL | CPUID_EXT2_LM |
1168 |
#endif
|
1169 |
); |
1170 |
env->cpuid_ext3_features &= TCG_EXT3_FEATURES; |
1171 |
env->cpuid_svm_features &= TCG_SVM_FEATURES; |
1172 |
} |
1173 |
object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
|
1174 |
if (error_is_set(&error)) {
|
1175 |
error_free(error); |
1176 |
return -1; |
1177 |
} |
1178 |
return 0; |
1179 |
} |
1180 |
|
1181 |
#if !defined(CONFIG_USER_ONLY)
|
1182 |
/* copy vendor id string to 32 bit register, nul pad as needed
|
1183 |
*/
|
1184 |
static void cpyid(const char *s, uint32_t *id) |
1185 |
{ |
1186 |
char *d = (char *)id; |
1187 |
char i;
|
1188 |
|
1189 |
for (i = sizeof (*id); i--; ) |
1190 |
*d++ = *s ? *s++ : '\0';
|
1191 |
} |
1192 |
|
1193 |
/* interpret radix and convert from string to arbitrary scalar,
|
1194 |
* otherwise flag failure
|
1195 |
*/
|
1196 |
#define setscalar(pval, str, perr) \
|
1197 |
{ \ |
1198 |
char *pend; \
|
1199 |
unsigned long ul; \ |
1200 |
\ |
1201 |
ul = strtoul(str, &pend, 0); \
|
1202 |
*str && !*pend ? (*pval = ul) : (*perr = 1); \
|
1203 |
} |
1204 |
|
1205 |
/* map cpuid options to feature bits, otherwise return failure
|
1206 |
* (option tags in *str are delimited by whitespace)
|
1207 |
*/
|
1208 |
static void setfeatures(uint32_t *pval, const char *str, |
1209 |
const char **featureset, int *perr) |
1210 |
{ |
1211 |
const char *p, *q; |
1212 |
|
1213 |
for (q = p = str; *p || *q; q = p) {
|
1214 |
while (iswhite(*p))
|
1215 |
q = ++p; |
1216 |
while (*p && !iswhite(*p))
|
1217 |
++p; |
1218 |
if (!*q && !*p)
|
1219 |
return;
|
1220 |
if (!lookup_feature(pval, q, p, featureset)) {
|
1221 |
fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
|
1222 |
(int)(p - q), q);
|
1223 |
*perr = 1;
|
1224 |
return;
|
1225 |
} |
1226 |
} |
1227 |
} |
1228 |
|
1229 |
/* map config file options to x86_def_t form
|
1230 |
*/
|
1231 |
static int cpudef_setfield(const char *name, const char *str, void *opaque) |
1232 |
{ |
1233 |
x86_def_t *def = opaque; |
1234 |
int err = 0; |
1235 |
|
1236 |
if (!strcmp(name, "name")) { |
1237 |
g_free((void *)def->name);
|
1238 |
def->name = g_strdup(str); |
1239 |
} else if (!strcmp(name, "model_id")) { |
1240 |
strncpy(def->model_id, str, sizeof (def->model_id));
|
1241 |
} else if (!strcmp(name, "level")) { |
1242 |
setscalar(&def->level, str, &err) |
1243 |
} else if (!strcmp(name, "vendor")) { |
1244 |
cpyid(&str[0], &def->vendor1);
|
1245 |
cpyid(&str[4], &def->vendor2);
|
1246 |
cpyid(&str[8], &def->vendor3);
|
1247 |
} else if (!strcmp(name, "family")) { |
1248 |
setscalar(&def->family, str, &err) |
1249 |
} else if (!strcmp(name, "model")) { |
1250 |
setscalar(&def->model, str, &err) |
1251 |
} else if (!strcmp(name, "stepping")) { |
1252 |
setscalar(&def->stepping, str, &err) |
1253 |
} else if (!strcmp(name, "feature_edx")) { |
1254 |
setfeatures(&def->features, str, feature_name, &err); |
1255 |
} else if (!strcmp(name, "feature_ecx")) { |
1256 |
setfeatures(&def->ext_features, str, ext_feature_name, &err); |
1257 |
} else if (!strcmp(name, "extfeature_edx")) { |
1258 |
setfeatures(&def->ext2_features, str, ext2_feature_name, &err); |
1259 |
} else if (!strcmp(name, "extfeature_ecx")) { |
1260 |
setfeatures(&def->ext3_features, str, ext3_feature_name, &err); |
1261 |
} else if (!strcmp(name, "xlevel")) { |
1262 |
setscalar(&def->xlevel, str, &err) |
1263 |
} else {
|
1264 |
fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
|
1265 |
return (1); |
1266 |
} |
1267 |
if (err) {
|
1268 |
fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
|
1269 |
return (1); |
1270 |
} |
1271 |
return (0); |
1272 |
} |
1273 |
|
1274 |
/* register config file entry as x86_def_t
|
1275 |
*/
|
1276 |
static int cpudef_register(QemuOpts *opts, void *opaque) |
1277 |
{ |
1278 |
x86_def_t *def = g_malloc0(sizeof (x86_def_t));
|
1279 |
|
1280 |
qemu_opt_foreach(opts, cpudef_setfield, def, 1);
|
1281 |
def->next = x86_defs; |
1282 |
x86_defs = def; |
1283 |
return (0); |
1284 |
} |
1285 |
|
1286 |
void cpu_clear_apic_feature(CPUX86State *env)
|
1287 |
{ |
1288 |
env->cpuid_features &= ~CPUID_APIC; |
1289 |
} |
1290 |
|
1291 |
#endif /* !CONFIG_USER_ONLY */ |
1292 |
|
1293 |
/* register "cpudef" models defined in configuration file. Here we first
|
1294 |
* preload any built-in definitions
|
1295 |
*/
|
1296 |
void x86_cpudef_setup(void) |
1297 |
{ |
1298 |
int i, j;
|
1299 |
static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" }; |
1300 |
|
1301 |
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) { |
1302 |
builtin_x86_defs[i].next = x86_defs; |
1303 |
builtin_x86_defs[i].flags = 1;
|
1304 |
|
1305 |
/* Look for specific "cpudef" models that */
|
1306 |
/* have the QEMU version in .model_id */
|
1307 |
for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) { |
1308 |
if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) { |
1309 |
pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version "); |
1310 |
pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
|
1311 |
break;
|
1312 |
} |
1313 |
} |
1314 |
|
1315 |
x86_defs = &builtin_x86_defs[i]; |
1316 |
} |
1317 |
#if !defined(CONFIG_USER_ONLY)
|
1318 |
qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0); |
1319 |
#endif
|
1320 |
} |
1321 |
|
1322 |
static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx, |
1323 |
uint32_t *ecx, uint32_t *edx) |
1324 |
{ |
1325 |
*ebx = env->cpuid_vendor1; |
1326 |
*edx = env->cpuid_vendor2; |
1327 |
*ecx = env->cpuid_vendor3; |
1328 |
|
1329 |
/* sysenter isn't supported on compatibility mode on AMD, syscall
|
1330 |
* isn't supported in compatibility mode on Intel.
|
1331 |
* Normally we advertise the actual cpu vendor, but you can override
|
1332 |
* this if you want to use KVM's sysenter/syscall emulation
|
1333 |
* in compatibility mode and when doing cross vendor migration
|
1334 |
*/
|
1335 |
if (kvm_enabled() && ! env->cpuid_vendor_override) {
|
1336 |
host_cpuid(0, 0, NULL, ebx, ecx, edx); |
1337 |
} |
1338 |
} |
1339 |
|
1340 |
void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
|
1341 |
uint32_t *eax, uint32_t *ebx, |
1342 |
uint32_t *ecx, uint32_t *edx) |
1343 |
{ |
1344 |
/* test if maximum index reached */
|
1345 |
if (index & 0x80000000) { |
1346 |
if (index > env->cpuid_xlevel) {
|
1347 |
if (env->cpuid_xlevel2 > 0) { |
1348 |
/* Handle the Centaur's CPUID instruction. */
|
1349 |
if (index > env->cpuid_xlevel2) {
|
1350 |
index = env->cpuid_xlevel2; |
1351 |
} else if (index < 0xC0000000) { |
1352 |
index = env->cpuid_xlevel; |
1353 |
} |
1354 |
} else {
|
1355 |
index = env->cpuid_xlevel; |
1356 |
} |
1357 |
} |
1358 |
} else {
|
1359 |
if (index > env->cpuid_level)
|
1360 |
index = env->cpuid_level; |
1361 |
} |
1362 |
|
1363 |
switch(index) {
|
1364 |
case 0: |
1365 |
*eax = env->cpuid_level; |
1366 |
get_cpuid_vendor(env, ebx, ecx, edx); |
1367 |
break;
|
1368 |
case 1: |
1369 |
*eax = env->cpuid_version; |
1370 |
*ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */ |
1371 |
*ecx = env->cpuid_ext_features; |
1372 |
*edx = env->cpuid_features; |
1373 |
if (env->nr_cores * env->nr_threads > 1) { |
1374 |
*ebx |= (env->nr_cores * env->nr_threads) << 16;
|
1375 |
*edx |= 1 << 28; /* HTT bit */ |
1376 |
} |
1377 |
break;
|
1378 |
case 2: |
1379 |
/* cache info: needed for Pentium Pro compatibility */
|
1380 |
*eax = 1;
|
1381 |
*ebx = 0;
|
1382 |
*ecx = 0;
|
1383 |
*edx = 0x2c307d;
|
1384 |
break;
|
1385 |
case 4: |
1386 |
/* cache info: needed for Core compatibility */
|
1387 |
if (env->nr_cores > 1) { |
1388 |
*eax = (env->nr_cores - 1) << 26; |
1389 |
} else {
|
1390 |
*eax = 0;
|
1391 |
} |
1392 |
switch (count) {
|
1393 |
case 0: /* L1 dcache info */ |
1394 |
*eax |= 0x0000121;
|
1395 |
*ebx = 0x1c0003f;
|
1396 |
*ecx = 0x000003f;
|
1397 |
*edx = 0x0000001;
|
1398 |
break;
|
1399 |
case 1: /* L1 icache info */ |
1400 |
*eax |= 0x0000122;
|
1401 |
*ebx = 0x1c0003f;
|
1402 |
*ecx = 0x000003f;
|
1403 |
*edx = 0x0000001;
|
1404 |
break;
|
1405 |
case 2: /* L2 cache info */ |
1406 |
*eax |= 0x0000143;
|
1407 |
if (env->nr_threads > 1) { |
1408 |
*eax |= (env->nr_threads - 1) << 14; |
1409 |
} |
1410 |
*ebx = 0x3c0003f;
|
1411 |
*ecx = 0x0000fff;
|
1412 |
*edx = 0x0000001;
|
1413 |
break;
|
1414 |
default: /* end of info */ |
1415 |
*eax = 0;
|
1416 |
*ebx = 0;
|
1417 |
*ecx = 0;
|
1418 |
*edx = 0;
|
1419 |
break;
|
1420 |
} |
1421 |
break;
|
1422 |
case 5: |
1423 |
/* mwait info: needed for Core compatibility */
|
1424 |
*eax = 0; /* Smallest monitor-line size in bytes */ |
1425 |
*ebx = 0; /* Largest monitor-line size in bytes */ |
1426 |
*ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE; |
1427 |
*edx = 0;
|
1428 |
break;
|
1429 |
case 6: |
1430 |
/* Thermal and Power Leaf */
|
1431 |
*eax = 0;
|
1432 |
*ebx = 0;
|
1433 |
*ecx = 0;
|
1434 |
*edx = 0;
|
1435 |
break;
|
1436 |
case 7: |
1437 |
/* Structured Extended Feature Flags Enumeration Leaf */
|
1438 |
if (count == 0) { |
1439 |
*eax = 0; /* Maximum ECX value for sub-leaves */ |
1440 |
*ebx = env->cpuid_7_0_ebx; /* Feature flags */
|
1441 |
*ecx = 0; /* Reserved */ |
1442 |
*edx = 0; /* Reserved */ |
1443 |
} else {
|
1444 |
*eax = 0;
|
1445 |
*ebx = 0;
|
1446 |
*ecx = 0;
|
1447 |
*edx = 0;
|
1448 |
} |
1449 |
break;
|
1450 |
case 9: |
1451 |
/* Direct Cache Access Information Leaf */
|
1452 |
*eax = 0; /* Bits 0-31 in DCA_CAP MSR */ |
1453 |
*ebx = 0;
|
1454 |
*ecx = 0;
|
1455 |
*edx = 0;
|
1456 |
break;
|
1457 |
case 0xA: |
1458 |
/* Architectural Performance Monitoring Leaf */
|
1459 |
if (kvm_enabled()) {
|
1460 |
KVMState *s = env->kvm_state; |
1461 |
|
1462 |
*eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
|
1463 |
*ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
|
1464 |
*ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
|
1465 |
*edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
|
1466 |
} else {
|
1467 |
*eax = 0;
|
1468 |
*ebx = 0;
|
1469 |
*ecx = 0;
|
1470 |
*edx = 0;
|
1471 |
} |
1472 |
break;
|
1473 |
case 0xD: |
1474 |
/* Processor Extended State */
|
1475 |
if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
|
1476 |
*eax = 0;
|
1477 |
*ebx = 0;
|
1478 |
*ecx = 0;
|
1479 |
*edx = 0;
|
1480 |
break;
|
1481 |
} |
1482 |
if (kvm_enabled()) {
|
1483 |
KVMState *s = env->kvm_state; |
1484 |
|
1485 |
*eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
|
1486 |
*ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
|
1487 |
*ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
|
1488 |
*edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
|
1489 |
} else {
|
1490 |
*eax = 0;
|
1491 |
*ebx = 0;
|
1492 |
*ecx = 0;
|
1493 |
*edx = 0;
|
1494 |
} |
1495 |
break;
|
1496 |
case 0x80000000: |
1497 |
*eax = env->cpuid_xlevel; |
1498 |
*ebx = env->cpuid_vendor1; |
1499 |
*edx = env->cpuid_vendor2; |
1500 |
*ecx = env->cpuid_vendor3; |
1501 |
break;
|
1502 |
case 0x80000001: |
1503 |
*eax = env->cpuid_version; |
1504 |
*ebx = 0;
|
1505 |
*ecx = env->cpuid_ext3_features; |
1506 |
*edx = env->cpuid_ext2_features; |
1507 |
|
1508 |
/* The Linux kernel checks for the CMPLegacy bit and
|
1509 |
* discards multiple thread information if it is set.
|
1510 |
* So dont set it here for Intel to make Linux guests happy.
|
1511 |
*/
|
1512 |
if (env->nr_cores * env->nr_threads > 1) { |
1513 |
uint32_t tebx, tecx, tedx; |
1514 |
get_cpuid_vendor(env, &tebx, &tecx, &tedx); |
1515 |
if (tebx != CPUID_VENDOR_INTEL_1 ||
|
1516 |
tedx != CPUID_VENDOR_INTEL_2 || |
1517 |
tecx != CPUID_VENDOR_INTEL_3) { |
1518 |
*ecx |= 1 << 1; /* CmpLegacy bit */ |
1519 |
} |
1520 |
} |
1521 |
break;
|
1522 |
case 0x80000002: |
1523 |
case 0x80000003: |
1524 |
case 0x80000004: |
1525 |
*eax = env->cpuid_model[(index - 0x80000002) * 4 + 0]; |
1526 |
*ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1]; |
1527 |
*ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2]; |
1528 |
*edx = env->cpuid_model[(index - 0x80000002) * 4 + 3]; |
1529 |
break;
|
1530 |
case 0x80000005: |
1531 |
/* cache info (L1 cache) */
|
1532 |
*eax = 0x01ff01ff;
|
1533 |
*ebx = 0x01ff01ff;
|
1534 |
*ecx = 0x40020140;
|
1535 |
*edx = 0x40020140;
|
1536 |
break;
|
1537 |
case 0x80000006: |
1538 |
/* cache info (L2 cache) */
|
1539 |
*eax = 0;
|
1540 |
*ebx = 0x42004200;
|
1541 |
*ecx = 0x02008140;
|
1542 |
*edx = 0;
|
1543 |
break;
|
1544 |
case 0x80000008: |
1545 |
/* virtual & phys address size in low 2 bytes. */
|
1546 |
/* XXX: This value must match the one used in the MMU code. */
|
1547 |
if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
|
1548 |
/* 64 bit processor */
|
1549 |
/* XXX: The physical address space is limited to 42 bits in exec.c. */
|
1550 |
*eax = 0x00003028; /* 48 bits virtual, 40 bits physical */ |
1551 |
} else {
|
1552 |
if (env->cpuid_features & CPUID_PSE36)
|
1553 |
*eax = 0x00000024; /* 36 bits physical */ |
1554 |
else
|
1555 |
*eax = 0x00000020; /* 32 bits physical */ |
1556 |
} |
1557 |
*ebx = 0;
|
1558 |
*ecx = 0;
|
1559 |
*edx = 0;
|
1560 |
if (env->nr_cores * env->nr_threads > 1) { |
1561 |
*ecx |= (env->nr_cores * env->nr_threads) - 1;
|
1562 |
} |
1563 |
break;
|
1564 |
case 0x8000000A: |
1565 |
if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
|
1566 |
*eax = 0x00000001; /* SVM Revision */ |
1567 |
*ebx = 0x00000010; /* nr of ASIDs */ |
1568 |
*ecx = 0;
|
1569 |
*edx = env->cpuid_svm_features; /* optional features */
|
1570 |
} else {
|
1571 |
*eax = 0;
|
1572 |
*ebx = 0;
|
1573 |
*ecx = 0;
|
1574 |
*edx = 0;
|
1575 |
} |
1576 |
break;
|
1577 |
case 0xC0000000: |
1578 |
*eax = env->cpuid_xlevel2; |
1579 |
*ebx = 0;
|
1580 |
*ecx = 0;
|
1581 |
*edx = 0;
|
1582 |
break;
|
1583 |
case 0xC0000001: |
1584 |
/* Support for VIA CPU's CPUID instruction */
|
1585 |
*eax = env->cpuid_version; |
1586 |
*ebx = 0;
|
1587 |
*ecx = 0;
|
1588 |
*edx = env->cpuid_ext4_features; |
1589 |
break;
|
1590 |
case 0xC0000002: |
1591 |
case 0xC0000003: |
1592 |
case 0xC0000004: |
1593 |
/* Reserved for the future, and now filled with zero */
|
1594 |
*eax = 0;
|
1595 |
*ebx = 0;
|
1596 |
*ecx = 0;
|
1597 |
*edx = 0;
|
1598 |
break;
|
1599 |
default:
|
1600 |
/* reserved values: zero */
|
1601 |
*eax = 0;
|
1602 |
*ebx = 0;
|
1603 |
*ecx = 0;
|
1604 |
*edx = 0;
|
1605 |
break;
|
1606 |
} |
1607 |
} |
1608 |
|
1609 |
/* CPUClass::reset() */
|
1610 |
static void x86_cpu_reset(CPUState *s) |
1611 |
{ |
1612 |
X86CPU *cpu = X86_CPU(s); |
1613 |
X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu); |
1614 |
CPUX86State *env = &cpu->env; |
1615 |
int i;
|
1616 |
|
1617 |
if (qemu_loglevel_mask(CPU_LOG_RESET)) {
|
1618 |
qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
|
1619 |
log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP); |
1620 |
} |
1621 |
|
1622 |
xcc->parent_reset(s); |
1623 |
|
1624 |
|
1625 |
memset(env, 0, offsetof(CPUX86State, breakpoints));
|
1626 |
|
1627 |
tlb_flush(env, 1);
|
1628 |
|
1629 |
env->old_exception = -1;
|
1630 |
|
1631 |
/* init to reset state */
|
1632 |
|
1633 |
#ifdef CONFIG_SOFTMMU
|
1634 |
env->hflags |= HF_SOFTMMU_MASK; |
1635 |
#endif
|
1636 |
env->hflags2 |= HF2_GIF_MASK; |
1637 |
|
1638 |
cpu_x86_update_cr0(env, 0x60000010);
|
1639 |
env->a20_mask = ~0x0;
|
1640 |
env->smbase = 0x30000;
|
1641 |
|
1642 |
env->idt.limit = 0xffff;
|
1643 |
env->gdt.limit = 0xffff;
|
1644 |
env->ldt.limit = 0xffff;
|
1645 |
env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
|
1646 |
env->tr.limit = 0xffff;
|
1647 |
env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
|
1648 |
|
1649 |
cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff, |
1650 |
DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK | |
1651 |
DESC_R_MASK | DESC_A_MASK); |
1652 |
cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff, |
1653 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1654 |
DESC_A_MASK); |
1655 |
cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff, |
1656 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1657 |
DESC_A_MASK); |
1658 |
cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff, |
1659 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1660 |
DESC_A_MASK); |
1661 |
cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff, |
1662 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1663 |
DESC_A_MASK); |
1664 |
cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff, |
1665 |
DESC_P_MASK | DESC_S_MASK | DESC_W_MASK | |
1666 |
DESC_A_MASK); |
1667 |
|
1668 |
env->eip = 0xfff0;
|
1669 |
env->regs[R_EDX] = env->cpuid_version; |
1670 |
|
1671 |
env->eflags = 0x2;
|
1672 |
|
1673 |
/* FPU init */
|
1674 |
for (i = 0; i < 8; i++) { |
1675 |
env->fptags[i] = 1;
|
1676 |
} |
1677 |
env->fpuc = 0x37f;
|
1678 |
|
1679 |
env->mxcsr = 0x1f80;
|
1680 |
|
1681 |
env->pat = 0x0007040600070406ULL;
|
1682 |
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT; |
1683 |
|
1684 |
memset(env->dr, 0, sizeof(env->dr)); |
1685 |
env->dr[6] = DR6_FIXED_1;
|
1686 |
env->dr[7] = DR7_FIXED_1;
|
1687 |
cpu_breakpoint_remove_all(env, BP_CPU); |
1688 |
cpu_watchpoint_remove_all(env, BP_CPU); |
1689 |
} |
1690 |
|
1691 |
static void mce_init(X86CPU *cpu) |
1692 |
{ |
1693 |
CPUX86State *cenv = &cpu->env; |
1694 |
unsigned int bank; |
1695 |
|
1696 |
if (((cenv->cpuid_version >> 8) & 0xf) >= 6 |
1697 |
&& (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) == |
1698 |
(CPUID_MCE | CPUID_MCA)) { |
1699 |
cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF; |
1700 |
cenv->mcg_ctl = ~(uint64_t)0;
|
1701 |
for (bank = 0; bank < MCE_BANKS_DEF; bank++) { |
1702 |
cenv->mce_banks[bank * 4] = ~(uint64_t)0; |
1703 |
} |
1704 |
} |
1705 |
} |
1706 |
|
1707 |
void x86_cpu_realize(Object *obj, Error **errp)
|
1708 |
{ |
1709 |
X86CPU *cpu = X86_CPU(obj); |
1710 |
|
1711 |
mce_init(cpu); |
1712 |
qemu_init_vcpu(&cpu->env); |
1713 |
} |
1714 |
|
1715 |
static void x86_cpu_initfn(Object *obj) |
1716 |
{ |
1717 |
X86CPU *cpu = X86_CPU(obj); |
1718 |
CPUX86State *env = &cpu->env; |
1719 |
|
1720 |
cpu_exec_init(env); |
1721 |
|
1722 |
object_property_add(obj, "family", "int", |
1723 |
x86_cpuid_version_get_family, |
1724 |
x86_cpuid_version_set_family, NULL, NULL, NULL); |
1725 |
object_property_add(obj, "model", "int", |
1726 |
x86_cpuid_version_get_model, |
1727 |
x86_cpuid_version_set_model, NULL, NULL, NULL); |
1728 |
object_property_add(obj, "stepping", "int", |
1729 |
x86_cpuid_version_get_stepping, |
1730 |
x86_cpuid_version_set_stepping, NULL, NULL, NULL); |
1731 |
object_property_add(obj, "level", "int", |
1732 |
x86_cpuid_get_level, |
1733 |
x86_cpuid_set_level, NULL, NULL, NULL); |
1734 |
object_property_add(obj, "xlevel", "int", |
1735 |
x86_cpuid_get_xlevel, |
1736 |
x86_cpuid_set_xlevel, NULL, NULL, NULL); |
1737 |
object_property_add_str(obj, "vendor",
|
1738 |
x86_cpuid_get_vendor, |
1739 |
x86_cpuid_set_vendor, NULL);
|
1740 |
object_property_add_str(obj, "model-id",
|
1741 |
x86_cpuid_get_model_id, |
1742 |
x86_cpuid_set_model_id, NULL);
|
1743 |
object_property_add(obj, "tsc-frequency", "int", |
1744 |
x86_cpuid_get_tsc_freq, |
1745 |
x86_cpuid_set_tsc_freq, NULL, NULL, NULL); |
1746 |
|
1747 |
env->cpuid_apic_id = env->cpu_index; |
1748 |
} |
1749 |
|
1750 |
static void x86_cpu_common_class_init(ObjectClass *oc, void *data) |
1751 |
{ |
1752 |
X86CPUClass *xcc = X86_CPU_CLASS(oc); |
1753 |
CPUClass *cc = CPU_CLASS(oc); |
1754 |
|
1755 |
xcc->parent_reset = cc->reset; |
1756 |
cc->reset = x86_cpu_reset; |
1757 |
} |
1758 |
|
1759 |
static const TypeInfo x86_cpu_type_info = { |
1760 |
.name = TYPE_X86_CPU, |
1761 |
.parent = TYPE_CPU, |
1762 |
.instance_size = sizeof(X86CPU),
|
1763 |
.instance_init = x86_cpu_initfn, |
1764 |
.abstract = false,
|
1765 |
.class_size = sizeof(X86CPUClass),
|
1766 |
.class_init = x86_cpu_common_class_init, |
1767 |
}; |
1768 |
|
1769 |
static void x86_cpu_register_types(void) |
1770 |
{ |
1771 |
type_register_static(&x86_cpu_type_info); |
1772 |
} |
1773 |
|
1774 |
type_init(x86_cpu_register_types) |