Archipelago » qemu

/*

 *  qemu user main

 *

 *  Copyright (c) 2003-2008 Fabrice Bellard

 *

 *  This program is free software; you can redistribute it and/or modify

 *  it under the terms of the GNU General Public License as published by

 *  the Free Software Foundation; either version 2 of the License, or

 *  (at your option) any later version.

 *

 *  This program is distributed in the hope that it will be useful,

 *  but WITHOUT ANY WARRANTY; without even the implied warranty of

 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 *  GNU General Public License for more details.

 *

 *  You should have received a copy of the GNU General Public License

 *  along with this program; if not, see <http://www.gnu.org/licenses/>.

 */

#include <stdlib.h>

#include <stdio.h>

#include <stdarg.h>

#include <string.h>

#include <errno.h>

#include <unistd.h>

#include <sys/mman.h>

#include <sys/syscall.h>

#include <sys/resource.h>

#include "qemu.h"

#include "qemu-common.h"

#include "qemu/cache-utils.h"

#include "cpu.h"

#include "tcg.h"

#include "qemu/timer.h"

#include "qemu/envlist.h"

#include "elf.h"

char *exec_path;

int singlestep;

const char *filename;

const char *argv0;

int gdbstub_port;

envlist_t *envlist;

static const char *cpu_model;

unsigned long mmap_min_addr;

#if defined(CONFIG_USE_GUEST_BASE)

unsigned long guest_base;

int have_guest_base;

#if (TARGET_LONG_BITS == 32) && (HOST_LONG_BITS == 64)

/*

 * When running 32-on-64 we should make sure we can fit all of the possible

 * guest address space into a contiguous chunk of virtual host memory.

 *

 * This way we will never overlap with our own libraries or binaries or stack

 * or anything else that QEMU maps.

 */

# ifdef TARGET_MIPS

/* MIPS only supports 31 bits of virtual address space for user space */

unsigned long reserved_va = 0x77000000;

# else

unsigned long reserved_va = 0xf7000000;

# endif

#else

unsigned long reserved_va;

#endif

#endif

static void usage(void);

static const char *interp_prefix = CONFIG_QEMU_INTERP_PREFIX;

const char *qemu_uname_release = CONFIG_UNAME_RELEASE;

/* XXX: on x86 MAP_GROWSDOWN only works if ESP <= address + 32, so

   we allocate a bigger stack. Need a better solution, for example

   by remapping the process stack directly at the right place */

unsigned long guest_stack_size = 8 * 1024 * 1024UL;

void gemu_log(const char *fmt, ...)

{

    va_list ap;

    va_start(ap, fmt);

    vfprintf(stderr, fmt, ap);

    va_end(ap);

}

#if defined(TARGET_I386)

int cpu_get_pic_interrupt(CPUX86State *env)

{

    return -1;

}

#endif

/***********************************************************/

/* Helper routines for implementing atomic operations.  */

/* To implement exclusive operations we force all cpus to syncronise.

   We don't require a full sync, only that no cpus are executing guest code.

   The alternative is to map target atomic ops onto host equivalents,

   which requires quite a lot of per host/target work.  */

static pthread_mutex_t cpu_list_mutex = PTHREAD_MUTEX_INITIALIZER;

static pthread_mutex_t exclusive_lock = PTHREAD_MUTEX_INITIALIZER;

static pthread_cond_t exclusive_cond = PTHREAD_COND_INITIALIZER;

static pthread_cond_t exclusive_resume = PTHREAD_COND_INITIALIZER;

static int pending_cpus;

/* Make sure everything is in a consistent state for calling fork().  */

void fork_start(void)

{

    pthread_mutex_lock(&tcg_ctx.tb_ctx.tb_lock);

    pthread_mutex_lock(&exclusive_lock);

    mmap_fork_start();

}

void fork_end(int child)

{

    mmap_fork_end(child);

    if (child) {

        CPUState *cpu, *next_cpu;

        /* Child processes created by fork() only have a single thread.

           Discard information about the parent threads.  */

        CPU_FOREACH_SAFE(cpu, next_cpu) {

            if (cpu != thread_cpu) {

                QTAILQ_REMOVE(&cpus, thread_cpu, node);

            }

        }

        pending_cpus = 0;

        pthread_mutex_init(&exclusive_lock, NULL);

        pthread_mutex_init(&cpu_list_mutex, NULL);

        pthread_cond_init(&exclusive_cond, NULL);

        pthread_cond_init(&exclusive_resume, NULL);

        pthread_mutex_init(&tcg_ctx.tb_ctx.tb_lock, NULL);

        gdbserver_fork((CPUArchState *)thread_cpu->env_ptr);

    } else {

        pthread_mutex_unlock(&exclusive_lock);

        pthread_mutex_unlock(&tcg_ctx.tb_ctx.tb_lock);

    }

}

/* Wait for pending exclusive operations to complete.  The exclusive lock

   must be held.  */

static inline void exclusive_idle(void)

{

    while (pending_cpus) {

        pthread_cond_wait(&exclusive_resume, &exclusive_lock);

    }

}

/* Start an exclusive operation.

   Must only be called from outside cpu_arm_exec.   */

static inline void start_exclusive(void)

{

    CPUState *other_cpu;

    pthread_mutex_lock(&exclusive_lock);

    exclusive_idle();

    pending_cpus = 1;

    /* Make all other cpus stop executing.  */

    CPU_FOREACH(other_cpu) {

        if (other_cpu->running) {

            pending_cpus++;

            cpu_exit(other_cpu);

        }

    }

    if (pending_cpus > 1) {

        pthread_cond_wait(&exclusive_cond, &exclusive_lock);

    }

}

/* Finish an exclusive operation.  */

static inline void end_exclusive(void)

{

    pending_cpus = 0;

    pthread_cond_broadcast(&exclusive_resume);

    pthread_mutex_unlock(&exclusive_lock);

}

/* Wait for exclusive ops to finish, and begin cpu execution.  */

static inline void cpu_exec_start(CPUState *cpu)

{

    pthread_mutex_lock(&exclusive_lock);

    exclusive_idle();

    cpu->running = true;

    pthread_mutex_unlock(&exclusive_lock);

}

/* Mark cpu as not executing, and release pending exclusive ops.  */

static inline void cpu_exec_end(CPUState *cpu)

{

    pthread_mutex_lock(&exclusive_lock);

    cpu->running = false;

    if (pending_cpus > 1) {

        pending_cpus--;

        if (pending_cpus == 1) {

            pthread_cond_signal(&exclusive_cond);

        }

    }

    exclusive_idle();

    pthread_mutex_unlock(&exclusive_lock);

}

void cpu_list_lock(void)

{

    pthread_mutex_lock(&cpu_list_mutex);

}

void cpu_list_unlock(void)

{

    pthread_mutex_unlock(&cpu_list_mutex);

}

#ifdef TARGET_I386

/***********************************************************/

/* CPUX86 core interface */

void cpu_smm_update(CPUX86State *env)

{

}

uint64_t cpu_get_tsc(CPUX86State *env)

{

    return cpu_get_real_ticks();

}

static void write_dt(void *ptr, unsigned long addr, unsigned long limit,

                     int flags)

{

    unsigned int e1, e2;

    uint32_t *p;

    e1 = (addr << 16) | (limit & 0xffff);

    e2 = ((addr >> 16) & 0xff) | (addr & 0xff000000) | (limit & 0x000f0000);

    e2 |= flags;

    p = ptr;

    p[0] = tswap32(e1);

    p[1] = tswap32(e2);

}

static uint64_t *idt_table;

#ifdef TARGET_X86_64

static void set_gate64(void *ptr, unsigned int type, unsigned int dpl,

                       uint64_t addr, unsigned int sel)

{

    uint32_t *p, e1, e2;

    e1 = (addr & 0xffff) | (sel << 16);

    e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);

    p = ptr;

    p[0] = tswap32(e1);

    p[1] = tswap32(e2);

    p[2] = tswap32(addr >> 32);

    p[3] = 0;

}

/* only dpl matters as we do only user space emulation */

static void set_idt(int n, unsigned int dpl)

{

    set_gate64(idt_table + n * 2, 0, dpl, 0, 0);

}

#else

static void set_gate(void *ptr, unsigned int type, unsigned int dpl,

                     uint32_t addr, unsigned int sel)

{

    uint32_t *p, e1, e2;

    e1 = (addr & 0xffff) | (sel << 16);

    e2 = (addr & 0xffff0000) | 0x8000 | (dpl << 13) | (type << 8);

    p = ptr;

    p[0] = tswap32(e1);

    p[1] = tswap32(e2);

}

/* only dpl matters as we do only user space emulation */

static void set_idt(int n, unsigned int dpl)

{

    set_gate(idt_table + n, 0, dpl, 0, 0);

}

#endif

void cpu_loop(CPUX86State *env)

{

    CPUState *cs = CPU(x86_env_get_cpu(env));

    int trapnr;

    abi_ulong pc;

    target_siginfo_t info;

    for(;;) {

        trapnr = cpu_x86_exec(env);

        switch(trapnr) {

        case 0x80:

            /* linux syscall from int $0x80 */

            env->regs[R_EAX] = do_syscall(env,

                                          env->regs[R_EAX],

                                          env->regs[R_EBX],

                                          env->regs[R_ECX],

                                          env->regs[R_EDX],

                                          env->regs[R_ESI],

                                          env->regs[R_EDI],

                                          env->regs[R_EBP],

                                          0, 0);

            break;

#ifndef TARGET_ABI32

        case EXCP_SYSCALL:

            /* linux syscall from syscall instruction */

            env->regs[R_EAX] = do_syscall(env,

                                          env->regs[R_EAX],

                                          env->regs[R_EDI],

                                          env->regs[R_ESI],

                                          env->regs[R_EDX],

                                          env->regs[10],

                                          env->regs[8],

                                          env->regs[9],

                                          0, 0);

            env->eip = env->exception_next_eip;

            break;

#endif

        case EXCP0B_NOSEG:

        case EXCP0C_STACK:

            info.si_signo = SIGBUS;

            info.si_errno = 0;

            info.si_code = TARGET_SI_KERNEL;

            info._sifields._sigfault._addr = 0;

            queue_signal(env, info.si_signo, &info);

            break;

        case EXCP0D_GPF:

            /* XXX: potential problem if ABI32 */

#ifndef TARGET_X86_64

            if (env->eflags & VM_MASK) {

                handle_vm86_fault(env);

            } else

#endif

            {

                info.si_signo = SIGSEGV;

                info.si_errno = 0;

                info.si_code = TARGET_SI_KERNEL;

                info._sifields._sigfault._addr = 0;

                queue_signal(env, info.si_signo, &info);

            }

            break;

        case EXCP0E_PAGE:

            info.si_signo = SIGSEGV;

            info.si_errno = 0;

            if (!(env->error_code & 1))

                info.si_code = TARGET_SEGV_MAPERR;

            else

                info.si_code = TARGET_SEGV_ACCERR;

            info._sifields._sigfault._addr = env->cr[2];

            queue_signal(env, info.si_signo, &info);

            break;

        case EXCP00_DIVZ:

#ifndef TARGET_X86_64

            if (env->eflags & VM_MASK) {

                handle_vm86_trap(env, trapnr);

            } else

#endif

            {

                /* division by zero */

                info.si_signo = SIGFPE;

                info.si_errno = 0;

                info.si_code = TARGET_FPE_INTDIV;

                info._sifields._sigfault._addr = env->eip;

                queue_signal(env, info.si_signo, &info);

            }

            break;

        case EXCP01_DB:

        case EXCP03_INT3:

#ifndef TARGET_X86_64

            if (env->eflags & VM_MASK) {

                handle_vm86_trap(env, trapnr);

            } else

#endif

            {

                info.si_signo = SIGTRAP;

                info.si_errno = 0;

                if (trapnr == EXCP01_DB) {

                    info.si_code = TARGET_TRAP_BRKPT;

                    info._sifields._sigfault._addr = env->eip;

                } else {

                    info.si_code = TARGET_SI_KERNEL;

                    info._sifields._sigfault._addr = 0;

                }

                queue_signal(env, info.si_signo, &info);

            }

            break;

        case EXCP04_INTO:

        case EXCP05_BOUND:

#ifndef TARGET_X86_64

            if (env->eflags & VM_MASK) {

                handle_vm86_trap(env, trapnr);

            } else

#endif

            {

                info.si_signo = SIGSEGV;

                info.si_errno = 0;

                info.si_code = TARGET_SI_KERNEL;

                info._sifields._sigfault._addr = 0;

                queue_signal(env, info.si_signo, &info);

            }

            break;

        case EXCP06_ILLOP:

            info.si_signo = SIGILL;

            info.si_errno = 0;

            info.si_code = TARGET_ILL_ILLOPN;

            info._sifields._sigfault._addr = env->eip;

            queue_signal(env, info.si_signo, &info);

            break;

        case EXCP_INTERRUPT:

            /* just indicate that signals should be handled asap */

            break;

        case EXCP_DEBUG:

            {

                int sig;

                sig = gdb_handlesig(cs, TARGET_SIGTRAP);

                if (sig)

                  {

                    info.si_signo = sig;

                    info.si_errno = 0;

                    info.si_code = TARGET_TRAP_BRKPT;

                    queue_signal(env, info.si_signo, &info);

                  }

            }

            break;

        default:

            pc = env->segs[R_CS].base + env->eip;

            fprintf(stderr, "qemu: 0x%08lx: unhandled CPU exception 0x%x - aborting\n",

                    (long)pc, trapnr);

            abort();

        }

        process_pending_signals(env);

    }

}

#endif

#ifdef TARGET_ARM

#define get_user_code_u32(x, gaddr, doswap)             \

    ({ abi_long __r = get_user_u32((x), (gaddr));       \

        if (!__r && (doswap)) {                         \

            (x) = bswap32(x);                           \

        }                                               \

        __r;                                            \

    })

#define get_user_code_u16(x, gaddr, doswap)             \

    ({ abi_long __r = get_user_u16((x), (gaddr));       \

        if (!__r && (doswap)) {                         \

            (x) = bswap16(x);                           \

        }                                               \

        __r;                                            \

    })

#ifdef TARGET_ABI32

/* Commpage handling -- there is no commpage for AArch64 */

/*

 * See the Linux kernel's Documentation/arm/kernel_user_helpers.txt

 * Input:

 * r0 = pointer to oldval

 * r1 = pointer to newval

 * r2 = pointer to target value

 *

 * Output:

 * r0 = 0 if *ptr was changed, non-0 if no exchange happened

 * C set if *ptr was changed, clear if no exchange happened

 *

 * Note segv's in kernel helpers are a bit tricky, we can set the

 * data address sensibly but the PC address is just the entry point.

 */

static void arm_kernel_cmpxchg64_helper(CPUARMState *env)

{

    uint64_t oldval, newval, val;

    uint32_t addr, cpsr;

    target_siginfo_t info;

    /* Based on the 32 bit code in do_kernel_trap */

    /* XXX: This only works between threads, not between processes.

       It's probably possible to implement this with native host

       operations. However things like ldrex/strex are much harder so

       there's not much point trying.  */

    start_exclusive();

    cpsr = cpsr_read(env);

    addr = env->regs[2];

    if (get_user_u64(oldval, env->regs[0])) {

        env->cp15.c6_data = env->regs[0];

        goto segv;

    };

    if (get_user_u64(newval, env->regs[1])) {

        env->cp15.c6_data = env->regs[1];

        goto segv;

    };

    if (get_user_u64(val, addr)) {

        env->cp15.c6_data = addr;

        goto segv;

    }

    if (val == oldval) {

        val = newval;

        if (put_user_u64(val, addr)) {

            env->cp15.c6_data = addr;

            goto segv;

        };

        env->regs[0] = 0;

        cpsr |= CPSR_C;

    } else {

        env->regs[0] = -1;

        cpsr &= ~CPSR_C;

    }

    cpsr_write(env, cpsr, CPSR_C);

    end_exclusive();

    return;

segv:

    end_exclusive();

    /* We get the PC of the entry address - which is as good as anything,

       on a real kernel what you get depends on which mode it uses. */

    info.si_signo = SIGSEGV;

    info.si_errno = 0;

    /* XXX: check env->error_code */

    info.si_code = TARGET_SEGV_MAPERR;

    info._sifields._sigfault._addr = env->cp15.c6_data;

    queue_signal(env, info.si_signo, &info);

    end_exclusive();

}

/* Handle a jump to the kernel code page.  */

static int

do_kernel_trap(CPUARMState *env)

{

    uint32_t addr;

    uint32_t cpsr;

    uint32_t val;

    switch (env->regs[15]) {

    case 0xffff0fa0: /* __kernel_memory_barrier */

        /* ??? No-op. Will need to do better for SMP.  */

        break;

    case 0xffff0fc0: /* __kernel_cmpxchg */

         /* XXX: This only works between threads, not between processes.

            It's probably possible to implement this with native host

            operations. However things like ldrex/strex are much harder so

            there's not much point trying.  */

        start_exclusive();

        cpsr = cpsr_read(env);

        addr = env->regs[2];

        /* FIXME: This should SEGV if the access fails.  */

        if (get_user_u32(val, addr))

            val = ~env->regs[0];

        if (val == env->regs[0]) {

            val = env->regs[1];

            /* FIXME: Check for segfaults.  */

            put_user_u32(val, addr);

            env->regs[0] = 0;

            cpsr |= CPSR_C;

        } else {

            env->regs[0] = -1;

            cpsr &= ~CPSR_C;

        }

        cpsr_write(env, cpsr, CPSR_C);

        end_exclusive();

        break;

    case 0xffff0fe0: /* __kernel_get_tls */

        env->regs[0] = env->cp15.c13_tls2;

        break;

    case 0xffff0f60: /* __kernel_cmpxchg64 */

        arm_kernel_cmpxchg64_helper(env);

        break;

    default:

        return 1;

    }

    /* Jump back to the caller.  */

    addr = env->regs[14];

    if (addr & 1) {

        env->thumb = 1;

        addr &= ~1;

    }

    env->regs[15] = addr;

    return 0;

}

#endif

static int do_strex(CPUARMState *env)

{

    uint32_t val;

    int size;

    int rc = 1;

    int segv = 0;

    uint32_t addr;

    start_exclusive();

    addr = env->exclusive_addr;

    if (addr != env->exclusive_test) {

        goto fail;

    }

    size = env->exclusive_info & 0xf;

    switch (size) {

    case 0:

        segv = get_user_u8(val, addr);

        break;

    case 1:

        segv = get_user_u16(val, addr);

        break;

    case 2:

    case 3:

        segv = get_user_u32(val, addr);

        break;

    default:

        abort();

    }

    if (segv) {

        env->cp15.c6_data = addr;

        goto done;

    }

    if (val != env->exclusive_val) {

        goto fail;

    }

    if (size == 3) {

        segv = get_user_u32(val, addr + 4);

        if (segv) {

            env->cp15.c6_data = addr + 4;

            goto done;

        }

        if (val != env->exclusive_high) {

            goto fail;

        }

    }

    val = env->regs[(env->exclusive_info >> 8) & 0xf];

    switch (size) {

    case 0:

        segv = put_user_u8(val, addr);

        break;

    case 1:

        segv = put_user_u16(val, addr);

        break;

    case 2:

    case 3:

        segv = put_user_u32(val, addr);

        break;

    }

    if (segv) {

        env->cp15.c6_data = addr;

        goto done;

    }

    if (size == 3) {

        val = env->regs[(env->exclusive_info >> 12) & 0xf];

        segv = put_user_u32(val, addr + 4);

        if (segv) {

            env->cp15.c6_data = addr + 4;

            goto done;

        }

    }

    rc = 0;

fail:

    env->regs[15] += 4;

    env->regs[(env->exclusive_info >> 4) & 0xf] = rc;

done:

    end_exclusive();

    return segv;

}

#ifdef TARGET_ABI32

void cpu_loop(CPUARMState *env)

{

    CPUState *cs = CPU(arm_env_get_cpu(env));

    int trapnr;

    unsigned int n, insn;

    target_siginfo_t info;

    uint32_t addr;

    for(;;) {

        cpu_exec_start(cs);

        trapnr = cpu_arm_exec(env);

        cpu_exec_end(cs);

        switch(trapnr) {

        case EXCP_UDEF:

            {

                TaskState *ts = env->opaque;

                uint32_t opcode;

                int rc;

                /* we handle the FPU emulation here, as Linux */

                /* we get the opcode */

                /* FIXME - what to do if get_user() fails? */

                get_user_code_u32(opcode, env->regs[15], env->bswap_code);

                rc = EmulateAll(opcode, &ts->fpa, env);

                if (rc == 0) { /* illegal instruction */

                    info.si_signo = SIGILL;

                    info.si_errno = 0;

                    info.si_code = TARGET_ILL_ILLOPN;

                    info._sifields._sigfault._addr = env->regs[15];

                    queue_signal(env, info.si_signo, &info);

                } else if (rc < 0) { /* FP exception */

                    int arm_fpe=0;

                    /* translate softfloat flags to FPSR flags */

                    if (-rc & float_flag_invalid)

                      arm_fpe |= BIT_IOC;

                    if (-rc & float_flag_divbyzero)

                      arm_fpe |= BIT_DZC;

                    if (-rc & float_flag_overflow)

                      arm_fpe |= BIT_OFC;

                    if (-rc & float_flag_underflow)

                      arm_fpe |= BIT_UFC;

                    if (-rc & float_flag_inexact)

                      arm_fpe |= BIT_IXC;

                    FPSR fpsr = ts->fpa.fpsr;

                    //printf("fpsr 0x%x, arm_fpe 0x%x\n",fpsr,arm_fpe);

                    if (fpsr & (arm_fpe << 16)) { /* exception enabled? */

                      info.si_signo = SIGFPE;

                      info.si_errno = 0;

                      /* ordered by priority, least first */

                      if (arm_fpe & BIT_IXC) info.si_code = TARGET_FPE_FLTRES;

                      if (arm_fpe & BIT_UFC) info.si_code = TARGET_FPE_FLTUND;

                      if (arm_fpe & BIT_OFC) info.si_code = TARGET_FPE_FLTOVF;

                      if (arm_fpe & BIT_DZC) info.si_code = TARGET_FPE_FLTDIV;

                      if (arm_fpe & BIT_IOC) info.si_code = TARGET_FPE_FLTINV;

                      info._sifields._sigfault._addr = env->regs[15];

                      queue_signal(env, info.si_signo, &info);

                    } else {

                      env->regs[15] += 4;

                    }

                    /* accumulate unenabled exceptions */

                    if ((!(fpsr & BIT_IXE)) && (arm_fpe & BIT_IXC))

                      fpsr |= BIT_IXC;

                    if ((!(fpsr & BIT_UFE)) && (arm_fpe & BIT_UFC))

                      fpsr |= BIT_UFC;

                    if ((!(fpsr & BIT_OFE)) && (arm_fpe & BIT_OFC))

                      fpsr |= BIT_OFC;

                    if ((!(fpsr & BIT_DZE)) && (arm_fpe & BIT_DZC))

                      fpsr |= BIT_DZC;

                    if ((!(fpsr & BIT_IOE)) && (arm_fpe & BIT_IOC))

                      fpsr |= BIT_IOC;

                    ts->fpa.fpsr=fpsr;

                } else { /* everything OK */

                    /* increment PC */

                    env->regs[15] += 4;

                }

            }

            break;

        case EXCP_SWI:

        case EXCP_BKPT:

            {

                env->eabi = 1;

                /* system call */

                if (trapnr == EXCP_BKPT) {

                    if (env->thumb) {

                        /* FIXME - what to do if get_user() fails? */

                        get_user_code_u16(insn, env->regs[15], env->bswap_code);

                        n = insn & 0xff;

                        env->regs[15] += 2;

                    } else {

                        /* FIXME - what to do if get_user() fails? */

                        get_user_code_u32(insn, env->regs[15], env->bswap_code);

                        n = (insn & 0xf) | ((insn >> 4) & 0xff0);

                        env->regs[15] += 4;

                    }

                } else {

                    if (env->thumb) {

                        /* FIXME - what to do if get_user() fails? */

                        get_user_code_u16(insn, env->regs[15] - 2,

                                          env->bswap_code);

                        n = insn & 0xff;

                    } else {

                        /* FIXME - what to do if get_user() fails? */

                        get_user_code_u32(insn, env->regs[15] - 4,

                                          env->bswap_code);

                        n = insn & 0xffffff;

                    }

                }

                if (n == ARM_NR_cacheflush) {

                    /* nop */

                } else if (n == ARM_NR_semihosting

                           || n == ARM_NR_thumb_semihosting) {

                    env->regs[0] = do_arm_semihosting (env);

                } else if (n == 0 || n >= ARM_SYSCALL_BASE || env->thumb) {

                    /* linux syscall */

                    if (env->thumb || n == 0) {

                        n = env->regs[7];

                    } else {

                        n -= ARM_SYSCALL_BASE;

                        env->eabi = 0;

                    }

                    if ( n > ARM_NR_BASE) {

                        switch (n) {

                        case ARM_NR_cacheflush:

                            /* nop */

                            break;

                        case ARM_NR_set_tls:

                            cpu_set_tls(env, env->regs[0]);

                            env->regs[0] = 0;

                            break;

                        default:

                            gemu_log("qemu: Unsupported ARM syscall: 0x%x\n",

                                     n);

                            env->regs[0] = -TARGET_ENOSYS;

                            break;

                        }

                    } else {

                        env->regs[0] = do_syscall(env,

                                                  n,

                                                  env->regs[0],

                                                  env->regs[1],

                                                  env->regs[2],

                                                  env->regs[3],

                                                  env->regs[4],

                                                  env->regs[5],

                                                  0, 0);

                    }

                } else {

                    goto error;

                }

            }

            break;

        case EXCP_INTERRUPT:

            /* just indicate that signals should be handled asap */

            break;

        case EXCP_PREFETCH_ABORT:

            addr = env->cp15.c6_insn;

            goto do_segv;

        case EXCP_DATA_ABORT:

            addr = env->cp15.c6_data;

        do_segv:

            {

                info.si_signo = SIGSEGV;

                info.si_errno = 0;

                /* XXX: check env->error_code */

                info.si_code = TARGET_SEGV_MAPERR;

                info._sifields._sigfault._addr = addr;

                queue_signal(env, info.si_signo, &info);

            }

            break;

        case EXCP_DEBUG:

            {

                int sig;

                sig = gdb_handlesig(cs, TARGET_SIGTRAP);

                if (sig)

                  {

                    info.si_signo = sig;

                    info.si_errno = 0;

                    info.si_code = TARGET_TRAP_BRKPT;

                    queue_signal(env, info.si_signo, &info);

                  }

            }

            break;

        case EXCP_KERNEL_TRAP:

            if (do_kernel_trap(env))

              goto error;

            break;

        case EXCP_STREX:

            if (do_strex(env)) {

                addr = env->cp15.c6_data;

                goto do_segv;

            }

            break;

        default:

        error:

            fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n",

                    trapnr);

            cpu_dump_state(cs, stderr, fprintf, 0);

            abort();

        }

        process_pending_signals(env);

    }

}

#else

/* AArch64 main loop */

void cpu_loop(CPUARMState *env)

{

    CPUState *cs = CPU(arm_env_get_cpu(env));

    int trapnr, sig;

    target_siginfo_t info;

    uint32_t addr;

    for (;;) {

        cpu_exec_start(cs);

        trapnr = cpu_arm_exec(env);

        cpu_exec_end(cs);

        switch (trapnr) {

        case EXCP_SWI:

            env->xregs[0] = do_syscall(env,

                                       env->xregs[8],

                                       env->xregs[0],

                                       env->xregs[1],

                                       env->xregs[2],