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Sparc64: replace tsptr with helper routine
tl and tsptr of members sparc64 cpu state must be changedsimultaneously to keep trap state window in sync with currenttrap level. Currently translation of store to tl does not changetsptr, which leads to corrupt trap state on corresponding...
sparc64 really implement itlb/dtlb automatic replacement writes
- implement "used" bit in tlb translation entry- mark tlb entry used if qemu code/data translation succeeds- fold i/d mmu replacement writes code into replace_tlb_1bit_lru whichadds 1bit lru replacement algorithm; previously code tried to replace...
sparc64 name mmu registers and general cleanup
- add names to mmu registers, this helps understanding the code whichuses/modifies them.- fold i/d mmu tlb entries tag and tte arrays into arrays of tlb entries- extract demap_tlb routine (code duplication)...
Fix most warnings (errors with -Werror) when debugging is enabled
I used the following command to enable debugging:perl -p -i -e 's/^\/\/#define DEBUG/#define DEBUG/g' * /* *//*
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Update to a hopefully more future proof FSF address
sparc64: trap handling corrections
On Sun, Jul 12, 2009 at 12:09 PM, Blue Swirl<blauwirbel@gmail.com> wrote:
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote: Good trap handling is required to process interrupts. This patch fixes the following:...
On 7/12/09, Igor Kovalenko <igor.v.kovalenko@gmail.com> wrote:
Good trap handling is required to process interrupts. This patch fixes the following:...
sparc64: mmu bypass mode correction
This Implement physical address truncation in mmu bypass mode.IMMU bypass is also active when cpu enters RED_STATE
Signed-off-by: igor.v.kovalenko@gmail.com
--Kind regards,Igor V. Kovalenko
sparc64: unify mmu tag matching code
This patch extracts common part of sparc64 tagmatching code used by IMMU and DMMU lookups.
Include assert.h from qemu-common.h
Include assert.h from qemu-common.h and remove other direct uses.cpu-all.h still need to include it because of the dyngen-exec.h hacks
Signed-off-by: Paul Brook <paul@codesourcery.com>
Use dynamical computation for condition codes
Clarify: dmmuregs1 is not a typo
sparc64 fix context value for ITLB fault
Revert previous change to get_physical_address_code:I/D MMU context register is shared, so using dmmuregs1 is correct
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
sparc64 fix TLB match code
TLB match code must respect page size, otherwise 4M page mappings maybe not found.
Also correct a typo in get_physical_address_code which should use IMMUregisters.
Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>...
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
Delete some unused macros detected with -Wp,-Wunused-macros use
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6856 c046a42c-6fe2-441c-8c8c-71466251a162
Turn MMUs and caches off on reset
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6636 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
Log reset events (Jan Kiszka)
Original idea&code by Kevin Wolf, split-up in two patches and added morearchs.
This patch introduces a flag to log CPU resets. Useful for tracingunexpected resets (such as those triggered by x86 triple faults).
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Get rid of user_mode_only
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6305 c046a42c-6fe2-441c-8c8c-71466251a162
Fix TLB access (Jakub Jermar)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6274 c046a42c-6fe2-441c-8c8c-71466251a162
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
Better SuperSPARC emulation (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6123 c046a42c-6fe2-441c-8c8c-71466251a162
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
Add static (spotted by sparse)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5439 c046a42c-6fe2-441c-8c8c-71466251a162
Rearrange tick functions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5408 c046a42c-6fe2-441c-8c8c-71466251a162
Add a generic Niagara machine
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5329 c046a42c-6fe2-441c-8c8c-71466251a162
Move also DEBUG_PCALL (see r5085)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5326 c046a42c-6fe2-441c-8c8c-71466251a162
Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5185 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc64 boot on i386 host: - move do_interrupt() back to op_helper.c - move non-helper prototypes from helper.h to exec.h - move some prototypes from cpu.h to exec.h - do not export either set_cwp() or cpu_set_cwp() from op_helper.c, but instead provide inline functions...
Use initial CPU definition structure for some CPU fields instead of copyingthem around, based on patch by Luis Pureza.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5042 c046a42c-6fe2-441c-8c8c-71466251a162
Make MAXTL dynamic, bounds check tl when indexing
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4942 c046a42c-6fe2-441c-8c8c-71466251a162
Add T1 and T2 CPUs, add a Sun4v machine
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4923 c046a42c-6fe2-441c-8c8c-71466251a162
Use MMU globals for some MMU traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4918 c046a42c-6fe2-441c-8c8c-71466251a162
Fix reset vector
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4917 c046a42c-6fe2-441c-8c8c-71466251a162
Print default and available CPU features separately
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4912 c046a42c-6fe2-441c-8c8c-71466251a162
Make UA200x features selectable, add MMU types
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4911 c046a42c-6fe2-441c-8c8c-71466251a162
Update TLB miss addresses
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4897 c046a42c-6fe2-441c-8c8c-71466251a162
Fix saving and loading of trap state
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4883 c046a42c-6fe2-441c-8c8c-71466251a162
Fix MMU miss traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4880 c046a42c-6fe2-441c-8c8c-71466251a162
Fix bogus format, reading uninitialised memory (original patch by Julian Seward)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4793 c046a42c-6fe2-441c-8c8c-71466251a162
Fix Sparc mmu bug seen with NetBSD, based on patch by Cliff Wright
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4785 c046a42c-6fe2-441c-8c8c-71466251a162
Allow NWINDOWS selection (CPU feature with model specific defaults)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4690 c046a42c-6fe2-441c-8c8c-71466251a162
Add more SuperSparcs
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4633 c046a42c-6fe2-441c-8c8c-71466251a162
MicroSparc I didn't have fsmuld op
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4618 c046a42c-6fe2-441c-8c8c-71466251a162
Move non-op functions from op_helper.c to helper.c and vice versa.Rearrange interrupt handling to match other targets.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4590 c046a42c-6fe2-441c-8c8c-71466251a162
Wrap long lines
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4440 c046a42c-6fe2-441c-8c8c-71466251a162
Fix compiler warnings
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4404 c046a42c-6fe2-441c-8c8c-71466251a162
CPU feature selection support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4399 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
Move CPU stuff unrelated to translation to helper.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4133 c046a42c-6fe2-441c-8c8c-71466251a162
Convert tick operations to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4011 c046a42c-6fe2-441c-8c8c-71466251a162
Sparc32 MMU register fixes (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3979 c046a42c-6fe2-441c-8c8c-71466251a162
Enforce context table alignment
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3857 c046a42c-6fe2-441c-8c8c-71466251a162
Increase prom size for boot mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3748 c046a42c-6fe2-441c-8c8c-71466251a162
Use slavio base as boot prom address, rearrange sun4m init code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3747 c046a42c-6fe2-441c-8c8c-71466251a162
Break up vl.h.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3674 c046a42c-6fe2-441c-8c8c-71466251a162
CPU specific boot mode (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3542 c046a42c-6fe2-441c-8c8c-71466251a162
Replace is_user variable with mmu_idx in softmmu core, allowing support of more than 2 mmu access modes.Add backward compatibility is_user variable in targets code when needed.Implement per target cpu_mmu_index function, avoiding duplicated code and #ifdef TARGET_xxx in softmmu core functions....
CPU boot mode
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3231 c046a42c-6fe2-441c-8c8c-71466251a162
Detabify
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3195 c046a42c-6fe2-441c-8c8c-71466251a162
find -type f | xargs sed -i 's/[\t ]$//g' # on most files
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
Use full 36-bit physical address space on SS10
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2830 c046a42c-6fe2-441c-8c8c-71466251a162
C99 64 bit printf
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2018 c046a42c-6fe2-441c-8c8c-71466251a162
MMU no fault fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1961 c046a42c-6fe2-441c-8c8c-71466251a162
PAGE_EXEC support (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1692 c046a42c-6fe2-441c-8c8c-71466251a162
sparc merge (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1620 c046a42c-6fe2-441c-8c8c-71466251a162
avoid using physical accesses in user emulation
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1592 c046a42c-6fe2-441c-8c8c-71466251a162
sparc64 fixes (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1514 c046a42c-6fe2-441c-8c8c-71466251a162
correct split between helper.c and op_helper.c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1506 c046a42c-6fe2-441c-8c8c-71466251a162
sparc64 marge (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1462 c046a42c-6fe2-441c-8c8c-71466251a162
MMU fix (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1390 c046a42c-6fe2-441c-8c8c-71466251a162
sparc exception fix (we go up to the shell prompt)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1343 c046a42c-6fe2-441c-8c8c-71466251a162
sparc fixes (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1326 c046a42c-6fe2-441c-8c8c-71466251a162
MMU fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1308 c046a42c-6fe2-441c-8c8c-71466251a162
sparc fix
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1294 c046a42c-6fe2-441c-8c8c-71466251a162
sparc fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1291 c046a42c-6fe2-441c-8c8c-71466251a162
clean up - comments
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1271 c046a42c-6fe2-441c-8c8c-71466251a162
initial sparc64 support - sparc fixes (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1251 c046a42c-6fe2-441c-8c8c-71466251a162
endianness fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1250 c046a42c-6fe2-441c-8c8c-71466251a162
64 bit target support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1195 c046a42c-6fe2-441c-8c8c-71466251a162
SPARC merge
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1179 c046a42c-6fe2-441c-8c8c-71466251a162
monitor fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1110 c046a42c-6fe2-441c-8c8c-71466251a162
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1098 c046a42c-6fe2-441c-8c8c-71466251a162
removed access_type hack
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1095 c046a42c-6fe2-441c-8c8c-71466251a162
full system SPARC emulation (Blue Swirl)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1083 c046a42c-6fe2-441c-8c8c-71466251a162