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1 | a541f297 | bellard | /*
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2 | e9df014c | j_mayer | * QEMU generic PowerPC hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
30 | ca20cf32 | Blue Swirl | #include "loader.h" |
31 | fc87e185 | Alexander Graf | #include "kvm.h" |
32 | fc87e185 | Alexander Graf | #include "kvm_ppc.h" |
33 | a541f297 | bellard | |
34 | e9df014c | j_mayer | //#define PPC_DEBUG_IRQ
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35 | 4b6d0a4c | j_mayer | //#define PPC_DEBUG_TB
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36 | e9df014c | j_mayer | |
37 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_IRQ
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38 | 93fcfe39 | aliguori | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
39 | d12d51d5 | aliguori | #else
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40 | d12d51d5 | aliguori | # define LOG_IRQ(...) do { } while (0) |
41 | d12d51d5 | aliguori | #endif
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42 | d12d51d5 | aliguori | |
43 | d12d51d5 | aliguori | |
44 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_TB
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45 | 93fcfe39 | aliguori | # define LOG_TB(...) qemu_log(__VA_ARGS__)
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46 | d12d51d5 | aliguori | #else
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47 | d12d51d5 | aliguori | # define LOG_TB(...) do { } while (0) |
48 | d12d51d5 | aliguori | #endif
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49 | d12d51d5 | aliguori | |
50 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env); |
51 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env); |
52 | dbdd2506 | j_mayer | |
53 | ddd1055b | Fabien Chouteau | void ppc_set_irq(CPUState *env, int n_IRQ, int level) |
54 | 47103572 | j_mayer | { |
55 | fc87e185 | Alexander Graf | unsigned int old_pending = env->pending_interrupts; |
56 | fc87e185 | Alexander Graf | |
57 | 47103572 | j_mayer | if (level) {
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58 | 47103572 | j_mayer | env->pending_interrupts |= 1 << n_IRQ;
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59 | 47103572 | j_mayer | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
60 | 47103572 | j_mayer | } else {
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61 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << n_IRQ);
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62 | 47103572 | j_mayer | if (env->pending_interrupts == 0) |
63 | 47103572 | j_mayer | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
64 | 47103572 | j_mayer | } |
65 | fc87e185 | Alexander Graf | |
66 | fc87e185 | Alexander Graf | if (old_pending != env->pending_interrupts) {
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67 | fc87e185 | Alexander Graf | #ifdef CONFIG_KVM
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68 | fc87e185 | Alexander Graf | kvmppc_set_interrupt(env, n_IRQ, level); |
69 | fc87e185 | Alexander Graf | #endif
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70 | fc87e185 | Alexander Graf | } |
71 | fc87e185 | Alexander Graf | |
72 | d12d51d5 | aliguori | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
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73 | aae9366a | j_mayer | "req %08x\n", __func__, env, n_IRQ, level,
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74 | a496775f | j_mayer | env->pending_interrupts, env->interrupt_request); |
75 | 47103572 | j_mayer | } |
76 | 47103572 | j_mayer | |
77 | e9df014c | j_mayer | /* PowerPC 6xx / 7xx internal IRQ controller */
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78 | e9df014c | j_mayer | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
79 | d537cf6c | pbrook | { |
80 | e9df014c | j_mayer | CPUState *env = opaque; |
81 | e9df014c | j_mayer | int cur_level;
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82 | d537cf6c | pbrook | |
83 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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84 | a496775f | j_mayer | env, pin, level); |
85 | e9df014c | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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86 | e9df014c | j_mayer | /* Don't generate spurious events */
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87 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
88 | e9df014c | j_mayer | switch (pin) {
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89 | dbdd2506 | j_mayer | case PPC6xx_INPUT_TBEN:
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90 | dbdd2506 | j_mayer | /* Level sensitive - active high */
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91 | d12d51d5 | aliguori | LOG_IRQ("%s: %s the time base\n",
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92 | dbdd2506 | j_mayer | __func__, level ? "start" : "stop"); |
93 | dbdd2506 | j_mayer | if (level) {
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94 | dbdd2506 | j_mayer | cpu_ppc_tb_start(env); |
95 | dbdd2506 | j_mayer | } else {
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96 | dbdd2506 | j_mayer | cpu_ppc_tb_stop(env); |
97 | dbdd2506 | j_mayer | } |
98 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_INT:
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99 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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100 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
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101 | a496775f | j_mayer | __func__, level); |
102 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
103 | e9df014c | j_mayer | break;
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104 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SMI:
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105 | e9df014c | j_mayer | /* Level sensitive - active high */
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106 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n",
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107 | a496775f | j_mayer | __func__, level); |
108 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
109 | e9df014c | j_mayer | break;
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110 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_MCP:
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111 | e9df014c | j_mayer | /* Negative edge sensitive */
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112 | e9df014c | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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113 | e9df014c | j_mayer | * 603/604/740/750: check HID0[EMCP]
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114 | e9df014c | j_mayer | */
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115 | e9df014c | j_mayer | if (cur_level == 1 && level == 0) { |
116 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
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117 | a496775f | j_mayer | __func__); |
118 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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119 | e9df014c | j_mayer | } |
120 | e9df014c | j_mayer | break;
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121 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_CKSTP_IN:
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122 | e9df014c | j_mayer | /* Level sensitive - active low */
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123 | e9df014c | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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124 | e63ecc6f | j_mayer | /* XXX: Note that the only way to restart the CPU is to reset it */
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125 | e9df014c | j_mayer | if (level) {
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126 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
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127 | e9df014c | j_mayer | env->halted = 1;
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128 | e9df014c | j_mayer | } |
129 | e9df014c | j_mayer | break;
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130 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_HRESET:
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131 | e9df014c | j_mayer | /* Level sensitive - active low */
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132 | e9df014c | j_mayer | if (level) {
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133 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
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134 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
135 | ef397e88 | j_mayer | /* XXX: TOFIX */
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136 | ef397e88 | j_mayer | #if 0
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137 | d84bda46 | Blue Swirl | cpu_reset(env);
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138 | ef397e88 | j_mayer | #else
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139 | ef397e88 | j_mayer | qemu_system_reset_request(); |
140 | e9df014c | j_mayer | #endif
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141 | e9df014c | j_mayer | } |
142 | e9df014c | j_mayer | break;
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143 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SRESET:
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144 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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145 | a496775f | j_mayer | __func__, level); |
146 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
147 | e9df014c | j_mayer | break;
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148 | e9df014c | j_mayer | default:
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149 | e9df014c | j_mayer | /* Unknown pin - do nothing */
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150 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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151 | e9df014c | j_mayer | return;
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152 | e9df014c | j_mayer | } |
153 | e9df014c | j_mayer | if (level)
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154 | e9df014c | j_mayer | env->irq_input_state |= 1 << pin;
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155 | e9df014c | j_mayer | else
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156 | e9df014c | j_mayer | env->irq_input_state &= ~(1 << pin);
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157 | d537cf6c | pbrook | } |
158 | d537cf6c | pbrook | } |
159 | d537cf6c | pbrook | |
160 | e9df014c | j_mayer | void ppc6xx_irq_init (CPUState *env)
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161 | 47103572 | j_mayer | { |
162 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
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163 | 7b62a955 | j_mayer | PPC6xx_INPUT_NB); |
164 | 47103572 | j_mayer | } |
165 | 47103572 | j_mayer | |
166 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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167 | d0dfae6e | j_mayer | /* PowerPC 970 internal IRQ controller */
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168 | d0dfae6e | j_mayer | static void ppc970_set_irq (void *opaque, int pin, int level) |
169 | d0dfae6e | j_mayer | { |
170 | d0dfae6e | j_mayer | CPUState *env = opaque; |
171 | d0dfae6e | j_mayer | int cur_level;
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172 | d0dfae6e | j_mayer | |
173 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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174 | d0dfae6e | j_mayer | env, pin, level); |
175 | d0dfae6e | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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176 | d0dfae6e | j_mayer | /* Don't generate spurious events */
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177 | d0dfae6e | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
178 | d0dfae6e | j_mayer | switch (pin) {
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179 | d0dfae6e | j_mayer | case PPC970_INPUT_INT:
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180 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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181 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
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182 | d0dfae6e | j_mayer | __func__, level); |
183 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
184 | d0dfae6e | j_mayer | break;
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185 | d0dfae6e | j_mayer | case PPC970_INPUT_THINT:
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186 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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187 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
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188 | d0dfae6e | j_mayer | level); |
189 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
190 | d0dfae6e | j_mayer | break;
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191 | d0dfae6e | j_mayer | case PPC970_INPUT_MCP:
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192 | d0dfae6e | j_mayer | /* Negative edge sensitive */
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193 | d0dfae6e | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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194 | d0dfae6e | j_mayer | * 603/604/740/750: check HID0[EMCP]
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195 | d0dfae6e | j_mayer | */
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196 | d0dfae6e | j_mayer | if (cur_level == 1 && level == 0) { |
197 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
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198 | d0dfae6e | j_mayer | __func__); |
199 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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200 | d0dfae6e | j_mayer | } |
201 | d0dfae6e | j_mayer | break;
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202 | d0dfae6e | j_mayer | case PPC970_INPUT_CKSTP:
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203 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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204 | d0dfae6e | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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205 | d0dfae6e | j_mayer | if (level) {
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206 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
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207 | d0dfae6e | j_mayer | env->halted = 1;
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208 | d0dfae6e | j_mayer | } else {
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209 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
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210 | d0dfae6e | j_mayer | env->halted = 0;
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211 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
212 | d0dfae6e | j_mayer | } |
213 | d0dfae6e | j_mayer | break;
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214 | d0dfae6e | j_mayer | case PPC970_INPUT_HRESET:
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215 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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216 | d0dfae6e | j_mayer | if (level) {
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217 | d0dfae6e | j_mayer | #if 0 // XXX: TOFIX
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218 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
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219 | d0dfae6e | j_mayer | cpu_reset(env);
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220 | d0dfae6e | j_mayer | #endif
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221 | d0dfae6e | j_mayer | } |
222 | d0dfae6e | j_mayer | break;
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223 | d0dfae6e | j_mayer | case PPC970_INPUT_SRESET:
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224 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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225 | d0dfae6e | j_mayer | __func__, level); |
226 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
227 | d0dfae6e | j_mayer | break;
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228 | d0dfae6e | j_mayer | case PPC970_INPUT_TBEN:
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229 | d12d51d5 | aliguori | LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
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230 | d0dfae6e | j_mayer | level); |
231 | d0dfae6e | j_mayer | /* XXX: TODO */
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232 | d0dfae6e | j_mayer | break;
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233 | d0dfae6e | j_mayer | default:
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234 | d0dfae6e | j_mayer | /* Unknown pin - do nothing */
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235 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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236 | d0dfae6e | j_mayer | return;
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237 | d0dfae6e | j_mayer | } |
238 | d0dfae6e | j_mayer | if (level)
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239 | d0dfae6e | j_mayer | env->irq_input_state |= 1 << pin;
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240 | d0dfae6e | j_mayer | else
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241 | d0dfae6e | j_mayer | env->irq_input_state &= ~(1 << pin);
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242 | d0dfae6e | j_mayer | } |
243 | d0dfae6e | j_mayer | } |
244 | d0dfae6e | j_mayer | |
245 | d0dfae6e | j_mayer | void ppc970_irq_init (CPUState *env)
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246 | d0dfae6e | j_mayer | { |
247 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
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248 | 7b62a955 | j_mayer | PPC970_INPUT_NB); |
249 | d0dfae6e | j_mayer | } |
250 | 9d52e907 | David Gibson | |
251 | 9d52e907 | David Gibson | /* POWER7 internal IRQ controller */
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252 | 9d52e907 | David Gibson | static void power7_set_irq (void *opaque, int pin, int level) |
253 | 9d52e907 | David Gibson | { |
254 | 9d52e907 | David Gibson | CPUState *env = opaque; |
255 | 9d52e907 | David Gibson | |
256 | 9d52e907 | David Gibson | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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257 | 9d52e907 | David Gibson | env, pin, level); |
258 | 9d52e907 | David Gibson | |
259 | 9d52e907 | David Gibson | switch (pin) {
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260 | 9d52e907 | David Gibson | case POWER7_INPUT_INT:
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261 | 9d52e907 | David Gibson | /* Level sensitive - active high */
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262 | 9d52e907 | David Gibson | LOG_IRQ("%s: set the external IRQ state to %d\n",
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263 | 9d52e907 | David Gibson | __func__, level); |
264 | 9d52e907 | David Gibson | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
265 | 9d52e907 | David Gibson | break;
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266 | 9d52e907 | David Gibson | default:
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267 | 9d52e907 | David Gibson | /* Unknown pin - do nothing */
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268 | 9d52e907 | David Gibson | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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269 | 9d52e907 | David Gibson | return;
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270 | 9d52e907 | David Gibson | } |
271 | 9d52e907 | David Gibson | if (level) {
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272 | 9d52e907 | David Gibson | env->irq_input_state |= 1 << pin;
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273 | 9d52e907 | David Gibson | } else {
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274 | 9d52e907 | David Gibson | env->irq_input_state &= ~(1 << pin);
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275 | 9d52e907 | David Gibson | } |
276 | 9d52e907 | David Gibson | } |
277 | 9d52e907 | David Gibson | |
278 | 9d52e907 | David Gibson | void ppcPOWER7_irq_init (CPUState *env)
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279 | 9d52e907 | David Gibson | { |
280 | 9d52e907 | David Gibson | env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env,
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281 | 9d52e907 | David Gibson | POWER7_INPUT_NB); |
282 | 9d52e907 | David Gibson | } |
283 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
284 | d0dfae6e | j_mayer | |
285 | 4e290a0b | j_mayer | /* PowerPC 40x internal IRQ controller */
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286 | 4e290a0b | j_mayer | static void ppc40x_set_irq (void *opaque, int pin, int level) |
287 | 24be5ae3 | j_mayer | { |
288 | 24be5ae3 | j_mayer | CPUState *env = opaque; |
289 | 24be5ae3 | j_mayer | int cur_level;
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290 | 24be5ae3 | j_mayer | |
291 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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292 | 8ecc7913 | j_mayer | env, pin, level); |
293 | 24be5ae3 | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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294 | 24be5ae3 | j_mayer | /* Don't generate spurious events */
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295 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
296 | 24be5ae3 | j_mayer | switch (pin) {
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297 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_SYS:
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298 | 8ecc7913 | j_mayer | if (level) {
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299 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC system\n",
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300 | 8ecc7913 | j_mayer | __func__); |
301 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
302 | 8ecc7913 | j_mayer | } |
303 | 8ecc7913 | j_mayer | break;
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304 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CHIP:
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305 | 8ecc7913 | j_mayer | if (level) {
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306 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
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307 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
308 | 8ecc7913 | j_mayer | } |
309 | 8ecc7913 | j_mayer | break;
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310 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CORE:
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311 | 24be5ae3 | j_mayer | /* XXX: TODO: update DBSR[MRR] */
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312 | 24be5ae3 | j_mayer | if (level) {
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313 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
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314 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
315 | 24be5ae3 | j_mayer | } |
316 | 24be5ae3 | j_mayer | break;
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317 | 4e290a0b | j_mayer | case PPC40x_INPUT_CINT:
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318 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
319 | d12d51d5 | aliguori | LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
320 | 8ecc7913 | j_mayer | __func__, level); |
321 | 4e290a0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
322 | 24be5ae3 | j_mayer | break;
|
323 | 4e290a0b | j_mayer | case PPC40x_INPUT_INT:
|
324 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
325 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
|
326 | a496775f | j_mayer | __func__, level); |
327 | 24be5ae3 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
328 | 24be5ae3 | j_mayer | break;
|
329 | 4e290a0b | j_mayer | case PPC40x_INPUT_HALT:
|
330 | 24be5ae3 | j_mayer | /* Level sensitive - active low */
|
331 | 24be5ae3 | j_mayer | if (level) {
|
332 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
|
333 | 24be5ae3 | j_mayer | env->halted = 1;
|
334 | 24be5ae3 | j_mayer | } else {
|
335 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
|
336 | 24be5ae3 | j_mayer | env->halted = 0;
|
337 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
338 | 24be5ae3 | j_mayer | } |
339 | 24be5ae3 | j_mayer | break;
|
340 | 4e290a0b | j_mayer | case PPC40x_INPUT_DEBUG:
|
341 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
342 | d12d51d5 | aliguori | LOG_IRQ("%s: set the debug pin state to %d\n",
|
343 | a496775f | j_mayer | __func__, level); |
344 | a750fc0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
345 | 24be5ae3 | j_mayer | break;
|
346 | 24be5ae3 | j_mayer | default:
|
347 | 24be5ae3 | j_mayer | /* Unknown pin - do nothing */
|
348 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
349 | 24be5ae3 | j_mayer | return;
|
350 | 24be5ae3 | j_mayer | } |
351 | 24be5ae3 | j_mayer | if (level)
|
352 | 24be5ae3 | j_mayer | env->irq_input_state |= 1 << pin;
|
353 | 24be5ae3 | j_mayer | else
|
354 | 24be5ae3 | j_mayer | env->irq_input_state &= ~(1 << pin);
|
355 | 24be5ae3 | j_mayer | } |
356 | 24be5ae3 | j_mayer | } |
357 | 24be5ae3 | j_mayer | |
358 | 4e290a0b | j_mayer | void ppc40x_irq_init (CPUState *env)
|
359 | 24be5ae3 | j_mayer | { |
360 | 4e290a0b | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
|
361 | 4e290a0b | j_mayer | env, PPC40x_INPUT_NB); |
362 | 24be5ae3 | j_mayer | } |
363 | 24be5ae3 | j_mayer | |
364 | 9fdc60bf | aurel32 | /* PowerPC E500 internal IRQ controller */
|
365 | 9fdc60bf | aurel32 | static void ppce500_set_irq (void *opaque, int pin, int level) |
366 | 9fdc60bf | aurel32 | { |
367 | 9fdc60bf | aurel32 | CPUState *env = opaque; |
368 | 9fdc60bf | aurel32 | int cur_level;
|
369 | 9fdc60bf | aurel32 | |
370 | 9fdc60bf | aurel32 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
371 | 9fdc60bf | aurel32 | env, pin, level); |
372 | 9fdc60bf | aurel32 | cur_level = (env->irq_input_state >> pin) & 1;
|
373 | 9fdc60bf | aurel32 | /* Don't generate spurious events */
|
374 | 9fdc60bf | aurel32 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
375 | 9fdc60bf | aurel32 | switch (pin) {
|
376 | 9fdc60bf | aurel32 | case PPCE500_INPUT_MCK:
|
377 | 9fdc60bf | aurel32 | if (level) {
|
378 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC system\n",
|
379 | 9fdc60bf | aurel32 | __func__); |
380 | 9fdc60bf | aurel32 | qemu_system_reset_request(); |
381 | 9fdc60bf | aurel32 | } |
382 | 9fdc60bf | aurel32 | break;
|
383 | 9fdc60bf | aurel32 | case PPCE500_INPUT_RESET_CORE:
|
384 | 9fdc60bf | aurel32 | if (level) {
|
385 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
|
386 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_MCK, level); |
387 | 9fdc60bf | aurel32 | } |
388 | 9fdc60bf | aurel32 | break;
|
389 | 9fdc60bf | aurel32 | case PPCE500_INPUT_CINT:
|
390 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
391 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
392 | 9fdc60bf | aurel32 | __func__, level); |
393 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
394 | 9fdc60bf | aurel32 | break;
|
395 | 9fdc60bf | aurel32 | case PPCE500_INPUT_INT:
|
396 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
397 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the core IRQ state to %d\n",
|
398 | 9fdc60bf | aurel32 | __func__, level); |
399 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
400 | 9fdc60bf | aurel32 | break;
|
401 | 9fdc60bf | aurel32 | case PPCE500_INPUT_DEBUG:
|
402 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
403 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the debug pin state to %d\n",
|
404 | 9fdc60bf | aurel32 | __func__, level); |
405 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
406 | 9fdc60bf | aurel32 | break;
|
407 | 9fdc60bf | aurel32 | default:
|
408 | 9fdc60bf | aurel32 | /* Unknown pin - do nothing */
|
409 | 9fdc60bf | aurel32 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
410 | 9fdc60bf | aurel32 | return;
|
411 | 9fdc60bf | aurel32 | } |
412 | 9fdc60bf | aurel32 | if (level)
|
413 | 9fdc60bf | aurel32 | env->irq_input_state |= 1 << pin;
|
414 | 9fdc60bf | aurel32 | else
|
415 | 9fdc60bf | aurel32 | env->irq_input_state &= ~(1 << pin);
|
416 | 9fdc60bf | aurel32 | } |
417 | 9fdc60bf | aurel32 | } |
418 | 9fdc60bf | aurel32 | |
419 | 9fdc60bf | aurel32 | void ppce500_irq_init (CPUState *env)
|
420 | 9fdc60bf | aurel32 | { |
421 | 9fdc60bf | aurel32 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
|
422 | 9fdc60bf | aurel32 | env, PPCE500_INPUT_NB); |
423 | 9fdc60bf | aurel32 | } |
424 | 9fddaa0c | bellard | /*****************************************************************************/
|
425 | e9df014c | j_mayer | /* PowerPC time base and decrementer emulation */
|
426 | 9fddaa0c | bellard | |
427 | ddd1055b | Fabien Chouteau | uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) |
428 | 9fddaa0c | bellard | { |
429 | 9fddaa0c | bellard | /* TB time in tb periods */
|
430 | 6ee093c9 | Juan Quintela | return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
|
431 | 9fddaa0c | bellard | } |
432 | 9fddaa0c | bellard | |
433 | e3ea6529 | Alexander Graf | uint64_t cpu_ppc_load_tbl (CPUState *env) |
434 | 9fddaa0c | bellard | { |
435 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
436 | 9fddaa0c | bellard | uint64_t tb; |
437 | 9fddaa0c | bellard | |
438 | 90dc8812 | Scott Wood | if (kvm_enabled()) {
|
439 | 90dc8812 | Scott Wood | return env->spr[SPR_TBL];
|
440 | 90dc8812 | Scott Wood | } |
441 | 90dc8812 | Scott Wood | |
442 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
443 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
444 | 9fddaa0c | bellard | |
445 | e3ea6529 | Alexander Graf | return tb;
|
446 | 9fddaa0c | bellard | } |
447 | 9fddaa0c | bellard | |
448 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) |
449 | 9fddaa0c | bellard | { |
450 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
451 | 9fddaa0c | bellard | uint64_t tb; |
452 | 9fddaa0c | bellard | |
453 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
454 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
455 | 76a66253 | j_mayer | |
456 | 9fddaa0c | bellard | return tb >> 32; |
457 | 9fddaa0c | bellard | } |
458 | 9fddaa0c | bellard | |
459 | 8a84de23 | j_mayer | uint32_t cpu_ppc_load_tbu (CPUState *env) |
460 | 8a84de23 | j_mayer | { |
461 | 90dc8812 | Scott Wood | if (kvm_enabled()) {
|
462 | 90dc8812 | Scott Wood | return env->spr[SPR_TBU];
|
463 | 90dc8812 | Scott Wood | } |
464 | 90dc8812 | Scott Wood | |
465 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
466 | 8a84de23 | j_mayer | } |
467 | 8a84de23 | j_mayer | |
468 | c227f099 | Anthony Liguori | static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
469 | 636aa200 | Blue Swirl | int64_t *tb_offsetp, uint64_t value) |
470 | 9fddaa0c | bellard | { |
471 | 6ee093c9 | Juan Quintela | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); |
472 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
473 | aae9366a | j_mayer | __func__, value, *tb_offsetp); |
474 | 9fddaa0c | bellard | } |
475 | 9fddaa0c | bellard | |
476 | a062e36c | j_mayer | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
|
477 | a062e36c | j_mayer | { |
478 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
479 | a062e36c | j_mayer | uint64_t tb; |
480 | a062e36c | j_mayer | |
481 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
482 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
483 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
484 | dbdd2506 | j_mayer | &tb_env->tb_offset, tb | (uint64_t)value); |
485 | a062e36c | j_mayer | } |
486 | a062e36c | j_mayer | |
487 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) |
488 | 9fddaa0c | bellard | { |
489 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
490 | a062e36c | j_mayer | uint64_t tb; |
491 | 9fddaa0c | bellard | |
492 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
493 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
494 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
495 | dbdd2506 | j_mayer | &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
|
496 | 9fddaa0c | bellard | } |
497 | 9fddaa0c | bellard | |
498 | 8a84de23 | j_mayer | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
499 | 8a84de23 | j_mayer | { |
500 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
501 | 8a84de23 | j_mayer | } |
502 | 8a84de23 | j_mayer | |
503 | b711de95 | Aurelien Jarno | uint64_t cpu_ppc_load_atbl (CPUState *env) |
504 | a062e36c | j_mayer | { |
505 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
506 | a062e36c | j_mayer | uint64_t tb; |
507 | a062e36c | j_mayer | |
508 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
509 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
510 | a062e36c | j_mayer | |
511 | b711de95 | Aurelien Jarno | return tb;
|
512 | a062e36c | j_mayer | } |
513 | a062e36c | j_mayer | |
514 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbu (CPUState *env) |
515 | a062e36c | j_mayer | { |
516 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
517 | a062e36c | j_mayer | uint64_t tb; |
518 | a062e36c | j_mayer | |
519 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
520 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
521 | a062e36c | j_mayer | |
522 | a062e36c | j_mayer | return tb >> 32; |
523 | a062e36c | j_mayer | } |
524 | a062e36c | j_mayer | |
525 | a062e36c | j_mayer | void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
|
526 | a062e36c | j_mayer | { |
527 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
528 | a062e36c | j_mayer | uint64_t tb; |
529 | a062e36c | j_mayer | |
530 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
531 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
532 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
533 | dbdd2506 | j_mayer | &tb_env->atb_offset, tb | (uint64_t)value); |
534 | a062e36c | j_mayer | } |
535 | a062e36c | j_mayer | |
536 | a062e36c | j_mayer | void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
|
537 | 9fddaa0c | bellard | { |
538 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
539 | a062e36c | j_mayer | uint64_t tb; |
540 | 9fddaa0c | bellard | |
541 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
542 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
543 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
544 | dbdd2506 | j_mayer | &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
|
545 | dbdd2506 | j_mayer | } |
546 | dbdd2506 | j_mayer | |
547 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env) |
548 | dbdd2506 | j_mayer | { |
549 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
550 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
551 | dbdd2506 | j_mayer | |
552 | dbdd2506 | j_mayer | /* If the time base is already frozen, do nothing */
|
553 | dbdd2506 | j_mayer | if (tb_env->tb_freq != 0) { |
554 | 74475455 | Paolo Bonzini | vmclk = qemu_get_clock_ns(vm_clock); |
555 | dbdd2506 | j_mayer | /* Get the time base */
|
556 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
557 | dbdd2506 | j_mayer | /* Get the alternate time base */
|
558 | dbdd2506 | j_mayer | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
559 | dbdd2506 | j_mayer | /* Store the time base value (ie compute the current offset) */
|
560 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
561 | dbdd2506 | j_mayer | /* Store the alternate time base value (compute the current offset) */
|
562 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
563 | dbdd2506 | j_mayer | /* Set the time base frequency to zero */
|
564 | dbdd2506 | j_mayer | tb_env->tb_freq = 0;
|
565 | dbdd2506 | j_mayer | /* Now, the time bases are frozen to tb_offset / atb_offset value */
|
566 | dbdd2506 | j_mayer | } |
567 | dbdd2506 | j_mayer | } |
568 | dbdd2506 | j_mayer | |
569 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env) |
570 | dbdd2506 | j_mayer | { |
571 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
572 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
573 | aae9366a | j_mayer | |
574 | dbdd2506 | j_mayer | /* If the time base is not frozen, do nothing */
|
575 | dbdd2506 | j_mayer | if (tb_env->tb_freq == 0) { |
576 | 74475455 | Paolo Bonzini | vmclk = qemu_get_clock_ns(vm_clock); |
577 | dbdd2506 | j_mayer | /* Get the time base from tb_offset */
|
578 | dbdd2506 | j_mayer | tb = tb_env->tb_offset; |
579 | dbdd2506 | j_mayer | /* Get the alternate time base from atb_offset */
|
580 | dbdd2506 | j_mayer | atb = tb_env->atb_offset; |
581 | dbdd2506 | j_mayer | /* Restore the tb frequency from the decrementer frequency */
|
582 | dbdd2506 | j_mayer | tb_env->tb_freq = tb_env->decr_freq; |
583 | dbdd2506 | j_mayer | /* Store the time base value */
|
584 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
585 | dbdd2506 | j_mayer | /* Store the alternate time base value */
|
586 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
587 | dbdd2506 | j_mayer | } |
588 | 9fddaa0c | bellard | } |
589 | 9fddaa0c | bellard | |
590 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) |
591 | 9fddaa0c | bellard | { |
592 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
593 | 9fddaa0c | bellard | uint32_t decr; |
594 | 4e588a4d | bellard | int64_t diff; |
595 | 9fddaa0c | bellard | |
596 | 74475455 | Paolo Bonzini | diff = next - qemu_get_clock_ns(vm_clock); |
597 | ddd1055b | Fabien Chouteau | if (diff >= 0) { |
598 | 6ee093c9 | Juan Quintela | decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); |
599 | ddd1055b | Fabien Chouteau | } else if (tb_env->flags & PPC_TIMER_BOOKE) { |
600 | ddd1055b | Fabien Chouteau | decr = 0;
|
601 | ddd1055b | Fabien Chouteau | } else {
|
602 | 6ee093c9 | Juan Quintela | decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec()); |
603 | ddd1055b | Fabien Chouteau | } |
604 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); |
605 | 76a66253 | j_mayer | |
606 | 9fddaa0c | bellard | return decr;
|
607 | 9fddaa0c | bellard | } |
608 | 9fddaa0c | bellard | |
609 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_decr (CPUState *env) |
610 | 58a7d328 | j_mayer | { |
611 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
612 | 58a7d328 | j_mayer | |
613 | 90dc8812 | Scott Wood | if (kvm_enabled()) {
|
614 | 90dc8812 | Scott Wood | return env->spr[SPR_DECR];
|
615 | 90dc8812 | Scott Wood | } |
616 | 90dc8812 | Scott Wood | |
617 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->decr_next);
|
618 | 58a7d328 | j_mayer | } |
619 | 58a7d328 | j_mayer | |
620 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_hdecr (CPUState *env) |
621 | 58a7d328 | j_mayer | { |
622 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
623 | 58a7d328 | j_mayer | |
624 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
|
625 | 58a7d328 | j_mayer | } |
626 | 58a7d328 | j_mayer | |
627 | 58a7d328 | j_mayer | uint64_t cpu_ppc_load_purr (CPUState *env) |
628 | 58a7d328 | j_mayer | { |
629 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
630 | 58a7d328 | j_mayer | uint64_t diff; |
631 | 58a7d328 | j_mayer | |
632 | 74475455 | Paolo Bonzini | diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start; |
633 | b33c17e1 | j_mayer | |
634 | 6ee093c9 | Juan Quintela | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
|
635 | 58a7d328 | j_mayer | } |
636 | 58a7d328 | j_mayer | |
637 | 9fddaa0c | bellard | /* When decrementer expires,
|
638 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
|
639 | 9fddaa0c | bellard | */
|
640 | 636aa200 | Blue Swirl | static inline void cpu_ppc_decr_excp(CPUState *env) |
641 | 9fddaa0c | bellard | { |
642 | 9fddaa0c | bellard | /* Raise it */
|
643 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
644 | 47103572 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
645 | 9fddaa0c | bellard | } |
646 | 9fddaa0c | bellard | |
647 | 636aa200 | Blue Swirl | static inline void cpu_ppc_hdecr_excp(CPUState *env) |
648 | 58a7d328 | j_mayer | { |
649 | 58a7d328 | j_mayer | /* Raise it */
|
650 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
651 | 58a7d328 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
|
652 | 58a7d328 | j_mayer | } |
653 | 58a7d328 | j_mayer | |
654 | 58a7d328 | j_mayer | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, |
655 | b33c17e1 | j_mayer | struct QEMUTimer *timer,
|
656 | b33c17e1 | j_mayer | void (*raise_excp)(CPUState *),
|
657 | b33c17e1 | j_mayer | uint32_t decr, uint32_t value, |
658 | b33c17e1 | j_mayer | int is_excp)
|
659 | 9fddaa0c | bellard | { |
660 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
661 | 9fddaa0c | bellard | uint64_t now, next; |
662 | 9fddaa0c | bellard | |
663 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
664 | aae9366a | j_mayer | decr, value); |
665 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
666 | 6ee093c9 | Juan Quintela | next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); |
667 | ddd1055b | Fabien Chouteau | if (is_excp) {
|
668 | 58a7d328 | j_mayer | next += *nextp - now; |
669 | ddd1055b | Fabien Chouteau | } |
670 | ddd1055b | Fabien Chouteau | if (next == now) {
|
671 | 76a66253 | j_mayer | next++; |
672 | ddd1055b | Fabien Chouteau | } |
673 | 58a7d328 | j_mayer | *nextp = next; |
674 | 9fddaa0c | bellard | /* Adjust timer */
|
675 | 58a7d328 | j_mayer | qemu_mod_timer(timer, next); |
676 | ddd1055b | Fabien Chouteau | |
677 | ddd1055b | Fabien Chouteau | /* If we set a negative value and the decrementer was positive, raise an
|
678 | ddd1055b | Fabien Chouteau | * exception.
|
679 | 9fddaa0c | bellard | */
|
680 | ddd1055b | Fabien Chouteau | if ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED)
|
681 | ddd1055b | Fabien Chouteau | && (value & 0x80000000)
|
682 | ddd1055b | Fabien Chouteau | && !(decr & 0x80000000)) {
|
683 | 58a7d328 | j_mayer | (*raise_excp)(env); |
684 | ddd1055b | Fabien Chouteau | } |
685 | 58a7d328 | j_mayer | } |
686 | 58a7d328 | j_mayer | |
687 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, |
688 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
689 | 58a7d328 | j_mayer | { |
690 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
691 | 58a7d328 | j_mayer | |
692 | 58a7d328 | j_mayer | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, |
693 | 58a7d328 | j_mayer | &cpu_ppc_decr_excp, decr, value, is_excp); |
694 | 9fddaa0c | bellard | } |
695 | 9fddaa0c | bellard | |
696 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
697 | 9fddaa0c | bellard | { |
698 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
699 | 9fddaa0c | bellard | } |
700 | 9fddaa0c | bellard | |
701 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
702 | 9fddaa0c | bellard | { |
703 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
704 | 9fddaa0c | bellard | } |
705 | 9fddaa0c | bellard | |
706 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, |
707 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
708 | 58a7d328 | j_mayer | { |
709 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
710 | 58a7d328 | j_mayer | |
711 | b172c56a | j_mayer | if (tb_env->hdecr_timer != NULL) { |
712 | b172c56a | j_mayer | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, |
713 | b172c56a | j_mayer | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); |
714 | b172c56a | j_mayer | } |
715 | 58a7d328 | j_mayer | } |
716 | 58a7d328 | j_mayer | |
717 | 58a7d328 | j_mayer | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
|
718 | 58a7d328 | j_mayer | { |
719 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
|
720 | 58a7d328 | j_mayer | } |
721 | 58a7d328 | j_mayer | |
722 | 58a7d328 | j_mayer | static void cpu_ppc_hdecr_cb (void *opaque) |
723 | 58a7d328 | j_mayer | { |
724 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
725 | 58a7d328 | j_mayer | } |
726 | 58a7d328 | j_mayer | |
727 | 58a7d328 | j_mayer | void cpu_ppc_store_purr (CPUState *env, uint64_t value)
|
728 | 58a7d328 | j_mayer | { |
729 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
730 | 58a7d328 | j_mayer | |
731 | 58a7d328 | j_mayer | tb_env->purr_load = value; |
732 | 74475455 | Paolo Bonzini | tb_env->purr_start = qemu_get_clock_ns(vm_clock); |
733 | 58a7d328 | j_mayer | } |
734 | 58a7d328 | j_mayer | |
735 | 8ecc7913 | j_mayer | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
736 | 8ecc7913 | j_mayer | { |
737 | 8ecc7913 | j_mayer | CPUState *env = opaque; |
738 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
739 | 8ecc7913 | j_mayer | |
740 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
741 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
742 | 8ecc7913 | j_mayer | /* There is a bug in Linux 2.4 kernels:
|
743 | 8ecc7913 | j_mayer | * if a decrementer exception is pending when it enables msr_ee at startup,
|
744 | 8ecc7913 | j_mayer | * it's not ready to handle it...
|
745 | 8ecc7913 | j_mayer | */
|
746 | 8ecc7913 | j_mayer | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
747 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
748 | 58a7d328 | j_mayer | cpu_ppc_store_purr(env, 0x0000000000000000ULL);
|
749 | 8ecc7913 | j_mayer | } |
750 | 8ecc7913 | j_mayer | |
751 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
|
752 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
753 | 9fddaa0c | bellard | { |
754 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
755 | 9fddaa0c | bellard | |
756 | 7267c094 | Anthony Liguori | tb_env = g_malloc0(sizeof(ppc_tb_t));
|
757 | 9fddaa0c | bellard | env->tb_env = tb_env; |
758 | ddd1055b | Fabien Chouteau | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
759 | 8ecc7913 | j_mayer | /* Create new timer */
|
760 | 74475455 | Paolo Bonzini | tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, env); |
761 | b172c56a | j_mayer | if (0) { |
762 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor decrementer
|
763 | b172c56a | j_mayer | */
|
764 | 74475455 | Paolo Bonzini | tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb, env); |
765 | b172c56a | j_mayer | } else {
|
766 | b172c56a | j_mayer | tb_env->hdecr_timer = NULL;
|
767 | b172c56a | j_mayer | } |
768 | 8ecc7913 | j_mayer | cpu_ppc_set_tb_clk(env, freq); |
769 | 9fddaa0c | bellard | |
770 | 8ecc7913 | j_mayer | return &cpu_ppc_set_tb_clk;
|
771 | 9fddaa0c | bellard | } |
772 | 9fddaa0c | bellard | |
773 | 76a66253 | j_mayer | /* Specific helpers for POWER & PowerPC 601 RTC */
|
774 | b1d8e52e | blueswir1 | #if 0
|
775 | b1d8e52e | blueswir1 | static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
|
776 | 76a66253 | j_mayer | {
|
777 | 76a66253 | j_mayer | return cpu_ppc_tb_init(env, 7812500);
|
778 | 76a66253 | j_mayer | }
|
779 | b1d8e52e | blueswir1 | #endif
|
780 | 76a66253 | j_mayer | |
781 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
782 | 8a84de23 | j_mayer | { |
783 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
784 | 8a84de23 | j_mayer | } |
785 | 76a66253 | j_mayer | |
786 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
787 | 8a84de23 | j_mayer | { |
788 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
789 | 8a84de23 | j_mayer | } |
790 | 76a66253 | j_mayer | |
791 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
792 | 76a66253 | j_mayer | { |
793 | 76a66253 | j_mayer | cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
794 | 76a66253 | j_mayer | } |
795 | 76a66253 | j_mayer | |
796 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
797 | 76a66253 | j_mayer | { |
798 | 76a66253 | j_mayer | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
799 | 76a66253 | j_mayer | } |
800 | 76a66253 | j_mayer | |
801 | 636aaad7 | j_mayer | /*****************************************************************************/
|
802 | ddd1055b | Fabien Chouteau | /* PowerPC 40x timers */
|
803 | 636aaad7 | j_mayer | |
804 | 636aaad7 | j_mayer | /* PIT, FIT & WDT */
|
805 | ddd1055b | Fabien Chouteau | typedef struct ppc40x_timer_t ppc40x_timer_t; |
806 | ddd1055b | Fabien Chouteau | struct ppc40x_timer_t {
|
807 | 636aaad7 | j_mayer | uint64_t pit_reload; /* PIT auto-reload value */
|
808 | 636aaad7 | j_mayer | uint64_t fit_next; /* Tick for next FIT interrupt */
|
809 | 636aaad7 | j_mayer | struct QEMUTimer *fit_timer;
|
810 | 636aaad7 | j_mayer | uint64_t wdt_next; /* Tick for next WDT interrupt */
|
811 | 636aaad7 | j_mayer | struct QEMUTimer *wdt_timer;
|
812 | d63cb48d | Edgar E. Iglesias | |
813 | d63cb48d | Edgar E. Iglesias | /* 405 have the PIT, 440 have a DECR. */
|
814 | d63cb48d | Edgar E. Iglesias | unsigned int decr_excp; |
815 | 636aaad7 | j_mayer | }; |
816 | 3b46e624 | ths | |
817 | 636aaad7 | j_mayer | /* Fixed interval timer */
|
818 | 636aaad7 | j_mayer | static void cpu_4xx_fit_cb (void *opaque) |
819 | 636aaad7 | j_mayer | { |
820 | 636aaad7 | j_mayer | CPUState *env; |
821 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
822 | ddd1055b | Fabien Chouteau | ppc40x_timer_t *ppc40x_timer; |
823 | 636aaad7 | j_mayer | uint64_t now, next; |
824 | 636aaad7 | j_mayer | |
825 | 636aaad7 | j_mayer | env = opaque; |
826 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
827 | ddd1055b | Fabien Chouteau | ppc40x_timer = tb_env->opaque; |
828 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
829 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
830 | 636aaad7 | j_mayer | case 0: |
831 | 636aaad7 | j_mayer | next = 1 << 9; |
832 | 636aaad7 | j_mayer | break;
|
833 | 636aaad7 | j_mayer | case 1: |
834 | 636aaad7 | j_mayer | next = 1 << 13; |
835 | 636aaad7 | j_mayer | break;
|
836 | 636aaad7 | j_mayer | case 2: |
837 | 636aaad7 | j_mayer | next = 1 << 17; |
838 | 636aaad7 | j_mayer | break;
|
839 | 636aaad7 | j_mayer | case 3: |
840 | 636aaad7 | j_mayer | next = 1 << 21; |
841 | 636aaad7 | j_mayer | break;
|
842 | 636aaad7 | j_mayer | default:
|
843 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
844 | 636aaad7 | j_mayer | return;
|
845 | 636aaad7 | j_mayer | } |
846 | 6ee093c9 | Juan Quintela | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq); |
847 | 636aaad7 | j_mayer | if (next == now)
|
848 | 636aaad7 | j_mayer | next++; |
849 | ddd1055b | Fabien Chouteau | qemu_mod_timer(ppc40x_timer->fit_timer, next); |
850 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 26; |
851 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
852 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
853 | 90e189ec | Blue Swirl | LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
854 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
855 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
856 | 636aaad7 | j_mayer | } |
857 | 636aaad7 | j_mayer | |
858 | 636aaad7 | j_mayer | /* Programmable interval timer */
|
859 | c227f099 | Anthony Liguori | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
860 | 76a66253 | j_mayer | { |
861 | ddd1055b | Fabien Chouteau | ppc40x_timer_t *ppc40x_timer; |
862 | 636aaad7 | j_mayer | uint64_t now, next; |
863 | 636aaad7 | j_mayer | |
864 | ddd1055b | Fabien Chouteau | ppc40x_timer = tb_env->opaque; |
865 | ddd1055b | Fabien Chouteau | if (ppc40x_timer->pit_reload <= 1 || |
866 | 4b6d0a4c | j_mayer | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
867 | 4b6d0a4c | j_mayer | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
868 | 4b6d0a4c | j_mayer | /* Stop PIT */
|
869 | d12d51d5 | aliguori | LOG_TB("%s: stop PIT\n", __func__);
|
870 | 4b6d0a4c | j_mayer | qemu_del_timer(tb_env->decr_timer); |
871 | 4b6d0a4c | j_mayer | } else {
|
872 | d12d51d5 | aliguori | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
873 | ddd1055b | Fabien Chouteau | __func__, ppc40x_timer->pit_reload); |
874 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
875 | ddd1055b | Fabien Chouteau | next = now + muldiv64(ppc40x_timer->pit_reload, |
876 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), tb_env->decr_freq); |
877 | 4b6d0a4c | j_mayer | if (is_excp)
|
878 | 4b6d0a4c | j_mayer | next += tb_env->decr_next - now; |
879 | 636aaad7 | j_mayer | if (next == now)
|
880 | 636aaad7 | j_mayer | next++; |
881 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
882 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
883 | 636aaad7 | j_mayer | } |
884 | 4b6d0a4c | j_mayer | } |
885 | 4b6d0a4c | j_mayer | |
886 | 4b6d0a4c | j_mayer | static void cpu_4xx_pit_cb (void *opaque) |
887 | 4b6d0a4c | j_mayer | { |
888 | 4b6d0a4c | j_mayer | CPUState *env; |
889 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
890 | ddd1055b | Fabien Chouteau | ppc40x_timer_t *ppc40x_timer; |
891 | 4b6d0a4c | j_mayer | |
892 | 4b6d0a4c | j_mayer | env = opaque; |
893 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
894 | ddd1055b | Fabien Chouteau | ppc40x_timer = tb_env->opaque; |
895 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 27; |
896 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
897 | ddd1055b | Fabien Chouteau | ppc_set_irq(env, ppc40x_timer->decr_excp, 1);
|
898 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
899 | 90e189ec | Blue Swirl | LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " |
900 | 90e189ec | Blue Swirl | "%016" PRIx64 "\n", __func__, |
901 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
902 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
903 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
904 | ddd1055b | Fabien Chouteau | ppc40x_timer->pit_reload); |
905 | 636aaad7 | j_mayer | } |
906 | 636aaad7 | j_mayer | |
907 | 636aaad7 | j_mayer | /* Watchdog timer */
|
908 | 636aaad7 | j_mayer | static void cpu_4xx_wdt_cb (void *opaque) |
909 | 636aaad7 | j_mayer | { |
910 | 636aaad7 | j_mayer | CPUState *env; |
911 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
912 | ddd1055b | Fabien Chouteau | ppc40x_timer_t *ppc40x_timer; |
913 | 636aaad7 | j_mayer | uint64_t now, next; |
914 | 636aaad7 | j_mayer | |
915 | 636aaad7 | j_mayer | env = opaque; |
916 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
917 | ddd1055b | Fabien Chouteau | ppc40x_timer = tb_env->opaque; |
918 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
919 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
920 | 636aaad7 | j_mayer | case 0: |
921 | 636aaad7 | j_mayer | next = 1 << 17; |
922 | 636aaad7 | j_mayer | break;
|
923 | 636aaad7 | j_mayer | case 1: |
924 | 636aaad7 | j_mayer | next = 1 << 21; |
925 | 636aaad7 | j_mayer | break;
|
926 | 636aaad7 | j_mayer | case 2: |
927 | 636aaad7 | j_mayer | next = 1 << 25; |
928 | 636aaad7 | j_mayer | break;
|
929 | 636aaad7 | j_mayer | case 3: |
930 | 636aaad7 | j_mayer | next = 1 << 29; |
931 | 636aaad7 | j_mayer | break;
|
932 | 636aaad7 | j_mayer | default:
|
933 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
934 | 636aaad7 | j_mayer | return;
|
935 | 636aaad7 | j_mayer | } |
936 | 6ee093c9 | Juan Quintela | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq); |
937 | 636aaad7 | j_mayer | if (next == now)
|
938 | 636aaad7 | j_mayer | next++; |
939 | 90e189ec | Blue Swirl | LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
940 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
941 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
942 | 636aaad7 | j_mayer | case 0x0: |
943 | 636aaad7 | j_mayer | case 0x1: |
944 | ddd1055b | Fabien Chouteau | qemu_mod_timer(ppc40x_timer->wdt_timer, next); |
945 | ddd1055b | Fabien Chouteau | ppc40x_timer->wdt_next = next; |
946 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 31; |
947 | 636aaad7 | j_mayer | break;
|
948 | 636aaad7 | j_mayer | case 0x2: |
949 | ddd1055b | Fabien Chouteau | qemu_mod_timer(ppc40x_timer->wdt_timer, next); |
950 | ddd1055b | Fabien Chouteau | ppc40x_timer->wdt_next = next; |
951 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 30; |
952 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
953 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
954 | 636aaad7 | j_mayer | break;
|
955 | 636aaad7 | j_mayer | case 0x3: |
956 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] &= ~0x30000000;
|
957 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
958 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
959 | 636aaad7 | j_mayer | case 0x0: |
960 | 636aaad7 | j_mayer | /* No reset */
|
961 | 636aaad7 | j_mayer | break;
|
962 | 636aaad7 | j_mayer | case 0x1: /* Core reset */ |
963 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
964 | 8ecc7913 | j_mayer | break;
|
965 | 636aaad7 | j_mayer | case 0x2: /* Chip reset */ |
966 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
967 | 8ecc7913 | j_mayer | break;
|
968 | 636aaad7 | j_mayer | case 0x3: /* System reset */ |
969 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
970 | 8ecc7913 | j_mayer | break;
|
971 | 636aaad7 | j_mayer | } |
972 | 636aaad7 | j_mayer | } |
973 | 76a66253 | j_mayer | } |
974 | 76a66253 | j_mayer | |
975 | 76a66253 | j_mayer | void store_40x_pit (CPUState *env, target_ulong val)
|
976 | 76a66253 | j_mayer | { |
977 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
978 | ddd1055b | Fabien Chouteau | ppc40x_timer_t *ppc40x_timer; |
979 | 636aaad7 | j_mayer | |
980 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
981 | ddd1055b | Fabien Chouteau | ppc40x_timer = tb_env->opaque; |
982 | 90e189ec | Blue Swirl | LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); |
983 | ddd1055b | Fabien Chouteau | ppc40x_timer->pit_reload = val; |
984 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 0);
|
985 | 76a66253 | j_mayer | } |
986 | 76a66253 | j_mayer | |
987 | 636aaad7 | j_mayer | target_ulong load_40x_pit (CPUState *env) |
988 | 76a66253 | j_mayer | { |
989 | 636aaad7 | j_mayer | return cpu_ppc_load_decr(env);
|
990 | 76a66253 | j_mayer | } |
991 | 76a66253 | j_mayer | |
992 | ddd1055b | Fabien Chouteau | static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) |
993 | 4b6d0a4c | j_mayer | { |
994 | 4b6d0a4c | j_mayer | CPUState *env = opaque; |
995 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
996 | 4b6d0a4c | j_mayer | |
997 | d12d51d5 | aliguori | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
998 | aae9366a | j_mayer | freq); |
999 | 4b6d0a4c | j_mayer | tb_env->tb_freq = freq; |
1000 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
1001 | 4b6d0a4c | j_mayer | /* XXX: we should also update all timers */
|
1002 | 4b6d0a4c | j_mayer | } |
1003 | 4b6d0a4c | j_mayer | |
1004 | ddd1055b | Fabien Chouteau | clk_setup_cb ppc_40x_timers_init (CPUState *env, uint32_t freq, |
1005 | d63cb48d | Edgar E. Iglesias | unsigned int decr_excp) |
1006 | 636aaad7 | j_mayer | { |
1007 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
1008 | ddd1055b | Fabien Chouteau | ppc40x_timer_t *ppc40x_timer; |
1009 | 636aaad7 | j_mayer | |
1010 | 7267c094 | Anthony Liguori | tb_env = g_malloc0(sizeof(ppc_tb_t));
|
1011 | 8ecc7913 | j_mayer | env->tb_env = tb_env; |
1012 | ddd1055b | Fabien Chouteau | tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; |
1013 | ddd1055b | Fabien Chouteau | ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t));
|
1014 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
1015 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
1016 | ddd1055b | Fabien Chouteau | tb_env->opaque = ppc40x_timer; |
1017 | d12d51d5 | aliguori | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
1018 | ddd1055b | Fabien Chouteau | if (ppc40x_timer != NULL) { |
1019 | 636aaad7 | j_mayer | /* We use decr timer for PIT */
|
1020 | 74475455 | Paolo Bonzini | tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env); |
1021 | ddd1055b | Fabien Chouteau | ppc40x_timer->fit_timer = |
1022 | 74475455 | Paolo Bonzini | qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env); |
1023 | ddd1055b | Fabien Chouteau | ppc40x_timer->wdt_timer = |
1024 | 74475455 | Paolo Bonzini | qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env); |
1025 | ddd1055b | Fabien Chouteau | ppc40x_timer->decr_excp = decr_excp; |
1026 | 636aaad7 | j_mayer | } |
1027 | 8ecc7913 | j_mayer | |
1028 | ddd1055b | Fabien Chouteau | return &ppc_40x_set_tb_clk;
|
1029 | 76a66253 | j_mayer | } |
1030 | 76a66253 | j_mayer | |
1031 | 2e719ba3 | j_mayer | /*****************************************************************************/
|
1032 | 2e719ba3 | j_mayer | /* Embedded PowerPC Device Control Registers */
|
1033 | c227f099 | Anthony Liguori | typedef struct ppc_dcrn_t ppc_dcrn_t; |
1034 | c227f099 | Anthony Liguori | struct ppc_dcrn_t {
|
1035 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read; |
1036 | 2e719ba3 | j_mayer | dcr_write_cb dcr_write; |
1037 | 2e719ba3 | j_mayer | void *opaque;
|
1038 | 2e719ba3 | j_mayer | }; |
1039 | 2e719ba3 | j_mayer | |
1040 | a750fc0b | j_mayer | /* XXX: on 460, DCR addresses are 32 bits wide,
|
1041 | a750fc0b | j_mayer | * using DCRIPR to get the 22 upper bits of the DCR address
|
1042 | a750fc0b | j_mayer | */
|
1043 | 2e719ba3 | j_mayer | #define DCRN_NB 1024 |
1044 | c227f099 | Anthony Liguori | struct ppc_dcr_t {
|
1045 | c227f099 | Anthony Liguori | ppc_dcrn_t dcrn[DCRN_NB]; |
1046 | 2e719ba3 | j_mayer | int (*read_error)(int dcrn); |
1047 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn); |
1048 | 2e719ba3 | j_mayer | }; |
1049 | 2e719ba3 | j_mayer | |
1050 | 73b01960 | Alexander Graf | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
1051 | 2e719ba3 | j_mayer | { |
1052 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1053 | 2e719ba3 | j_mayer | |
1054 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1055 | 2e719ba3 | j_mayer | goto error;
|
1056 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1057 | 2e719ba3 | j_mayer | if (dcr->dcr_read == NULL) |
1058 | 2e719ba3 | j_mayer | goto error;
|
1059 | 2e719ba3 | j_mayer | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
1060 | 2e719ba3 | j_mayer | |
1061 | 2e719ba3 | j_mayer | return 0; |
1062 | 2e719ba3 | j_mayer | |
1063 | 2e719ba3 | j_mayer | error:
|
1064 | 2e719ba3 | j_mayer | if (dcr_env->read_error != NULL) |
1065 | 2e719ba3 | j_mayer | return (*dcr_env->read_error)(dcrn);
|
1066 | 2e719ba3 | j_mayer | |
1067 | 2e719ba3 | j_mayer | return -1; |
1068 | 2e719ba3 | j_mayer | } |
1069 | 2e719ba3 | j_mayer | |
1070 | 73b01960 | Alexander Graf | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
1071 | 2e719ba3 | j_mayer | { |
1072 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1073 | 2e719ba3 | j_mayer | |
1074 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1075 | 2e719ba3 | j_mayer | goto error;
|
1076 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1077 | 2e719ba3 | j_mayer | if (dcr->dcr_write == NULL) |
1078 | 2e719ba3 | j_mayer | goto error;
|
1079 | 2e719ba3 | j_mayer | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
1080 | 2e719ba3 | j_mayer | |
1081 | 2e719ba3 | j_mayer | return 0; |
1082 | 2e719ba3 | j_mayer | |
1083 | 2e719ba3 | j_mayer | error:
|
1084 | 2e719ba3 | j_mayer | if (dcr_env->write_error != NULL) |
1085 | 2e719ba3 | j_mayer | return (*dcr_env->write_error)(dcrn);
|
1086 | 2e719ba3 | j_mayer | |
1087 | 2e719ba3 | j_mayer | return -1; |
1088 | 2e719ba3 | j_mayer | } |
1089 | 2e719ba3 | j_mayer | |
1090 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1091 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
1092 | 2e719ba3 | j_mayer | { |
1093 | c227f099 | Anthony Liguori | ppc_dcr_t *dcr_env; |
1094 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1095 | 2e719ba3 | j_mayer | |
1096 | 2e719ba3 | j_mayer | dcr_env = env->dcr_env; |
1097 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
1098 | 2e719ba3 | j_mayer | return -1; |
1099 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1100 | 2e719ba3 | j_mayer | return -1; |
1101 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1102 | 2e719ba3 | j_mayer | if (dcr->opaque != NULL || |
1103 | 2e719ba3 | j_mayer | dcr->dcr_read != NULL ||
|
1104 | 2e719ba3 | j_mayer | dcr->dcr_write != NULL)
|
1105 | 2e719ba3 | j_mayer | return -1; |
1106 | 2e719ba3 | j_mayer | dcr->opaque = opaque; |
1107 | 2e719ba3 | j_mayer | dcr->dcr_read = dcr_read; |
1108 | 2e719ba3 | j_mayer | dcr->dcr_write = dcr_write; |
1109 | 2e719ba3 | j_mayer | |
1110 | 2e719ba3 | j_mayer | return 0; |
1111 | 2e719ba3 | j_mayer | } |
1112 | 2e719ba3 | j_mayer | |
1113 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
1114 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn)) |
1115 | 2e719ba3 | j_mayer | { |
1116 | c227f099 | Anthony Liguori | ppc_dcr_t *dcr_env; |
1117 | 2e719ba3 | j_mayer | |
1118 | 7267c094 | Anthony Liguori | dcr_env = g_malloc0(sizeof(ppc_dcr_t));
|
1119 | 2e719ba3 | j_mayer | dcr_env->read_error = read_error; |
1120 | 2e719ba3 | j_mayer | dcr_env->write_error = write_error; |
1121 | 2e719ba3 | j_mayer | env->dcr_env = dcr_env; |
1122 | 2e719ba3 | j_mayer | |
1123 | 2e719ba3 | j_mayer | return 0; |
1124 | 2e719ba3 | j_mayer | } |
1125 | 2e719ba3 | j_mayer | |
1126 | 64201201 | bellard | /*****************************************************************************/
|
1127 | 64201201 | bellard | /* Debug port */
|
1128 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
1129 | 64201201 | bellard | { |
1130 | 64201201 | bellard | addr &= 0xF;
|
1131 | 64201201 | bellard | switch (addr) {
|
1132 | 64201201 | bellard | case 0: |
1133 | 64201201 | bellard | printf("%c", val);
|
1134 | 64201201 | bellard | break;
|
1135 | 64201201 | bellard | case 1: |
1136 | 64201201 | bellard | printf("\n");
|
1137 | 64201201 | bellard | fflush(stdout); |
1138 | 64201201 | bellard | break;
|
1139 | 64201201 | bellard | case 2: |
1140 | aae9366a | j_mayer | printf("Set loglevel to %04" PRIx32 "\n", val); |
1141 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
|
1142 | 64201201 | bellard | break;
|
1143 | 64201201 | bellard | } |
1144 | 64201201 | bellard | } |
1145 | 64201201 | bellard | |
1146 | 64201201 | bellard | /*****************************************************************************/
|
1147 | 64201201 | bellard | /* NVRAM helpers */
|
1148 | c227f099 | Anthony Liguori | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
1149 | 64201201 | bellard | { |
1150 | 3cbee15b | j_mayer | return (*nvram->read_fn)(nvram->opaque, addr);;
|
1151 | 64201201 | bellard | } |
1152 | 64201201 | bellard | |
1153 | c227f099 | Anthony Liguori | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
1154 | 64201201 | bellard | { |
1155 | 3cbee15b | j_mayer | (*nvram->write_fn)(nvram->opaque, addr, val); |
1156 | 64201201 | bellard | } |
1157 | 64201201 | bellard | |
1158 | c227f099 | Anthony Liguori | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
|
1159 | 64201201 | bellard | { |
1160 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value); |
1161 | 64201201 | bellard | } |
1162 | 64201201 | bellard | |
1163 | c227f099 | Anthony Liguori | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) |
1164 | 3cbee15b | j_mayer | { |
1165 | 3cbee15b | j_mayer | return nvram_read(nvram, addr);
|
1166 | 3cbee15b | j_mayer | } |
1167 | 3cbee15b | j_mayer | |
1168 | c227f099 | Anthony Liguori | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
|
1169 | 3cbee15b | j_mayer | { |
1170 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 8);
|
1171 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, value & 0xFF); |
1172 | 3cbee15b | j_mayer | } |
1173 | 3cbee15b | j_mayer | |
1174 | c227f099 | Anthony Liguori | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) |
1175 | 64201201 | bellard | { |
1176 | 64201201 | bellard | uint16_t tmp; |
1177 | 64201201 | bellard | |
1178 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 8;
|
1179 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1);
|
1180 | 3cbee15b | j_mayer | |
1181 | 64201201 | bellard | return tmp;
|
1182 | 64201201 | bellard | } |
1183 | 64201201 | bellard | |
1184 | c227f099 | Anthony Liguori | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
|
1185 | 64201201 | bellard | { |
1186 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 24);
|
1187 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
1188 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
1189 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 3, value & 0xFF); |
1190 | 64201201 | bellard | } |
1191 | 64201201 | bellard | |
1192 | c227f099 | Anthony Liguori | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
1193 | 64201201 | bellard | { |
1194 | 64201201 | bellard | uint32_t tmp; |
1195 | 64201201 | bellard | |
1196 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 24;
|
1197 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1) << 16; |
1198 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 2) << 8; |
1199 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 3);
|
1200 | 76a66253 | j_mayer | |
1201 | 64201201 | bellard | return tmp;
|
1202 | 64201201 | bellard | } |
1203 | 64201201 | bellard | |
1204 | c227f099 | Anthony Liguori | void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
|
1205 | b55266b5 | blueswir1 | const char *str, uint32_t max) |
1206 | 64201201 | bellard | { |
1207 | 64201201 | bellard | int i;
|
1208 | 64201201 | bellard | |
1209 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
1210 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1211 | 64201201 | bellard | } |
1212 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1213 | 3cbee15b | j_mayer | nvram_write(nvram, addr + max - 1, '\0'); |
1214 | 64201201 | bellard | } |
1215 | 64201201 | bellard | |
1216 | c227f099 | Anthony Liguori | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
1217 | 64201201 | bellard | { |
1218 | 64201201 | bellard | int i;
|
1219 | 64201201 | bellard | |
1220 | 64201201 | bellard | memset(dst, 0, max);
|
1221 | 64201201 | bellard | for (i = 0; i < max; i++) { |
1222 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
1223 | 64201201 | bellard | if (dst[i] == '\0') |
1224 | 64201201 | bellard | break;
|
1225 | 64201201 | bellard | } |
1226 | 64201201 | bellard | |
1227 | 64201201 | bellard | return i;
|
1228 | 64201201 | bellard | } |
1229 | 64201201 | bellard | |
1230 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
1231 | 64201201 | bellard | { |
1232 | 64201201 | bellard | uint16_t tmp; |
1233 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
1234 | 64201201 | bellard | |
1235 | 64201201 | bellard | tmp = prev >> 8;
|
1236 | 64201201 | bellard | pd = prev ^ value; |
1237 | 64201201 | bellard | pd1 = pd & 0x000F;
|
1238 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
1239 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
1240 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
1241 | 64201201 | bellard | |
1242 | 64201201 | bellard | return tmp;
|
1243 | 64201201 | bellard | } |
1244 | 64201201 | bellard | |
1245 | c227f099 | Anthony Liguori | static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
|
1246 | 64201201 | bellard | { |
1247 | 64201201 | bellard | uint32_t i; |
1248 | 64201201 | bellard | uint16_t crc = 0xFFFF;
|
1249 | 64201201 | bellard | int odd;
|
1250 | 64201201 | bellard | |
1251 | 64201201 | bellard | odd = count & 1;
|
1252 | 64201201 | bellard | count &= ~1;
|
1253 | 64201201 | bellard | for (i = 0; i != count; i++) { |
1254 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
1255 | 64201201 | bellard | } |
1256 | 64201201 | bellard | if (odd) {
|
1257 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
1258 | 64201201 | bellard | } |
1259 | 64201201 | bellard | |
1260 | 64201201 | bellard | return crc;
|
1261 | 64201201 | bellard | } |
1262 | 64201201 | bellard | |
1263 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
1264 | fd0bbb12 | bellard | |
1265 | c227f099 | Anthony Liguori | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
1266 | b55266b5 | blueswir1 | const char *arch, |
1267 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1268 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1269 | fd0bbb12 | bellard | const char *cmdline, |
1270 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1271 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
1272 | fd0bbb12 | bellard | int width, int height, int depth) |
1273 | 64201201 | bellard | { |
1274 | 64201201 | bellard | uint16_t crc; |
1275 | 64201201 | bellard | |
1276 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
1277 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
1278 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
1279 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
1280 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
1281 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
1282 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
1283 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
|
1284 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
1285 | fd0bbb12 | bellard | if (cmdline) {
|
1286 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
1287 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
|
1288 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
1289 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
1290 | fd0bbb12 | bellard | } else {
|
1291 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
1292 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
1293 | fd0bbb12 | bellard | } |
1294 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
1295 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
1296 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
1297 | fd0bbb12 | bellard | |
1298 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
1299 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
1300 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
1301 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
1302 | 3cbee15b | j_mayer | NVRAM_set_word(nvram, 0xFC, crc);
|
1303 | 64201201 | bellard | |
1304 | 64201201 | bellard | return 0; |
1305 | a541f297 | bellard | } |