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1 | d34cab9f | ths | /*
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2 | d34cab9f | ths | * QEMU VMware-SVGA "chipset".
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3 | d34cab9f | ths | *
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4 | d34cab9f | ths | * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
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5 | d34cab9f | ths | *
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6 | d34cab9f | ths | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | d34cab9f | ths | * of this software and associated documentation files (the "Software"), to deal
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8 | d34cab9f | ths | * in the Software without restriction, including without limitation the rights
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9 | d34cab9f | ths | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | d34cab9f | ths | * copies of the Software, and to permit persons to whom the Software is
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11 | d34cab9f | ths | * furnished to do so, subject to the following conditions:
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12 | d34cab9f | ths | *
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13 | d34cab9f | ths | * The above copyright notice and this permission notice shall be included in
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14 | d34cab9f | ths | * all copies or substantial portions of the Software.
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15 | d34cab9f | ths | *
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16 | d34cab9f | ths | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | d34cab9f | ths | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | d34cab9f | ths | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | d34cab9f | ths | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | d34cab9f | ths | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | d34cab9f | ths | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | d34cab9f | ths | * THE SOFTWARE.
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23 | d34cab9f | ths | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | b3c3f123 | Dave Airlie | #include "loader.h" |
26 | 87ecb68b | pbrook | #include "console.h" |
27 | 87ecb68b | pbrook | #include "pci.h" |
28 | 18e08a55 | Michael S. Tsirkin | #include "vmware_vga.h" |
29 | d34cab9f | ths | |
30 | ca0508df | Jan Kiszka | #undef VERBOSE
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31 | d34cab9f | ths | #define HW_RECT_ACCEL
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32 | d34cab9f | ths | #define HW_FILL_ACCEL
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33 | d34cab9f | ths | #define HW_MOUSE_ACCEL
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34 | d34cab9f | ths | |
35 | d34cab9f | ths | # include "vga_int.h" |
36 | d34cab9f | ths | |
37 | d34cab9f | ths | struct vmsvga_state_s {
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38 | 4e12cd94 | Avi Kivity | VGACommonState vga; |
39 | d34cab9f | ths | |
40 | d34cab9f | ths | int width;
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41 | d34cab9f | ths | int height;
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42 | d34cab9f | ths | int invalidated;
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43 | d34cab9f | ths | int depth;
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44 | d34cab9f | ths | int bypp;
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45 | d34cab9f | ths | int enable;
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46 | d34cab9f | ths | int config;
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47 | d34cab9f | ths | struct {
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48 | d34cab9f | ths | int id;
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49 | d34cab9f | ths | int x;
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50 | d34cab9f | ths | int y;
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51 | d34cab9f | ths | int on;
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52 | d34cab9f | ths | } cursor; |
53 | d34cab9f | ths | |
54 | d34cab9f | ths | int index;
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55 | d34cab9f | ths | int scratch_size;
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56 | d34cab9f | ths | uint32_t *scratch; |
57 | d34cab9f | ths | int new_width;
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58 | d34cab9f | ths | int new_height;
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59 | d34cab9f | ths | uint32_t guest; |
60 | d34cab9f | ths | uint32_t svgaid; |
61 | d34cab9f | ths | uint32_t wred; |
62 | d34cab9f | ths | uint32_t wgreen; |
63 | d34cab9f | ths | uint32_t wblue; |
64 | d34cab9f | ths | int syncing;
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65 | d34cab9f | ths | int fb_size;
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66 | d34cab9f | ths | |
67 | b1950430 | Avi Kivity | MemoryRegion fifo_ram; |
68 | f351d050 | Dave Airlie | uint8_t *fifo_ptr; |
69 | f351d050 | Dave Airlie | unsigned int fifo_size; |
70 | f351d050 | Dave Airlie | |
71 | d34cab9f | ths | union {
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72 | d34cab9f | ths | uint32_t *fifo; |
73 | 541dc0d4 | Stefan Weil | struct QEMU_PACKED {
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74 | d34cab9f | ths | uint32_t min; |
75 | d34cab9f | ths | uint32_t max; |
76 | d34cab9f | ths | uint32_t next_cmd; |
77 | d34cab9f | ths | uint32_t stop; |
78 | d34cab9f | ths | /* Add registers here when adding capabilities. */
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79 | d34cab9f | ths | uint32_t fifo[0];
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80 | d34cab9f | ths | } *cmd; |
81 | d34cab9f | ths | }; |
82 | d34cab9f | ths | |
83 | d34cab9f | ths | #define REDRAW_FIFO_LEN 512 |
84 | d34cab9f | ths | struct vmsvga_rect_s {
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85 | d34cab9f | ths | int x, y, w, h;
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86 | d34cab9f | ths | } redraw_fifo[REDRAW_FIFO_LEN]; |
87 | d34cab9f | ths | int redraw_fifo_first, redraw_fifo_last;
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88 | d34cab9f | ths | }; |
89 | d34cab9f | ths | |
90 | d34cab9f | ths | struct pci_vmsvga_state_s {
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91 | d34cab9f | ths | PCIDevice card; |
92 | d34cab9f | ths | struct vmsvga_state_s chip;
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93 | b1950430 | Avi Kivity | MemoryRegion io_bar; |
94 | d34cab9f | ths | }; |
95 | d34cab9f | ths | |
96 | d34cab9f | ths | #define SVGA_MAGIC 0x900000UL |
97 | d34cab9f | ths | #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) |
98 | d34cab9f | ths | #define SVGA_ID_0 SVGA_MAKE_ID(0) |
99 | d34cab9f | ths | #define SVGA_ID_1 SVGA_MAKE_ID(1) |
100 | d34cab9f | ths | #define SVGA_ID_2 SVGA_MAKE_ID(2) |
101 | d34cab9f | ths | |
102 | d34cab9f | ths | #define SVGA_LEGACY_BASE_PORT 0x4560 |
103 | d34cab9f | ths | #define SVGA_INDEX_PORT 0x0 |
104 | d34cab9f | ths | #define SVGA_VALUE_PORT 0x1 |
105 | d34cab9f | ths | #define SVGA_BIOS_PORT 0x2 |
106 | d34cab9f | ths | |
107 | d34cab9f | ths | #define SVGA_VERSION_2
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108 | d34cab9f | ths | |
109 | d34cab9f | ths | #ifdef SVGA_VERSION_2
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110 | d34cab9f | ths | # define SVGA_ID SVGA_ID_2
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111 | d34cab9f | ths | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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112 | d34cab9f | ths | # define SVGA_IO_MUL 1 |
113 | d34cab9f | ths | # define SVGA_FIFO_SIZE 0x10000 |
114 | d34cab9f | ths | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
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115 | d34cab9f | ths | #else
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116 | d34cab9f | ths | # define SVGA_ID SVGA_ID_1
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117 | d34cab9f | ths | # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
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118 | d34cab9f | ths | # define SVGA_IO_MUL 4 |
119 | d34cab9f | ths | # define SVGA_FIFO_SIZE 0x10000 |
120 | d34cab9f | ths | # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
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121 | d34cab9f | ths | #endif
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122 | d34cab9f | ths | |
123 | d34cab9f | ths | enum {
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124 | d34cab9f | ths | /* ID 0, 1 and 2 registers */
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125 | d34cab9f | ths | SVGA_REG_ID = 0,
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126 | d34cab9f | ths | SVGA_REG_ENABLE = 1,
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127 | d34cab9f | ths | SVGA_REG_WIDTH = 2,
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128 | d34cab9f | ths | SVGA_REG_HEIGHT = 3,
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129 | d34cab9f | ths | SVGA_REG_MAX_WIDTH = 4,
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130 | d34cab9f | ths | SVGA_REG_MAX_HEIGHT = 5,
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131 | d34cab9f | ths | SVGA_REG_DEPTH = 6,
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132 | d34cab9f | ths | SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ |
133 | d34cab9f | ths | SVGA_REG_PSEUDOCOLOR = 8,
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134 | d34cab9f | ths | SVGA_REG_RED_MASK = 9,
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135 | d34cab9f | ths | SVGA_REG_GREEN_MASK = 10,
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136 | d34cab9f | ths | SVGA_REG_BLUE_MASK = 11,
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137 | d34cab9f | ths | SVGA_REG_BYTES_PER_LINE = 12,
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138 | d34cab9f | ths | SVGA_REG_FB_START = 13,
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139 | d34cab9f | ths | SVGA_REG_FB_OFFSET = 14,
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140 | d34cab9f | ths | SVGA_REG_VRAM_SIZE = 15,
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141 | d34cab9f | ths | SVGA_REG_FB_SIZE = 16,
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142 | d34cab9f | ths | |
143 | d34cab9f | ths | /* ID 1 and 2 registers */
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144 | d34cab9f | ths | SVGA_REG_CAPABILITIES = 17,
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145 | d34cab9f | ths | SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ |
146 | d34cab9f | ths | SVGA_REG_MEM_SIZE = 19,
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147 | d34cab9f | ths | SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ |
148 | d34cab9f | ths | SVGA_REG_SYNC = 21, /* Write to force synchronization */ |
149 | d34cab9f | ths | SVGA_REG_BUSY = 22, /* Read to check if sync is done */ |
150 | d34cab9f | ths | SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ |
151 | d34cab9f | ths | SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ |
152 | d34cab9f | ths | SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ |
153 | d34cab9f | ths | SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ |
154 | d34cab9f | ths | SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ |
155 | d34cab9f | ths | SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ |
156 | d34cab9f | ths | SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ |
157 | d34cab9f | ths | SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ |
158 | d34cab9f | ths | SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ |
159 | d34cab9f | ths | SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ |
160 | d34cab9f | ths | |
161 | d34cab9f | ths | SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ |
162 | d34cab9f | ths | SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
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163 | d34cab9f | ths | SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
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164 | d34cab9f | ths | }; |
165 | d34cab9f | ths | |
166 | d34cab9f | ths | #define SVGA_CAP_NONE 0 |
167 | d34cab9f | ths | #define SVGA_CAP_RECT_FILL (1 << 0) |
168 | d34cab9f | ths | #define SVGA_CAP_RECT_COPY (1 << 1) |
169 | d34cab9f | ths | #define SVGA_CAP_RECT_PAT_FILL (1 << 2) |
170 | d34cab9f | ths | #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) |
171 | d34cab9f | ths | #define SVGA_CAP_RASTER_OP (1 << 4) |
172 | d34cab9f | ths | #define SVGA_CAP_CURSOR (1 << 5) |
173 | d34cab9f | ths | #define SVGA_CAP_CURSOR_BYPASS (1 << 6) |
174 | d34cab9f | ths | #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) |
175 | d34cab9f | ths | #define SVGA_CAP_8BIT_EMULATION (1 << 8) |
176 | d34cab9f | ths | #define SVGA_CAP_ALPHA_CURSOR (1 << 9) |
177 | d34cab9f | ths | #define SVGA_CAP_GLYPH (1 << 10) |
178 | d34cab9f | ths | #define SVGA_CAP_GLYPH_CLIPPING (1 << 11) |
179 | d34cab9f | ths | #define SVGA_CAP_OFFSCREEN_1 (1 << 12) |
180 | d34cab9f | ths | #define SVGA_CAP_ALPHA_BLEND (1 << 13) |
181 | d34cab9f | ths | #define SVGA_CAP_3D (1 << 14) |
182 | d34cab9f | ths | #define SVGA_CAP_EXTENDED_FIFO (1 << 15) |
183 | d34cab9f | ths | #define SVGA_CAP_MULTIMON (1 << 16) |
184 | d34cab9f | ths | #define SVGA_CAP_PITCHLOCK (1 << 17) |
185 | d34cab9f | ths | |
186 | d34cab9f | ths | /*
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187 | d34cab9f | ths | * FIFO offsets (seen as an array of 32-bit words)
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188 | d34cab9f | ths | */
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189 | d34cab9f | ths | enum {
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190 | d34cab9f | ths | /*
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191 | d34cab9f | ths | * The original defined FIFO offsets
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192 | d34cab9f | ths | */
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193 | d34cab9f | ths | SVGA_FIFO_MIN = 0,
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194 | d34cab9f | ths | SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
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195 | d34cab9f | ths | SVGA_FIFO_NEXT_CMD, |
196 | d34cab9f | ths | SVGA_FIFO_STOP, |
197 | d34cab9f | ths | |
198 | d34cab9f | ths | /*
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199 | d34cab9f | ths | * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
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200 | d34cab9f | ths | */
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201 | d34cab9f | ths | SVGA_FIFO_CAPABILITIES = 4,
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202 | d34cab9f | ths | SVGA_FIFO_FLAGS, |
203 | d34cab9f | ths | SVGA_FIFO_FENCE, |
204 | d34cab9f | ths | SVGA_FIFO_3D_HWVERSION, |
205 | d34cab9f | ths | SVGA_FIFO_PITCHLOCK, |
206 | d34cab9f | ths | }; |
207 | d34cab9f | ths | |
208 | d34cab9f | ths | #define SVGA_FIFO_CAP_NONE 0 |
209 | d34cab9f | ths | #define SVGA_FIFO_CAP_FENCE (1 << 0) |
210 | d34cab9f | ths | #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) |
211 | d34cab9f | ths | #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) |
212 | d34cab9f | ths | |
213 | d34cab9f | ths | #define SVGA_FIFO_FLAG_NONE 0 |
214 | d34cab9f | ths | #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) |
215 | d34cab9f | ths | |
216 | d34cab9f | ths | /* These values can probably be changed arbitrarily. */
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217 | d34cab9f | ths | #define SVGA_SCRATCH_SIZE 0x8000 |
218 | d34cab9f | ths | #define SVGA_MAX_WIDTH 2360 |
219 | d34cab9f | ths | #define SVGA_MAX_HEIGHT 1770 |
220 | d34cab9f | ths | |
221 | d34cab9f | ths | #ifdef VERBOSE
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222 | d34cab9f | ths | # define GUEST_OS_BASE 0x5001 |
223 | d34cab9f | ths | static const char *vmsvga_guest_id[] = { |
224 | f707cfba | balrog | [0x00] = "Dos", |
225 | f707cfba | balrog | [0x01] = "Windows 3.1", |
226 | f707cfba | balrog | [0x02] = "Windows 95", |
227 | f707cfba | balrog | [0x03] = "Windows 98", |
228 | f707cfba | balrog | [0x04] = "Windows ME", |
229 | f707cfba | balrog | [0x05] = "Windows NT", |
230 | f707cfba | balrog | [0x06] = "Windows 2000", |
231 | f707cfba | balrog | [0x07] = "Linux", |
232 | f707cfba | balrog | [0x08] = "OS/2", |
233 | 511d2b14 | blueswir1 | [0x09] = "an unknown OS", |
234 | f707cfba | balrog | [0x0a] = "BSD", |
235 | f707cfba | balrog | [0x0b] = "Whistler", |
236 | 511d2b14 | blueswir1 | [0x0c] = "an unknown OS", |
237 | 511d2b14 | blueswir1 | [0x0d] = "an unknown OS", |
238 | 511d2b14 | blueswir1 | [0x0e] = "an unknown OS", |
239 | 511d2b14 | blueswir1 | [0x0f] = "an unknown OS", |
240 | 511d2b14 | blueswir1 | [0x10] = "an unknown OS", |
241 | 511d2b14 | blueswir1 | [0x11] = "an unknown OS", |
242 | 511d2b14 | blueswir1 | [0x12] = "an unknown OS", |
243 | 511d2b14 | blueswir1 | [0x13] = "an unknown OS", |
244 | 511d2b14 | blueswir1 | [0x14] = "an unknown OS", |
245 | f707cfba | balrog | [0x15] = "Windows 2003", |
246 | d34cab9f | ths | }; |
247 | d34cab9f | ths | #endif
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248 | d34cab9f | ths | |
249 | d34cab9f | ths | enum {
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250 | d34cab9f | ths | SVGA_CMD_INVALID_CMD = 0,
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251 | d34cab9f | ths | SVGA_CMD_UPDATE = 1,
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252 | d34cab9f | ths | SVGA_CMD_RECT_FILL = 2,
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253 | d34cab9f | ths | SVGA_CMD_RECT_COPY = 3,
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254 | d34cab9f | ths | SVGA_CMD_DEFINE_BITMAP = 4,
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255 | d34cab9f | ths | SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
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256 | d34cab9f | ths | SVGA_CMD_DEFINE_PIXMAP = 6,
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257 | d34cab9f | ths | SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
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258 | d34cab9f | ths | SVGA_CMD_RECT_BITMAP_FILL = 8,
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259 | d34cab9f | ths | SVGA_CMD_RECT_PIXMAP_FILL = 9,
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260 | d34cab9f | ths | SVGA_CMD_RECT_BITMAP_COPY = 10,
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261 | d34cab9f | ths | SVGA_CMD_RECT_PIXMAP_COPY = 11,
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262 | d34cab9f | ths | SVGA_CMD_FREE_OBJECT = 12,
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263 | d34cab9f | ths | SVGA_CMD_RECT_ROP_FILL = 13,
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264 | d34cab9f | ths | SVGA_CMD_RECT_ROP_COPY = 14,
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265 | d34cab9f | ths | SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
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266 | d34cab9f | ths | SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
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267 | d34cab9f | ths | SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
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268 | d34cab9f | ths | SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
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269 | d34cab9f | ths | SVGA_CMD_DEFINE_CURSOR = 19,
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270 | d34cab9f | ths | SVGA_CMD_DISPLAY_CURSOR = 20,
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271 | d34cab9f | ths | SVGA_CMD_MOVE_CURSOR = 21,
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272 | d34cab9f | ths | SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
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273 | d34cab9f | ths | SVGA_CMD_DRAW_GLYPH = 23,
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274 | d34cab9f | ths | SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
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275 | d34cab9f | ths | SVGA_CMD_UPDATE_VERBOSE = 25,
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276 | d34cab9f | ths | SVGA_CMD_SURFACE_FILL = 26,
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277 | d34cab9f | ths | SVGA_CMD_SURFACE_COPY = 27,
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278 | d34cab9f | ths | SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
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279 | d34cab9f | ths | SVGA_CMD_FRONT_ROP_FILL = 29,
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280 | d34cab9f | ths | SVGA_CMD_FENCE = 30,
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281 | d34cab9f | ths | }; |
282 | d34cab9f | ths | |
283 | d34cab9f | ths | /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
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284 | d34cab9f | ths | enum {
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285 | d34cab9f | ths | SVGA_CURSOR_ON_HIDE = 0,
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286 | d34cab9f | ths | SVGA_CURSOR_ON_SHOW = 1,
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287 | d34cab9f | ths | SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
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288 | d34cab9f | ths | SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
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289 | d34cab9f | ths | }; |
290 | d34cab9f | ths | |
291 | d34cab9f | ths | static inline void vmsvga_update_rect(struct vmsvga_state_s *s, |
292 | d34cab9f | ths | int x, int y, int w, int h) |
293 | d34cab9f | ths | { |
294 | a8fbaf96 | balrog | int line;
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295 | a8fbaf96 | balrog | int bypl;
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296 | a8fbaf96 | balrog | int width;
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297 | a8fbaf96 | balrog | int start;
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298 | a8fbaf96 | balrog | uint8_t *src; |
299 | a8fbaf96 | balrog | uint8_t *dst; |
300 | a8fbaf96 | balrog | |
301 | a8fbaf96 | balrog | if (x + w > s->width) {
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302 | a8fbaf96 | balrog | fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
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303 | a8fbaf96 | balrog | __FUNCTION__, x, w); |
304 | a8fbaf96 | balrog | x = MIN(x, s->width); |
305 | a8fbaf96 | balrog | w = s->width - x; |
306 | a8fbaf96 | balrog | } |
307 | a8fbaf96 | balrog | |
308 | a8fbaf96 | balrog | if (y + h > s->height) {
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309 | a8fbaf96 | balrog | fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
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310 | a8fbaf96 | balrog | __FUNCTION__, y, h); |
311 | a8fbaf96 | balrog | y = MIN(y, s->height); |
312 | a8fbaf96 | balrog | h = s->height - y; |
313 | a8fbaf96 | balrog | } |
314 | a8fbaf96 | balrog | |
315 | a8fbaf96 | balrog | line = h; |
316 | a8fbaf96 | balrog | bypl = s->bypp * s->width; |
317 | a8fbaf96 | balrog | width = s->bypp * w; |
318 | a8fbaf96 | balrog | start = s->bypp * x + bypl * y; |
319 | 4e12cd94 | Avi Kivity | src = s->vga.vram_ptr + start; |
320 | 4e12cd94 | Avi Kivity | dst = ds_get_data(s->vga.ds) + start; |
321 | d34cab9f | ths | |
322 | d34cab9f | ths | for (; line > 0; line --, src += bypl, dst += bypl) |
323 | d34cab9f | ths | memcpy(dst, src, width); |
324 | d34cab9f | ths | |
325 | 4e12cd94 | Avi Kivity | dpy_update(s->vga.ds, x, y, w, h); |
326 | d34cab9f | ths | } |
327 | d34cab9f | ths | |
328 | d34cab9f | ths | static inline void vmsvga_update_screen(struct vmsvga_state_s *s) |
329 | d34cab9f | ths | { |
330 | 8d121d49 | Jan Kiszka | memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, |
331 | 8d121d49 | Jan Kiszka | s->bypp * s->width * s->height); |
332 | 4e12cd94 | Avi Kivity | dpy_update(s->vga.ds, 0, 0, s->width, s->height); |
333 | d34cab9f | ths | } |
334 | d34cab9f | ths | |
335 | d34cab9f | ths | static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, |
336 | d34cab9f | ths | int x, int y, int w, int h) |
337 | d34cab9f | ths | { |
338 | d34cab9f | ths | struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
|
339 | d34cab9f | ths | s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
|
340 | d34cab9f | ths | rect->x = x; |
341 | d34cab9f | ths | rect->y = y; |
342 | d34cab9f | ths | rect->w = w; |
343 | d34cab9f | ths | rect->h = h; |
344 | d34cab9f | ths | } |
345 | d34cab9f | ths | |
346 | d34cab9f | ths | static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) |
347 | d34cab9f | ths | { |
348 | d34cab9f | ths | struct vmsvga_rect_s *rect;
|
349 | d34cab9f | ths | if (s->invalidated) {
|
350 | d34cab9f | ths | s->redraw_fifo_first = s->redraw_fifo_last; |
351 | d34cab9f | ths | return;
|
352 | d34cab9f | ths | } |
353 | d34cab9f | ths | /* Overlapping region updates can be optimised out here - if someone
|
354 | d34cab9f | ths | * knows a smart algorithm to do that, please share. */
|
355 | d34cab9f | ths | while (s->redraw_fifo_first != s->redraw_fifo_last) {
|
356 | d34cab9f | ths | rect = &s->redraw_fifo[s->redraw_fifo_first ++]; |
357 | d34cab9f | ths | s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
|
358 | d34cab9f | ths | vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); |
359 | d34cab9f | ths | } |
360 | d34cab9f | ths | } |
361 | d34cab9f | ths | |
362 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
363 | d34cab9f | ths | static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, |
364 | d34cab9f | ths | int x0, int y0, int x1, int y1, int w, int h) |
365 | d34cab9f | ths | { |
366 | 4e12cd94 | Avi Kivity | uint8_t *vram = s->vga.vram_ptr; |
367 | d34cab9f | ths | int bypl = s->bypp * s->width;
|
368 | d34cab9f | ths | int width = s->bypp * w;
|
369 | d34cab9f | ths | int line = h;
|
370 | d34cab9f | ths | uint8_t *ptr[2];
|
371 | d34cab9f | ths | |
372 | 8d121d49 | Jan Kiszka | if (y1 > y0) {
|
373 | 8d121d49 | Jan Kiszka | ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); |
374 | 8d121d49 | Jan Kiszka | ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); |
375 | 8d121d49 | Jan Kiszka | for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { |
376 | 8d121d49 | Jan Kiszka | memmove(ptr[1], ptr[0], width); |
377 | 8d121d49 | Jan Kiszka | } |
378 | 8d121d49 | Jan Kiszka | } else {
|
379 | 8d121d49 | Jan Kiszka | ptr[0] = vram + s->bypp * x0 + bypl * y0;
|
380 | 8d121d49 | Jan Kiszka | ptr[1] = vram + s->bypp * x1 + bypl * y1;
|
381 | 8d121d49 | Jan Kiszka | for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { |
382 | 8d121d49 | Jan Kiszka | memmove(ptr[1], ptr[0], width); |
383 | d34cab9f | ths | } |
384 | d34cab9f | ths | } |
385 | d34cab9f | ths | |
386 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x1, y1, w, h); |
387 | d34cab9f | ths | } |
388 | d34cab9f | ths | #endif
|
389 | d34cab9f | ths | |
390 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
391 | d34cab9f | ths | static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, |
392 | d34cab9f | ths | uint32_t c, int x, int y, int w, int h) |
393 | d34cab9f | ths | { |
394 | 4e12cd94 | Avi Kivity | uint8_t *vram = s->vga.vram_ptr; |
395 | d34cab9f | ths | int bypp = s->bypp;
|
396 | d34cab9f | ths | int bypl = bypp * s->width;
|
397 | d34cab9f | ths | int width = bypp * w;
|
398 | d34cab9f | ths | int line = h;
|
399 | d34cab9f | ths | int column;
|
400 | d34cab9f | ths | uint8_t *fst = vram + bypp * x + bypl * y; |
401 | d34cab9f | ths | uint8_t *dst; |
402 | d34cab9f | ths | uint8_t *src; |
403 | d34cab9f | ths | uint8_t col[4];
|
404 | d34cab9f | ths | |
405 | 8d121d49 | Jan Kiszka | col[0] = c;
|
406 | 8d121d49 | Jan Kiszka | col[1] = c >> 8; |
407 | 8d121d49 | Jan Kiszka | col[2] = c >> 16; |
408 | 8d121d49 | Jan Kiszka | col[3] = c >> 24; |
409 | 8d121d49 | Jan Kiszka | |
410 | 8d121d49 | Jan Kiszka | if (line--) {
|
411 | 8d121d49 | Jan Kiszka | dst = fst; |
412 | 8d121d49 | Jan Kiszka | src = col; |
413 | 8d121d49 | Jan Kiszka | for (column = width; column > 0; column--) { |
414 | 8d121d49 | Jan Kiszka | *(dst++) = *(src++); |
415 | 8d121d49 | Jan Kiszka | if (src - col == bypp) {
|
416 | 8d121d49 | Jan Kiszka | src = col; |
417 | d34cab9f | ths | } |
418 | d34cab9f | ths | } |
419 | 8d121d49 | Jan Kiszka | dst = fst; |
420 | 8d121d49 | Jan Kiszka | for (; line > 0; line--) { |
421 | 8d121d49 | Jan Kiszka | dst += bypl; |
422 | 8d121d49 | Jan Kiszka | memcpy(dst, fst, width); |
423 | 8d121d49 | Jan Kiszka | } |
424 | d34cab9f | ths | } |
425 | d34cab9f | ths | |
426 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x, y, w, h); |
427 | d34cab9f | ths | } |
428 | d34cab9f | ths | #endif
|
429 | d34cab9f | ths | |
430 | d34cab9f | ths | struct vmsvga_cursor_definition_s {
|
431 | d34cab9f | ths | int width;
|
432 | d34cab9f | ths | int height;
|
433 | d34cab9f | ths | int id;
|
434 | d34cab9f | ths | int bpp;
|
435 | d34cab9f | ths | int hot_x;
|
436 | d34cab9f | ths | int hot_y;
|
437 | d34cab9f | ths | uint32_t mask[1024];
|
438 | 8095cb3e | Dave Airlie | uint32_t image[4096];
|
439 | d34cab9f | ths | }; |
440 | d34cab9f | ths | |
441 | d34cab9f | ths | #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) |
442 | d34cab9f | ths | #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) |
443 | d34cab9f | ths | |
444 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
445 | d34cab9f | ths | static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, |
446 | d34cab9f | ths | struct vmsvga_cursor_definition_s *c)
|
447 | d34cab9f | ths | { |
448 | fbe6d7a4 | Gerd Hoffmann | QEMUCursor *qc; |
449 | fbe6d7a4 | Gerd Hoffmann | int i, pixels;
|
450 | fbe6d7a4 | Gerd Hoffmann | |
451 | fbe6d7a4 | Gerd Hoffmann | qc = cursor_alloc(c->width, c->height); |
452 | fbe6d7a4 | Gerd Hoffmann | qc->hot_x = c->hot_x; |
453 | fbe6d7a4 | Gerd Hoffmann | qc->hot_y = c->hot_y; |
454 | fbe6d7a4 | Gerd Hoffmann | switch (c->bpp) {
|
455 | fbe6d7a4 | Gerd Hoffmann | case 1: |
456 | fbe6d7a4 | Gerd Hoffmann | cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image, |
457 | fbe6d7a4 | Gerd Hoffmann | 1, (void*)c->mask); |
458 | fbe6d7a4 | Gerd Hoffmann | #ifdef DEBUG
|
459 | fbe6d7a4 | Gerd Hoffmann | cursor_print_ascii_art(qc, "vmware/mono");
|
460 | fbe6d7a4 | Gerd Hoffmann | #endif
|
461 | fbe6d7a4 | Gerd Hoffmann | break;
|
462 | fbe6d7a4 | Gerd Hoffmann | case 32: |
463 | fbe6d7a4 | Gerd Hoffmann | /* fill alpha channel from mask, set color to zero */
|
464 | fbe6d7a4 | Gerd Hoffmann | cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask, |
465 | fbe6d7a4 | Gerd Hoffmann | 1, (void*)c->mask); |
466 | fbe6d7a4 | Gerd Hoffmann | /* add in rgb values */
|
467 | fbe6d7a4 | Gerd Hoffmann | pixels = c->width * c->height; |
468 | fbe6d7a4 | Gerd Hoffmann | for (i = 0; i < pixels; i++) { |
469 | fbe6d7a4 | Gerd Hoffmann | qc->data[i] |= c->image[i] & 0xffffff;
|
470 | fbe6d7a4 | Gerd Hoffmann | } |
471 | fbe6d7a4 | Gerd Hoffmann | #ifdef DEBUG
|
472 | fbe6d7a4 | Gerd Hoffmann | cursor_print_ascii_art(qc, "vmware/32bit");
|
473 | fbe6d7a4 | Gerd Hoffmann | #endif
|
474 | fbe6d7a4 | Gerd Hoffmann | break;
|
475 | fbe6d7a4 | Gerd Hoffmann | default:
|
476 | fbe6d7a4 | Gerd Hoffmann | fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n",
|
477 | fbe6d7a4 | Gerd Hoffmann | __FUNCTION__, c->bpp); |
478 | fbe6d7a4 | Gerd Hoffmann | cursor_put(qc); |
479 | fbe6d7a4 | Gerd Hoffmann | qc = cursor_builtin_left_ptr(); |
480 | fbe6d7a4 | Gerd Hoffmann | } |
481 | d34cab9f | ths | |
482 | 4e12cd94 | Avi Kivity | if (s->vga.ds->cursor_define)
|
483 | fbe6d7a4 | Gerd Hoffmann | s->vga.ds->cursor_define(qc); |
484 | fbe6d7a4 | Gerd Hoffmann | cursor_put(qc); |
485 | d34cab9f | ths | } |
486 | d34cab9f | ths | #endif
|
487 | d34cab9f | ths | |
488 | ff9cf2cb | balrog | #define CMD(f) le32_to_cpu(s->cmd->f)
|
489 | ff9cf2cb | balrog | |
490 | 4dedc07f | Andrzej Zaborowski | static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) |
491 | d34cab9f | ths | { |
492 | 4dedc07f | Andrzej Zaborowski | int num;
|
493 | d34cab9f | ths | if (!s->config || !s->enable)
|
494 | 4dedc07f | Andrzej Zaborowski | return 0; |
495 | 4dedc07f | Andrzej Zaborowski | num = CMD(next_cmd) - CMD(stop); |
496 | 4dedc07f | Andrzej Zaborowski | if (num < 0) |
497 | 4dedc07f | Andrzej Zaborowski | num += CMD(max) - CMD(min); |
498 | 4dedc07f | Andrzej Zaborowski | return num >> 2; |
499 | d34cab9f | ths | } |
500 | d34cab9f | ths | |
501 | ff9cf2cb | balrog | static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) |
502 | d34cab9f | ths | { |
503 | ff9cf2cb | balrog | uint32_t cmd = s->fifo[CMD(stop) >> 2];
|
504 | ff9cf2cb | balrog | s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
|
505 | ff9cf2cb | balrog | if (CMD(stop) >= CMD(max))
|
506 | d34cab9f | ths | s->cmd->stop = s->cmd->min; |
507 | d34cab9f | ths | return cmd;
|
508 | d34cab9f | ths | } |
509 | d34cab9f | ths | |
510 | ff9cf2cb | balrog | static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s) |
511 | ff9cf2cb | balrog | { |
512 | ff9cf2cb | balrog | return le32_to_cpu(vmsvga_fifo_read_raw(s));
|
513 | ff9cf2cb | balrog | } |
514 | ff9cf2cb | balrog | |
515 | d34cab9f | ths | static void vmsvga_fifo_run(struct vmsvga_state_s *s) |
516 | d34cab9f | ths | { |
517 | d34cab9f | ths | uint32_t cmd, colour; |
518 | 4dedc07f | Andrzej Zaborowski | int args, len;
|
519 | d34cab9f | ths | int x, y, dx, dy, width, height;
|
520 | d34cab9f | ths | struct vmsvga_cursor_definition_s cursor;
|
521 | 4dedc07f | Andrzej Zaborowski | uint32_t cmd_start; |
522 | 4dedc07f | Andrzej Zaborowski | |
523 | 4dedc07f | Andrzej Zaborowski | len = vmsvga_fifo_length(s); |
524 | 4dedc07f | Andrzej Zaborowski | while (len > 0) { |
525 | 4dedc07f | Andrzej Zaborowski | /* May need to go back to the start of the command if incomplete */
|
526 | 4dedc07f | Andrzej Zaborowski | cmd_start = s->cmd->stop; |
527 | 4dedc07f | Andrzej Zaborowski | |
528 | d34cab9f | ths | switch (cmd = vmsvga_fifo_read(s)) {
|
529 | d34cab9f | ths | case SVGA_CMD_UPDATE:
|
530 | d34cab9f | ths | case SVGA_CMD_UPDATE_VERBOSE:
|
531 | 4dedc07f | Andrzej Zaborowski | len -= 5;
|
532 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
533 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
534 | 4dedc07f | Andrzej Zaborowski | |
535 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
536 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
537 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
538 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
539 | d34cab9f | ths | vmsvga_update_rect_delayed(s, x, y, width, height); |
540 | d34cab9f | ths | break;
|
541 | d34cab9f | ths | |
542 | d34cab9f | ths | case SVGA_CMD_RECT_FILL:
|
543 | 4dedc07f | Andrzej Zaborowski | len -= 6;
|
544 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
545 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
546 | 4dedc07f | Andrzej Zaborowski | |
547 | d34cab9f | ths | colour = vmsvga_fifo_read(s); |
548 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
549 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
550 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
551 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
552 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
553 | d34cab9f | ths | vmsvga_fill_rect(s, colour, x, y, width, height); |
554 | d34cab9f | ths | break;
|
555 | d34cab9f | ths | #else
|
556 | 4dedc07f | Andrzej Zaborowski | args = 0;
|
557 | d34cab9f | ths | goto badcmd;
|
558 | d34cab9f | ths | #endif
|
559 | d34cab9f | ths | |
560 | d34cab9f | ths | case SVGA_CMD_RECT_COPY:
|
561 | 4dedc07f | Andrzej Zaborowski | len -= 7;
|
562 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
563 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
564 | 4dedc07f | Andrzej Zaborowski | |
565 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
566 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
567 | d34cab9f | ths | dx = vmsvga_fifo_read(s); |
568 | d34cab9f | ths | dy = vmsvga_fifo_read(s); |
569 | d34cab9f | ths | width = vmsvga_fifo_read(s); |
570 | d34cab9f | ths | height = vmsvga_fifo_read(s); |
571 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
572 | d34cab9f | ths | vmsvga_copy_rect(s, x, y, dx, dy, width, height); |
573 | d34cab9f | ths | break;
|
574 | d34cab9f | ths | #else
|
575 | 4dedc07f | Andrzej Zaborowski | args = 0;
|
576 | d34cab9f | ths | goto badcmd;
|
577 | d34cab9f | ths | #endif
|
578 | d34cab9f | ths | |
579 | d34cab9f | ths | case SVGA_CMD_DEFINE_CURSOR:
|
580 | 4dedc07f | Andrzej Zaborowski | len -= 8;
|
581 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
582 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
583 | 4dedc07f | Andrzej Zaborowski | |
584 | d34cab9f | ths | cursor.id = vmsvga_fifo_read(s); |
585 | d34cab9f | ths | cursor.hot_x = vmsvga_fifo_read(s); |
586 | d34cab9f | ths | cursor.hot_y = vmsvga_fifo_read(s); |
587 | d34cab9f | ths | cursor.width = x = vmsvga_fifo_read(s); |
588 | d34cab9f | ths | cursor.height = y = vmsvga_fifo_read(s); |
589 | d34cab9f | ths | vmsvga_fifo_read(s); |
590 | d34cab9f | ths | cursor.bpp = vmsvga_fifo_read(s); |
591 | f2d928d4 | Roland Dreier | |
592 | 4dedc07f | Andrzej Zaborowski | args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); |
593 | 9f810beb | Andrzej Zaborowski | if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || |
594 | 9f810beb | Andrzej Zaborowski | SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image)
|
595 | 9f810beb | Andrzej Zaborowski | goto badcmd;
|
596 | 4dedc07f | Andrzej Zaborowski | |
597 | 4dedc07f | Andrzej Zaborowski | len -= args; |
598 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
599 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
600 | f2d928d4 | Roland Dreier | |
601 | d34cab9f | ths | for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++) |
602 | ff9cf2cb | balrog | cursor.mask[args] = vmsvga_fifo_read_raw(s); |
603 | d34cab9f | ths | for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++) |
604 | ff9cf2cb | balrog | cursor.image[args] = vmsvga_fifo_read_raw(s); |
605 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
606 | d34cab9f | ths | vmsvga_cursor_define(s, &cursor); |
607 | d34cab9f | ths | break;
|
608 | d34cab9f | ths | #else
|
609 | d34cab9f | ths | args = 0;
|
610 | d34cab9f | ths | goto badcmd;
|
611 | d34cab9f | ths | #endif
|
612 | d34cab9f | ths | |
613 | d34cab9f | ths | /*
|
614 | d34cab9f | ths | * Other commands that we at least know the number of arguments
|
615 | d34cab9f | ths | * for so we can avoid FIFO desync if driver uses them illegally.
|
616 | d34cab9f | ths | */
|
617 | d34cab9f | ths | case SVGA_CMD_DEFINE_ALPHA_CURSOR:
|
618 | 4dedc07f | Andrzej Zaborowski | len -= 6;
|
619 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
620 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
621 | 4dedc07f | Andrzej Zaborowski | |
622 | d34cab9f | ths | vmsvga_fifo_read(s); |
623 | d34cab9f | ths | vmsvga_fifo_read(s); |
624 | d34cab9f | ths | vmsvga_fifo_read(s); |
625 | d34cab9f | ths | x = vmsvga_fifo_read(s); |
626 | d34cab9f | ths | y = vmsvga_fifo_read(s); |
627 | d34cab9f | ths | args = x * y; |
628 | d34cab9f | ths | goto badcmd;
|
629 | d34cab9f | ths | case SVGA_CMD_RECT_ROP_FILL:
|
630 | d34cab9f | ths | args = 6;
|
631 | d34cab9f | ths | goto badcmd;
|
632 | d34cab9f | ths | case SVGA_CMD_RECT_ROP_COPY:
|
633 | d34cab9f | ths | args = 7;
|
634 | d34cab9f | ths | goto badcmd;
|
635 | d34cab9f | ths | case SVGA_CMD_DRAW_GLYPH_CLIPPED:
|
636 | 4dedc07f | Andrzej Zaborowski | len -= 4;
|
637 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
638 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
639 | 4dedc07f | Andrzej Zaborowski | |
640 | d34cab9f | ths | vmsvga_fifo_read(s); |
641 | d34cab9f | ths | vmsvga_fifo_read(s); |
642 | d34cab9f | ths | args = 7 + (vmsvga_fifo_read(s) >> 2); |
643 | d34cab9f | ths | goto badcmd;
|
644 | d34cab9f | ths | case SVGA_CMD_SURFACE_ALPHA_BLEND:
|
645 | d34cab9f | ths | args = 12;
|
646 | d34cab9f | ths | goto badcmd;
|
647 | d34cab9f | ths | |
648 | d34cab9f | ths | /*
|
649 | d34cab9f | ths | * Other commands that are not listed as depending on any
|
650 | d34cab9f | ths | * CAPABILITIES bits, but are not described in the README either.
|
651 | d34cab9f | ths | */
|
652 | d34cab9f | ths | case SVGA_CMD_SURFACE_FILL:
|
653 | d34cab9f | ths | case SVGA_CMD_SURFACE_COPY:
|
654 | d34cab9f | ths | case SVGA_CMD_FRONT_ROP_FILL:
|
655 | d34cab9f | ths | case SVGA_CMD_FENCE:
|
656 | d34cab9f | ths | case SVGA_CMD_INVALID_CMD:
|
657 | d34cab9f | ths | break; /* Nop */ |
658 | d34cab9f | ths | |
659 | d34cab9f | ths | default:
|
660 | 4dedc07f | Andrzej Zaborowski | args = 0;
|
661 | d34cab9f | ths | badcmd:
|
662 | 4dedc07f | Andrzej Zaborowski | len -= args; |
663 | 4dedc07f | Andrzej Zaborowski | if (len < 0) |
664 | 4dedc07f | Andrzej Zaborowski | goto rewind;
|
665 | d34cab9f | ths | while (args --)
|
666 | d34cab9f | ths | vmsvga_fifo_read(s); |
667 | d34cab9f | ths | printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
|
668 | d34cab9f | ths | __FUNCTION__, cmd); |
669 | d34cab9f | ths | break;
|
670 | 4dedc07f | Andrzej Zaborowski | |
671 | 4dedc07f | Andrzej Zaborowski | rewind:
|
672 | 4dedc07f | Andrzej Zaborowski | s->cmd->stop = cmd_start; |
673 | 4dedc07f | Andrzej Zaborowski | break;
|
674 | d34cab9f | ths | } |
675 | 4dedc07f | Andrzej Zaborowski | } |
676 | d34cab9f | ths | |
677 | d34cab9f | ths | s->syncing = 0;
|
678 | d34cab9f | ths | } |
679 | d34cab9f | ths | |
680 | d34cab9f | ths | static uint32_t vmsvga_index_read(void *opaque, uint32_t address) |
681 | d34cab9f | ths | { |
682 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
683 | d34cab9f | ths | return s->index;
|
684 | d34cab9f | ths | } |
685 | d34cab9f | ths | |
686 | d34cab9f | ths | static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) |
687 | d34cab9f | ths | { |
688 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
689 | d34cab9f | ths | s->index = index; |
690 | d34cab9f | ths | } |
691 | d34cab9f | ths | |
692 | d34cab9f | ths | static uint32_t vmsvga_value_read(void *opaque, uint32_t address) |
693 | d34cab9f | ths | { |
694 | d34cab9f | ths | uint32_t caps; |
695 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
696 | d34cab9f | ths | switch (s->index) {
|
697 | d34cab9f | ths | case SVGA_REG_ID:
|
698 | d34cab9f | ths | return s->svgaid;
|
699 | d34cab9f | ths | |
700 | d34cab9f | ths | case SVGA_REG_ENABLE:
|
701 | d34cab9f | ths | return s->enable;
|
702 | d34cab9f | ths | |
703 | d34cab9f | ths | case SVGA_REG_WIDTH:
|
704 | d34cab9f | ths | return s->width;
|
705 | d34cab9f | ths | |
706 | d34cab9f | ths | case SVGA_REG_HEIGHT:
|
707 | d34cab9f | ths | return s->height;
|
708 | d34cab9f | ths | |
709 | d34cab9f | ths | case SVGA_REG_MAX_WIDTH:
|
710 | d34cab9f | ths | return SVGA_MAX_WIDTH;
|
711 | d34cab9f | ths | |
712 | d34cab9f | ths | case SVGA_REG_MAX_HEIGHT:
|
713 | f707cfba | balrog | return SVGA_MAX_HEIGHT;
|
714 | d34cab9f | ths | |
715 | d34cab9f | ths | case SVGA_REG_DEPTH:
|
716 | d34cab9f | ths | return s->depth;
|
717 | d34cab9f | ths | |
718 | d34cab9f | ths | case SVGA_REG_BITS_PER_PIXEL:
|
719 | d34cab9f | ths | return (s->depth + 7) & ~7; |
720 | d34cab9f | ths | |
721 | d34cab9f | ths | case SVGA_REG_PSEUDOCOLOR:
|
722 | d34cab9f | ths | return 0x0; |
723 | d34cab9f | ths | |
724 | d34cab9f | ths | case SVGA_REG_RED_MASK:
|
725 | d34cab9f | ths | return s->wred;
|
726 | d34cab9f | ths | case SVGA_REG_GREEN_MASK:
|
727 | d34cab9f | ths | return s->wgreen;
|
728 | d34cab9f | ths | case SVGA_REG_BLUE_MASK:
|
729 | d34cab9f | ths | return s->wblue;
|
730 | d34cab9f | ths | |
731 | d34cab9f | ths | case SVGA_REG_BYTES_PER_LINE:
|
732 | d34cab9f | ths | return ((s->depth + 7) >> 3) * s->new_width; |
733 | d34cab9f | ths | |
734 | 7b619b9a | Avi Kivity | case SVGA_REG_FB_START: {
|
735 | 7b619b9a | Avi Kivity | struct pci_vmsvga_state_s *pci_vmsvga
|
736 | 7b619b9a | Avi Kivity | = container_of(s, struct pci_vmsvga_state_s, chip);
|
737 | 7b619b9a | Avi Kivity | return pci_get_bar_addr(&pci_vmsvga->card, 1); |
738 | 7b619b9a | Avi Kivity | } |
739 | d34cab9f | ths | |
740 | d34cab9f | ths | case SVGA_REG_FB_OFFSET:
|
741 | d34cab9f | ths | return 0x0; |
742 | d34cab9f | ths | |
743 | d34cab9f | ths | case SVGA_REG_VRAM_SIZE:
|
744 | f351d050 | Dave Airlie | return s->vga.vram_size;
|
745 | d34cab9f | ths | |
746 | d34cab9f | ths | case SVGA_REG_FB_SIZE:
|
747 | d34cab9f | ths | return s->fb_size;
|
748 | d34cab9f | ths | |
749 | d34cab9f | ths | case SVGA_REG_CAPABILITIES:
|
750 | d34cab9f | ths | caps = SVGA_CAP_NONE; |
751 | d34cab9f | ths | #ifdef HW_RECT_ACCEL
|
752 | d34cab9f | ths | caps |= SVGA_CAP_RECT_COPY; |
753 | d34cab9f | ths | #endif
|
754 | d34cab9f | ths | #ifdef HW_FILL_ACCEL
|
755 | d34cab9f | ths | caps |= SVGA_CAP_RECT_FILL; |
756 | d34cab9f | ths | #endif
|
757 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
758 | 4e12cd94 | Avi Kivity | if (s->vga.ds->mouse_set)
|
759 | d34cab9f | ths | caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | |
760 | d34cab9f | ths | SVGA_CAP_CURSOR_BYPASS; |
761 | d34cab9f | ths | #endif
|
762 | d34cab9f | ths | return caps;
|
763 | d34cab9f | ths | |
764 | b1950430 | Avi Kivity | case SVGA_REG_MEM_START: {
|
765 | b1950430 | Avi Kivity | struct pci_vmsvga_state_s *pci_vmsvga
|
766 | b1950430 | Avi Kivity | = container_of(s, struct pci_vmsvga_state_s, chip);
|
767 | b1950430 | Avi Kivity | return pci_get_bar_addr(&pci_vmsvga->card, 2); |
768 | b1950430 | Avi Kivity | } |
769 | d34cab9f | ths | |
770 | d34cab9f | ths | case SVGA_REG_MEM_SIZE:
|
771 | f351d050 | Dave Airlie | return s->fifo_size;
|
772 | d34cab9f | ths | |
773 | d34cab9f | ths | case SVGA_REG_CONFIG_DONE:
|
774 | d34cab9f | ths | return s->config;
|
775 | d34cab9f | ths | |
776 | d34cab9f | ths | case SVGA_REG_SYNC:
|
777 | d34cab9f | ths | case SVGA_REG_BUSY:
|
778 | d34cab9f | ths | return s->syncing;
|
779 | d34cab9f | ths | |
780 | d34cab9f | ths | case SVGA_REG_GUEST_ID:
|
781 | d34cab9f | ths | return s->guest;
|
782 | d34cab9f | ths | |
783 | d34cab9f | ths | case SVGA_REG_CURSOR_ID:
|
784 | d34cab9f | ths | return s->cursor.id;
|
785 | d34cab9f | ths | |
786 | d34cab9f | ths | case SVGA_REG_CURSOR_X:
|
787 | d34cab9f | ths | return s->cursor.x;
|
788 | d34cab9f | ths | |
789 | d34cab9f | ths | case SVGA_REG_CURSOR_Y:
|
790 | d34cab9f | ths | return s->cursor.x;
|
791 | d34cab9f | ths | |
792 | d34cab9f | ths | case SVGA_REG_CURSOR_ON:
|
793 | d34cab9f | ths | return s->cursor.on;
|
794 | d34cab9f | ths | |
795 | d34cab9f | ths | case SVGA_REG_HOST_BITS_PER_PIXEL:
|
796 | d34cab9f | ths | return (s->depth + 7) & ~7; |
797 | d34cab9f | ths | |
798 | d34cab9f | ths | case SVGA_REG_SCRATCH_SIZE:
|
799 | d34cab9f | ths | return s->scratch_size;
|
800 | d34cab9f | ths | |
801 | d34cab9f | ths | case SVGA_REG_MEM_REGS:
|
802 | d34cab9f | ths | case SVGA_REG_NUM_DISPLAYS:
|
803 | d34cab9f | ths | case SVGA_REG_PITCHLOCK:
|
804 | d34cab9f | ths | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
805 | d34cab9f | ths | return 0; |
806 | d34cab9f | ths | |
807 | d34cab9f | ths | default:
|
808 | d34cab9f | ths | if (s->index >= SVGA_SCRATCH_BASE &&
|
809 | d34cab9f | ths | s->index < SVGA_SCRATCH_BASE + s->scratch_size) |
810 | d34cab9f | ths | return s->scratch[s->index - SVGA_SCRATCH_BASE];
|
811 | d34cab9f | ths | printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
812 | d34cab9f | ths | } |
813 | d34cab9f | ths | |
814 | d34cab9f | ths | return 0; |
815 | d34cab9f | ths | } |
816 | d34cab9f | ths | |
817 | d34cab9f | ths | static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) |
818 | d34cab9f | ths | { |
819 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
820 | d34cab9f | ths | switch (s->index) {
|
821 | d34cab9f | ths | case SVGA_REG_ID:
|
822 | d34cab9f | ths | if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
|
823 | d34cab9f | ths | s->svgaid = value; |
824 | d34cab9f | ths | break;
|
825 | d34cab9f | ths | |
826 | d34cab9f | ths | case SVGA_REG_ENABLE:
|
827 | f707cfba | balrog | s->enable = value; |
828 | f707cfba | balrog | s->config &= !!value; |
829 | d34cab9f | ths | s->width = -1;
|
830 | d34cab9f | ths | s->height = -1;
|
831 | d34cab9f | ths | s->invalidated = 1;
|
832 | 4e12cd94 | Avi Kivity | s->vga.invalidate(&s->vga); |
833 | b5cc6e32 | Anthony Liguori | if (s->enable) {
|
834 | 9f810beb | Andrzej Zaborowski | s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; |
835 | 9f810beb | Andrzej Zaborowski | vga_dirty_log_stop(&s->vga); |
836 | 9f810beb | Andrzej Zaborowski | } else {
|
837 | 9f810beb | Andrzej Zaborowski | vga_dirty_log_start(&s->vga); |
838 | 9f810beb | Andrzej Zaborowski | } |
839 | d34cab9f | ths | break;
|
840 | d34cab9f | ths | |
841 | d34cab9f | ths | case SVGA_REG_WIDTH:
|
842 | d34cab9f | ths | s->new_width = value; |
843 | d34cab9f | ths | s->invalidated = 1;
|
844 | d34cab9f | ths | break;
|
845 | d34cab9f | ths | |
846 | d34cab9f | ths | case SVGA_REG_HEIGHT:
|
847 | d34cab9f | ths | s->new_height = value; |
848 | d34cab9f | ths | s->invalidated = 1;
|
849 | d34cab9f | ths | break;
|
850 | d34cab9f | ths | |
851 | d34cab9f | ths | case SVGA_REG_DEPTH:
|
852 | d34cab9f | ths | case SVGA_REG_BITS_PER_PIXEL:
|
853 | d34cab9f | ths | if (value != s->depth) {
|
854 | d34cab9f | ths | printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
|
855 | d34cab9f | ths | s->config = 0;
|
856 | d34cab9f | ths | } |
857 | d34cab9f | ths | break;
|
858 | d34cab9f | ths | |
859 | d34cab9f | ths | case SVGA_REG_CONFIG_DONE:
|
860 | d34cab9f | ths | if (value) {
|
861 | f351d050 | Dave Airlie | s->fifo = (uint32_t *) s->fifo_ptr; |
862 | d34cab9f | ths | /* Check range and alignment. */
|
863 | ff9cf2cb | balrog | if ((CMD(min) | CMD(max) |
|
864 | ff9cf2cb | balrog | CMD(next_cmd) | CMD(stop)) & 3)
|
865 | d34cab9f | ths | break;
|
866 | ff9cf2cb | balrog | if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
|
867 | d34cab9f | ths | break;
|
868 | ff9cf2cb | balrog | if (CMD(max) > SVGA_FIFO_SIZE)
|
869 | d34cab9f | ths | break;
|
870 | ff9cf2cb | balrog | if (CMD(max) < CMD(min) + 10 * 1024) |
871 | d34cab9f | ths | break;
|
872 | d34cab9f | ths | } |
873 | f707cfba | balrog | s->config = !!value; |
874 | d34cab9f | ths | break;
|
875 | d34cab9f | ths | |
876 | d34cab9f | ths | case SVGA_REG_SYNC:
|
877 | d34cab9f | ths | s->syncing = 1;
|
878 | d34cab9f | ths | vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
|
879 | d34cab9f | ths | break;
|
880 | d34cab9f | ths | |
881 | d34cab9f | ths | case SVGA_REG_GUEST_ID:
|
882 | d34cab9f | ths | s->guest = value; |
883 | d34cab9f | ths | #ifdef VERBOSE
|
884 | d34cab9f | ths | if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
|
885 | b1503cda | malc | ARRAY_SIZE(vmsvga_guest_id)) |
886 | d34cab9f | ths | printf("%s: guest runs %s.\n", __FUNCTION__,
|
887 | d34cab9f | ths | vmsvga_guest_id[value - GUEST_OS_BASE]); |
888 | d34cab9f | ths | #endif
|
889 | d34cab9f | ths | break;
|
890 | d34cab9f | ths | |
891 | d34cab9f | ths | case SVGA_REG_CURSOR_ID:
|
892 | d34cab9f | ths | s->cursor.id = value; |
893 | d34cab9f | ths | break;
|
894 | d34cab9f | ths | |
895 | d34cab9f | ths | case SVGA_REG_CURSOR_X:
|
896 | d34cab9f | ths | s->cursor.x = value; |
897 | d34cab9f | ths | break;
|
898 | d34cab9f | ths | |
899 | d34cab9f | ths | case SVGA_REG_CURSOR_Y:
|
900 | d34cab9f | ths | s->cursor.y = value; |
901 | d34cab9f | ths | break;
|
902 | d34cab9f | ths | |
903 | d34cab9f | ths | case SVGA_REG_CURSOR_ON:
|
904 | d34cab9f | ths | s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); |
905 | d34cab9f | ths | s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); |
906 | d34cab9f | ths | #ifdef HW_MOUSE_ACCEL
|
907 | 4e12cd94 | Avi Kivity | if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
|
908 | 4e12cd94 | Avi Kivity | s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); |
909 | d34cab9f | ths | #endif
|
910 | d34cab9f | ths | break;
|
911 | d34cab9f | ths | |
912 | d34cab9f | ths | case SVGA_REG_MEM_REGS:
|
913 | d34cab9f | ths | case SVGA_REG_NUM_DISPLAYS:
|
914 | d34cab9f | ths | case SVGA_REG_PITCHLOCK:
|
915 | d34cab9f | ths | case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
|
916 | d34cab9f | ths | break;
|
917 | d34cab9f | ths | |
918 | d34cab9f | ths | default:
|
919 | d34cab9f | ths | if (s->index >= SVGA_SCRATCH_BASE &&
|
920 | d34cab9f | ths | s->index < SVGA_SCRATCH_BASE + s->scratch_size) { |
921 | d34cab9f | ths | s->scratch[s->index - SVGA_SCRATCH_BASE] = value; |
922 | d34cab9f | ths | break;
|
923 | d34cab9f | ths | } |
924 | d34cab9f | ths | printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
|
925 | d34cab9f | ths | } |
926 | d34cab9f | ths | } |
927 | d34cab9f | ths | |
928 | d34cab9f | ths | static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) |
929 | d34cab9f | ths | { |
930 | d34cab9f | ths | printf("%s: what are we supposed to return?\n", __FUNCTION__);
|
931 | d34cab9f | ths | return 0xcafe; |
932 | d34cab9f | ths | } |
933 | d34cab9f | ths | |
934 | d34cab9f | ths | static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) |
935 | d34cab9f | ths | { |
936 | d34cab9f | ths | printf("%s: what are we supposed to do with (%08x)?\n",
|
937 | d34cab9f | ths | __FUNCTION__, data); |
938 | d34cab9f | ths | } |
939 | d34cab9f | ths | |
940 | d34cab9f | ths | static inline void vmsvga_size(struct vmsvga_state_s *s) |
941 | d34cab9f | ths | { |
942 | d34cab9f | ths | if (s->new_width != s->width || s->new_height != s->height) {
|
943 | d34cab9f | ths | s->width = s->new_width; |
944 | d34cab9f | ths | s->height = s->new_height; |
945 | 4e12cd94 | Avi Kivity | qemu_console_resize(s->vga.ds, s->width, s->height); |
946 | d34cab9f | ths | s->invalidated = 1;
|
947 | d34cab9f | ths | } |
948 | d34cab9f | ths | } |
949 | d34cab9f | ths | |
950 | d34cab9f | ths | static void vmsvga_update_display(void *opaque) |
951 | d34cab9f | ths | { |
952 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
953 | d34cab9f | ths | if (!s->enable) {
|
954 | 4e12cd94 | Avi Kivity | s->vga.update(&s->vga); |
955 | d34cab9f | ths | return;
|
956 | d34cab9f | ths | } |
957 | d34cab9f | ths | |
958 | d34cab9f | ths | vmsvga_size(s); |
959 | d34cab9f | ths | |
960 | d34cab9f | ths | vmsvga_fifo_run(s); |
961 | d34cab9f | ths | vmsvga_update_rect_flush(s); |
962 | d34cab9f | ths | |
963 | d34cab9f | ths | /*
|
964 | d34cab9f | ths | * Is it more efficient to look at vram VGA-dirty bits or wait
|
965 | d34cab9f | ths | * for the driver to issue SVGA_CMD_UPDATE?
|
966 | d34cab9f | ths | */
|
967 | d34cab9f | ths | if (s->invalidated) {
|
968 | d34cab9f | ths | s->invalidated = 0;
|
969 | d34cab9f | ths | vmsvga_update_screen(s); |
970 | d34cab9f | ths | } |
971 | d34cab9f | ths | } |
972 | d34cab9f | ths | |
973 | 8a9501ba | Jan Kiszka | static void vmsvga_reset(DeviceState *dev) |
974 | d34cab9f | ths | { |
975 | 8a9501ba | Jan Kiszka | struct pci_vmsvga_state_s *pci =
|
976 | 8a9501ba | Jan Kiszka | DO_UPCAST(struct pci_vmsvga_state_s, card.qdev, dev);
|
977 | 8a9501ba | Jan Kiszka | struct vmsvga_state_s *s = &pci->chip;
|
978 | 8a9501ba | Jan Kiszka | |
979 | d34cab9f | ths | s->index = 0;
|
980 | d34cab9f | ths | s->enable = 0;
|
981 | d34cab9f | ths | s->config = 0;
|
982 | d34cab9f | ths | s->width = -1;
|
983 | d34cab9f | ths | s->height = -1;
|
984 | d34cab9f | ths | s->svgaid = SVGA_ID; |
985 | d34cab9f | ths | s->cursor.on = 0;
|
986 | d34cab9f | ths | s->redraw_fifo_first = 0;
|
987 | d34cab9f | ths | s->redraw_fifo_last = 0;
|
988 | d34cab9f | ths | s->syncing = 0;
|
989 | b5cc6e32 | Anthony Liguori | |
990 | b5cc6e32 | Anthony Liguori | vga_dirty_log_start(&s->vga); |
991 | d34cab9f | ths | } |
992 | d34cab9f | ths | |
993 | d34cab9f | ths | static void vmsvga_invalidate_display(void *opaque) |
994 | d34cab9f | ths | { |
995 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
996 | d34cab9f | ths | if (!s->enable) {
|
997 | 4e12cd94 | Avi Kivity | s->vga.invalidate(&s->vga); |
998 | d34cab9f | ths | return;
|
999 | d34cab9f | ths | } |
1000 | d34cab9f | ths | |
1001 | d34cab9f | ths | s->invalidated = 1;
|
1002 | d34cab9f | ths | } |
1003 | d34cab9f | ths | |
1004 | f707cfba | balrog | /* save the vga display in a PPM image even if no display is
|
1005 | f707cfba | balrog | available */
|
1006 | 45efb161 | Gerd Hoffmann | static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch) |
1007 | d34cab9f | ths | { |
1008 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1009 | d34cab9f | ths | if (!s->enable) {
|
1010 | 45efb161 | Gerd Hoffmann | s->vga.screen_dump(&s->vga, filename, cswitch); |
1011 | d34cab9f | ths | return;
|
1012 | d34cab9f | ths | } |
1013 | d34cab9f | ths | |
1014 | f707cfba | balrog | if (s->depth == 32) { |
1015 | e07d630a | aliguori | DisplaySurface *ds = qemu_create_displaysurface_from(s->width, |
1016 | 4e12cd94 | Avi Kivity | s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr);
|
1017 | e07d630a | aliguori | ppm_save(filename, ds); |
1018 | 7267c094 | Anthony Liguori | g_free(ds); |
1019 | f707cfba | balrog | } |
1020 | d34cab9f | ths | } |
1021 | d34cab9f | ths | |
1022 | c227f099 | Anthony Liguori | static void vmsvga_text_update(void *opaque, console_ch_t *chardata) |
1023 | 4d3b6f6e | balrog | { |
1024 | 467d44b2 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1025 | 4d3b6f6e | balrog | |
1026 | 4e12cd94 | Avi Kivity | if (s->vga.text_update)
|
1027 | 4e12cd94 | Avi Kivity | s->vga.text_update(&s->vga, chardata); |
1028 | 4d3b6f6e | balrog | } |
1029 | 4d3b6f6e | balrog | |
1030 | bacbe284 | Juan Quintela | static int vmsvga_post_load(void *opaque, int version_id) |
1031 | d34cab9f | ths | { |
1032 | bacbe284 | Juan Quintela | struct vmsvga_state_s *s = opaque;
|
1033 | d34cab9f | ths | |
1034 | d34cab9f | ths | s->invalidated = 1;
|
1035 | d34cab9f | ths | if (s->config)
|
1036 | f351d050 | Dave Airlie | s->fifo = (uint32_t *) s->fifo_ptr; |
1037 | d34cab9f | ths | |
1038 | d34cab9f | ths | return 0; |
1039 | d34cab9f | ths | } |
1040 | d34cab9f | ths | |
1041 | d05ac8fa | Blue Swirl | static const VMStateDescription vmstate_vmware_vga_internal = { |
1042 | bacbe284 | Juan Quintela | .name = "vmware_vga_internal",
|
1043 | bacbe284 | Juan Quintela | .version_id = 0,
|
1044 | bacbe284 | Juan Quintela | .minimum_version_id = 0,
|
1045 | bacbe284 | Juan Quintela | .minimum_version_id_old = 0,
|
1046 | bacbe284 | Juan Quintela | .post_load = vmsvga_post_load, |
1047 | bacbe284 | Juan Quintela | .fields = (VMStateField []) { |
1048 | bacbe284 | Juan Quintela | VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
|
1049 | bacbe284 | Juan Quintela | VMSTATE_INT32(enable, struct vmsvga_state_s),
|
1050 | bacbe284 | Juan Quintela | VMSTATE_INT32(config, struct vmsvga_state_s),
|
1051 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
|
1052 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.x, struct vmsvga_state_s),
|
1053 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.y, struct vmsvga_state_s),
|
1054 | bacbe284 | Juan Quintela | VMSTATE_INT32(cursor.on, struct vmsvga_state_s),
|
1055 | bacbe284 | Juan Quintela | VMSTATE_INT32(index, struct vmsvga_state_s),
|
1056 | bacbe284 | Juan Quintela | VMSTATE_VARRAY_INT32(scratch, struct vmsvga_state_s,
|
1057 | bacbe284 | Juan Quintela | scratch_size, 0, vmstate_info_uint32, uint32_t),
|
1058 | bacbe284 | Juan Quintela | VMSTATE_INT32(new_width, struct vmsvga_state_s),
|
1059 | bacbe284 | Juan Quintela | VMSTATE_INT32(new_height, struct vmsvga_state_s),
|
1060 | bacbe284 | Juan Quintela | VMSTATE_UINT32(guest, struct vmsvga_state_s),
|
1061 | bacbe284 | Juan Quintela | VMSTATE_UINT32(svgaid, struct vmsvga_state_s),
|
1062 | bacbe284 | Juan Quintela | VMSTATE_INT32(syncing, struct vmsvga_state_s),
|
1063 | bacbe284 | Juan Quintela | VMSTATE_INT32(fb_size, struct vmsvga_state_s),
|
1064 | bacbe284 | Juan Quintela | VMSTATE_END_OF_LIST() |
1065 | bacbe284 | Juan Quintela | } |
1066 | bacbe284 | Juan Quintela | }; |
1067 | bacbe284 | Juan Quintela | |
1068 | d05ac8fa | Blue Swirl | static const VMStateDescription vmstate_vmware_vga = { |
1069 | bacbe284 | Juan Quintela | .name = "vmware_vga",
|
1070 | bacbe284 | Juan Quintela | .version_id = 0,
|
1071 | bacbe284 | Juan Quintela | .minimum_version_id = 0,
|
1072 | bacbe284 | Juan Quintela | .minimum_version_id_old = 0,
|
1073 | bacbe284 | Juan Quintela | .fields = (VMStateField []) { |
1074 | bacbe284 | Juan Quintela | VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s),
|
1075 | bacbe284 | Juan Quintela | VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, |
1076 | bacbe284 | Juan Quintela | vmstate_vmware_vga_internal, struct vmsvga_state_s),
|
1077 | bacbe284 | Juan Quintela | VMSTATE_END_OF_LIST() |
1078 | bacbe284 | Juan Quintela | } |
1079 | bacbe284 | Juan Quintela | }; |
1080 | bacbe284 | Juan Quintela | |
1081 | be20f9e9 | Avi Kivity | static void vmsvga_init(struct vmsvga_state_s *s, int vga_ram_size, |
1082 | 0a039dc7 | Richard Henderson | MemoryRegion *address_space, MemoryRegion *io) |
1083 | d34cab9f | ths | { |
1084 | d34cab9f | ths | s->scratch_size = SVGA_SCRATCH_SIZE; |
1085 | 7267c094 | Anthony Liguori | s->scratch = g_malloc(s->scratch_size * 4);
|
1086 | d34cab9f | ths | |
1087 | a6109ff1 | Anthony Liguori | s->vga.ds = graphic_console_init(vmsvga_update_display, |
1088 | a6109ff1 | Anthony Liguori | vmsvga_invalidate_display, |
1089 | a6109ff1 | Anthony Liguori | vmsvga_screen_dump, |
1090 | a6109ff1 | Anthony Liguori | vmsvga_text_update, s); |
1091 | a6109ff1 | Anthony Liguori | |
1092 | 4445b0a6 | Andrzej Zaborowski | |
1093 | f351d050 | Dave Airlie | s->fifo_size = SVGA_FIFO_SIZE; |
1094 | c5705a77 | Avi Kivity | memory_region_init_ram(&s->fifo_ram, "vmsvga.fifo", s->fifo_size);
|
1095 | c5705a77 | Avi Kivity | vmstate_register_ram_global(&s->fifo_ram); |
1096 | b1950430 | Avi Kivity | s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); |
1097 | f351d050 | Dave Airlie | |
1098 | a4a2f59c | Juan Quintela | vga_common_init(&s->vga, vga_ram_size); |
1099 | 0a039dc7 | Richard Henderson | vga_init(&s->vga, address_space, io, true);
|
1100 | 0be71e32 | Alex Williamson | vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); |
1101 | e93a5f4f | balrog | |
1102 | 8a9501ba | Jan Kiszka | s->depth = ds_get_bits_per_pixel(s->vga.ds); |
1103 | 8a9501ba | Jan Kiszka | s->bypp = ds_get_bytes_per_pixel(s->vga.ds); |
1104 | 8a9501ba | Jan Kiszka | switch (s->depth) {
|
1105 | 8a9501ba | Jan Kiszka | case 8: |
1106 | 8a9501ba | Jan Kiszka | s->wred = 0x00000007;
|
1107 | 8a9501ba | Jan Kiszka | s->wgreen = 0x00000038;
|
1108 | 8a9501ba | Jan Kiszka | s->wblue = 0x000000c0;
|
1109 | 8a9501ba | Jan Kiszka | break;
|
1110 | 8a9501ba | Jan Kiszka | case 15: |
1111 | 8a9501ba | Jan Kiszka | s->wred = 0x0000001f;
|
1112 | 8a9501ba | Jan Kiszka | s->wgreen = 0x000003e0;
|
1113 | 8a9501ba | Jan Kiszka | s->wblue = 0x00007c00;
|
1114 | 8a9501ba | Jan Kiszka | break;
|
1115 | 8a9501ba | Jan Kiszka | case 16: |
1116 | 8a9501ba | Jan Kiszka | s->wred = 0x0000001f;
|
1117 | 8a9501ba | Jan Kiszka | s->wgreen = 0x000007e0;
|
1118 | 8a9501ba | Jan Kiszka | s->wblue = 0x0000f800;
|
1119 | 8a9501ba | Jan Kiszka | break;
|
1120 | 8a9501ba | Jan Kiszka | case 24: |
1121 | 8a9501ba | Jan Kiszka | s->wred = 0x00ff0000;
|
1122 | 8a9501ba | Jan Kiszka | s->wgreen = 0x0000ff00;
|
1123 | 8a9501ba | Jan Kiszka | s->wblue = 0x000000ff;
|
1124 | 8a9501ba | Jan Kiszka | break;
|
1125 | 8a9501ba | Jan Kiszka | case 32: |
1126 | 8a9501ba | Jan Kiszka | s->wred = 0x00ff0000;
|
1127 | 8a9501ba | Jan Kiszka | s->wgreen = 0x0000ff00;
|
1128 | 8a9501ba | Jan Kiszka | s->wblue = 0x000000ff;
|
1129 | 8a9501ba | Jan Kiszka | break;
|
1130 | 8a9501ba | Jan Kiszka | } |
1131 | d34cab9f | ths | } |
1132 | d34cab9f | ths | |
1133 | b1950430 | Avi Kivity | static uint64_t vmsvga_io_read(void *opaque, target_phys_addr_t addr, |
1134 | b1950430 | Avi Kivity | unsigned size)
|
1135 | 1492a3c4 | balrog | { |
1136 | b1950430 | Avi Kivity | struct vmsvga_state_s *s = opaque;
|
1137 | b1950430 | Avi Kivity | |
1138 | b1950430 | Avi Kivity | switch (addr) {
|
1139 | b1950430 | Avi Kivity | case SVGA_IO_MUL * SVGA_INDEX_PORT: return vmsvga_index_read(s, addr); |
1140 | b1950430 | Avi Kivity | case SVGA_IO_MUL * SVGA_VALUE_PORT: return vmsvga_value_read(s, addr); |
1141 | b1950430 | Avi Kivity | case SVGA_IO_MUL * SVGA_BIOS_PORT: return vmsvga_bios_read(s, addr); |
1142 | b1950430 | Avi Kivity | default: return -1u; |
1143 | b1950430 | Avi Kivity | } |
1144 | 1492a3c4 | balrog | } |
1145 | 1492a3c4 | balrog | |
1146 | b1950430 | Avi Kivity | static void vmsvga_io_write(void *opaque, target_phys_addr_t addr, |
1147 | b1950430 | Avi Kivity | uint64_t data, unsigned size)
|
1148 | 3016d80b | balrog | { |
1149 | b1950430 | Avi Kivity | struct vmsvga_state_s *s = opaque;
|
1150 | ee3e41a9 | Anthony Liguori | |
1151 | b1950430 | Avi Kivity | switch (addr) {
|
1152 | b1950430 | Avi Kivity | case SVGA_IO_MUL * SVGA_INDEX_PORT:
|
1153 | b1950430 | Avi Kivity | return vmsvga_index_write(s, addr, data);
|
1154 | b1950430 | Avi Kivity | case SVGA_IO_MUL * SVGA_VALUE_PORT:
|
1155 | b1950430 | Avi Kivity | return vmsvga_value_write(s, addr, data);
|
1156 | b1950430 | Avi Kivity | case SVGA_IO_MUL * SVGA_BIOS_PORT:
|
1157 | b1950430 | Avi Kivity | return vmsvga_bios_write(s, addr, data);
|
1158 | b1950430 | Avi Kivity | } |
1159 | 3016d80b | balrog | } |
1160 | 3016d80b | balrog | |
1161 | b1950430 | Avi Kivity | static const MemoryRegionOps vmsvga_io_ops = { |
1162 | b1950430 | Avi Kivity | .read = vmsvga_io_read, |
1163 | b1950430 | Avi Kivity | .write = vmsvga_io_write, |
1164 | b1950430 | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
1165 | b1950430 | Avi Kivity | .valid = { |
1166 | b1950430 | Avi Kivity | .min_access_size = 4,
|
1167 | b1950430 | Avi Kivity | .max_access_size = 4,
|
1168 | b1950430 | Avi Kivity | }, |
1169 | b1950430 | Avi Kivity | }; |
1170 | f351d050 | Dave Airlie | |
1171 | 81a322d4 | Gerd Hoffmann | static int pci_vmsvga_initfn(PCIDevice *dev) |
1172 | d34cab9f | ths | { |
1173 | a414c306 | Gerd Hoffmann | struct pci_vmsvga_state_s *s =
|
1174 | a414c306 | Gerd Hoffmann | DO_UPCAST(struct pci_vmsvga_state_s, card, dev);
|
1175 | b1950430 | Avi Kivity | MemoryRegion *iomem; |
1176 | b1950430 | Avi Kivity | |
1177 | b1950430 | Avi Kivity | iomem = &s->chip.vga.vram; |
1178 | b1950430 | Avi Kivity | |
1179 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ |
1180 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ |
1181 | 3fa0f955 | Michael S. Tsirkin | s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ |
1182 | d34cab9f | ths | |
1183 | b1950430 | Avi Kivity | memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip, |
1184 | b1950430 | Avi Kivity | "vmsvga-io", 0x10); |
1185 | e824b2cc | Avi Kivity | pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar);
|
1186 | f351d050 | Dave Airlie | |
1187 | 0a039dc7 | Richard Henderson | vmsvga_init(&s->chip, VGA_RAM_SIZE, pci_address_space(dev), |
1188 | 0a039dc7 | Richard Henderson | pci_address_space_io(dev)); |
1189 | d34cab9f | ths | |
1190 | e824b2cc | Avi Kivity | pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem);
|
1191 | e824b2cc | Avi Kivity | pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH,
|
1192 | e824b2cc | Avi Kivity | &s->chip.fifo_ram); |
1193 | b1950430 | Avi Kivity | |
1194 | 281a26b1 | Gerd Hoffmann | if (!dev->rom_bar) {
|
1195 | 281a26b1 | Gerd Hoffmann | /* compatibility with pc-0.13 and older */
|
1196 | be20f9e9 | Avi Kivity | vga_init_vbe(&s->chip.vga, pci_address_space(dev)); |
1197 | 281a26b1 | Gerd Hoffmann | } |
1198 | 281a26b1 | Gerd Hoffmann | |
1199 | 81a322d4 | Gerd Hoffmann | return 0; |
1200 | d34cab9f | ths | } |
1201 | a414c306 | Gerd Hoffmann | |
1202 | 40021f08 | Anthony Liguori | static void vmsvga_class_init(ObjectClass *klass, void *data) |
1203 | 40021f08 | Anthony Liguori | { |
1204 | 39bffca2 | Anthony Liguori | DeviceClass *dc = DEVICE_CLASS(klass); |
1205 | 40021f08 | Anthony Liguori | PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
1206 | 40021f08 | Anthony Liguori | |
1207 | 40021f08 | Anthony Liguori | k->no_hotplug = 1;
|
1208 | 40021f08 | Anthony Liguori | k->init = pci_vmsvga_initfn; |
1209 | 40021f08 | Anthony Liguori | k->romfile = "vgabios-vmware.bin";
|
1210 | 40021f08 | Anthony Liguori | k->vendor_id = PCI_VENDOR_ID_VMWARE; |
1211 | 40021f08 | Anthony Liguori | k->device_id = SVGA_PCI_DEVICE_ID; |
1212 | 40021f08 | Anthony Liguori | k->class_id = PCI_CLASS_DISPLAY_VGA; |
1213 | 40021f08 | Anthony Liguori | k->subsystem_vendor_id = PCI_VENDOR_ID_VMWARE; |
1214 | 40021f08 | Anthony Liguori | k->subsystem_id = SVGA_PCI_DEVICE_ID; |
1215 | 39bffca2 | Anthony Liguori | dc->reset = vmsvga_reset; |
1216 | 39bffca2 | Anthony Liguori | dc->vmsd = &vmstate_vmware_vga; |
1217 | 40021f08 | Anthony Liguori | } |
1218 | 40021f08 | Anthony Liguori | |
1219 | 39bffca2 | Anthony Liguori | static TypeInfo vmsvga_info = {
|
1220 | 39bffca2 | Anthony Liguori | .name = "vmware-svga",
|
1221 | 39bffca2 | Anthony Liguori | .parent = TYPE_PCI_DEVICE, |
1222 | 39bffca2 | Anthony Liguori | .instance_size = sizeof(struct pci_vmsvga_state_s), |
1223 | 39bffca2 | Anthony Liguori | .class_init = vmsvga_class_init, |
1224 | a414c306 | Gerd Hoffmann | }; |
1225 | a414c306 | Gerd Hoffmann | |
1226 | 83f7d43a | Andreas Färber | static void vmsvga_register_types(void) |
1227 | a414c306 | Gerd Hoffmann | { |
1228 | 39bffca2 | Anthony Liguori | type_register_static(&vmsvga_info); |
1229 | a414c306 | Gerd Hoffmann | } |
1230 | 83f7d43a | Andreas Färber | |
1231 | 83f7d43a | Andreas Färber | type_init(vmsvga_register_types) |