root / hw / mac_dbdma.c @ 0dad6c35
History | View | Annotate | Download (21.4 kB)
1 | 3cbee15b | j_mayer | /*
|
---|---|---|---|
2 | 3cbee15b | j_mayer | * PowerMac descriptor-based DMA emulation
|
3 | 3cbee15b | j_mayer | *
|
4 | 3cbee15b | j_mayer | * Copyright (c) 2005-2007 Fabrice Bellard
|
5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
|
6 | 28ce5ce6 | aurel32 | * Copyright (c) 2009 Laurent Vivier
|
7 | 28ce5ce6 | aurel32 | *
|
8 | 28ce5ce6 | aurel32 | * some parts from linux-2.6.28, arch/powerpc/include/asm/dbdma.h
|
9 | 28ce5ce6 | aurel32 | *
|
10 | 28ce5ce6 | aurel32 | * Definitions for using the Apple Descriptor-Based DMA controller
|
11 | 28ce5ce6 | aurel32 | * in Power Macintosh computers.
|
12 | 28ce5ce6 | aurel32 | *
|
13 | 28ce5ce6 | aurel32 | * Copyright (C) 1996 Paul Mackerras.
|
14 | 28ce5ce6 | aurel32 | *
|
15 | 28ce5ce6 | aurel32 | * some parts from mol 0.9.71
|
16 | 28ce5ce6 | aurel32 | *
|
17 | 28ce5ce6 | aurel32 | * Descriptor based DMA emulation
|
18 | 28ce5ce6 | aurel32 | *
|
19 | 28ce5ce6 | aurel32 | * Copyright (C) 1998-2004 Samuel Rydh (samuel@ibrium.se)
|
20 | 3cbee15b | j_mayer | *
|
21 | 3cbee15b | j_mayer | * Permission is hereby granted, free of charge, to any person obtaining a copy
|
22 | 3cbee15b | j_mayer | * of this software and associated documentation files (the "Software"), to deal
|
23 | 3cbee15b | j_mayer | * in the Software without restriction, including without limitation the rights
|
24 | 3cbee15b | j_mayer | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
25 | 3cbee15b | j_mayer | * copies of the Software, and to permit persons to whom the Software is
|
26 | 3cbee15b | j_mayer | * furnished to do so, subject to the following conditions:
|
27 | 3cbee15b | j_mayer | *
|
28 | 3cbee15b | j_mayer | * The above copyright notice and this permission notice shall be included in
|
29 | 3cbee15b | j_mayer | * all copies or substantial portions of the Software.
|
30 | 3cbee15b | j_mayer | *
|
31 | 3cbee15b | j_mayer | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
32 | 3cbee15b | j_mayer | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
33 | 3cbee15b | j_mayer | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
34 | 3cbee15b | j_mayer | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
35 | 3cbee15b | j_mayer | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
36 | 3cbee15b | j_mayer | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
37 | 3cbee15b | j_mayer | * THE SOFTWARE.
|
38 | 3cbee15b | j_mayer | */
|
39 | 87ecb68b | pbrook | #include "hw.h" |
40 | 28ce5ce6 | aurel32 | #include "isa.h" |
41 | 28ce5ce6 | aurel32 | #include "mac_dbdma.h" |
42 | 3cbee15b | j_mayer | |
43 | ea026b2f | blueswir1 | /* debug DBDMA */
|
44 | ea026b2f | blueswir1 | //#define DEBUG_DBDMA
|
45 | ea026b2f | blueswir1 | |
46 | ea026b2f | blueswir1 | #ifdef DEBUG_DBDMA
|
47 | 001faf32 | Blue Swirl | #define DBDMA_DPRINTF(fmt, ...) \
|
48 | 001faf32 | Blue Swirl | do { printf("DBDMA: " fmt , ## __VA_ARGS__); } while (0) |
49 | ea026b2f | blueswir1 | #else
|
50 | 001faf32 | Blue Swirl | #define DBDMA_DPRINTF(fmt, ...)
|
51 | ea026b2f | blueswir1 | #endif
|
52 | ea026b2f | blueswir1 | |
53 | 28ce5ce6 | aurel32 | /*
|
54 | 28ce5ce6 | aurel32 | */
|
55 | 28ce5ce6 | aurel32 | |
56 | 28ce5ce6 | aurel32 | /*
|
57 | 28ce5ce6 | aurel32 | * DBDMA control/status registers. All little-endian.
|
58 | 28ce5ce6 | aurel32 | */
|
59 | 3cbee15b | j_mayer | |
60 | 28ce5ce6 | aurel32 | #define DBDMA_CONTROL 0x00 |
61 | 28ce5ce6 | aurel32 | #define DBDMA_STATUS 0x01 |
62 | 28ce5ce6 | aurel32 | #define DBDMA_CMDPTR_HI 0x02 |
63 | 28ce5ce6 | aurel32 | #define DBDMA_CMDPTR_LO 0x03 |
64 | 28ce5ce6 | aurel32 | #define DBDMA_INTR_SEL 0x04 |
65 | 28ce5ce6 | aurel32 | #define DBDMA_BRANCH_SEL 0x05 |
66 | 28ce5ce6 | aurel32 | #define DBDMA_WAIT_SEL 0x06 |
67 | 28ce5ce6 | aurel32 | #define DBDMA_XFER_MODE 0x07 |
68 | 28ce5ce6 | aurel32 | #define DBDMA_DATA2PTR_HI 0x08 |
69 | 28ce5ce6 | aurel32 | #define DBDMA_DATA2PTR_LO 0x09 |
70 | 28ce5ce6 | aurel32 | #define DBDMA_RES1 0x0A |
71 | 28ce5ce6 | aurel32 | #define DBDMA_ADDRESS_HI 0x0B |
72 | 28ce5ce6 | aurel32 | #define DBDMA_BRANCH_ADDR_HI 0x0C |
73 | 28ce5ce6 | aurel32 | #define DBDMA_RES2 0x0D |
74 | 28ce5ce6 | aurel32 | #define DBDMA_RES3 0x0E |
75 | 28ce5ce6 | aurel32 | #define DBDMA_RES4 0x0F |
76 | 28ce5ce6 | aurel32 | |
77 | 28ce5ce6 | aurel32 | #define DBDMA_REGS 16 |
78 | 28ce5ce6 | aurel32 | #define DBDMA_SIZE (DBDMA_REGS * sizeof(uint32_t)) |
79 | 28ce5ce6 | aurel32 | |
80 | 28ce5ce6 | aurel32 | #define DBDMA_CHANNEL_SHIFT 7 |
81 | 28ce5ce6 | aurel32 | #define DBDMA_CHANNEL_SIZE (1 << DBDMA_CHANNEL_SHIFT) |
82 | 28ce5ce6 | aurel32 | |
83 | 28ce5ce6 | aurel32 | #define DBDMA_CHANNELS (0x1000 >> DBDMA_CHANNEL_SHIFT) |
84 | 28ce5ce6 | aurel32 | |
85 | 28ce5ce6 | aurel32 | /* Bits in control and status registers */
|
86 | 28ce5ce6 | aurel32 | |
87 | 28ce5ce6 | aurel32 | #define RUN 0x8000 |
88 | 28ce5ce6 | aurel32 | #define PAUSE 0x4000 |
89 | 28ce5ce6 | aurel32 | #define FLUSH 0x2000 |
90 | 28ce5ce6 | aurel32 | #define WAKE 0x1000 |
91 | 28ce5ce6 | aurel32 | #define DEAD 0x0800 |
92 | 28ce5ce6 | aurel32 | #define ACTIVE 0x0400 |
93 | 28ce5ce6 | aurel32 | #define BT 0x0100 |
94 | 28ce5ce6 | aurel32 | #define DEVSTAT 0x00ff |
95 | 28ce5ce6 | aurel32 | |
96 | 28ce5ce6 | aurel32 | /*
|
97 | 28ce5ce6 | aurel32 | * DBDMA command structure. These fields are all little-endian!
|
98 | 28ce5ce6 | aurel32 | */
|
99 | 28ce5ce6 | aurel32 | |
100 | 28ce5ce6 | aurel32 | typedef struct dbdma_cmd { |
101 | 28ce5ce6 | aurel32 | uint16_t req_count; /* requested byte transfer count */
|
102 | 28ce5ce6 | aurel32 | uint16_t command; /* command word (has bit-fields) */
|
103 | 28ce5ce6 | aurel32 | uint32_t phy_addr; /* physical data address */
|
104 | 28ce5ce6 | aurel32 | uint32_t cmd_dep; /* command-dependent field */
|
105 | 28ce5ce6 | aurel32 | uint16_t res_count; /* residual count after completion */
|
106 | 28ce5ce6 | aurel32 | uint16_t xfer_status; /* transfer status */
|
107 | 28ce5ce6 | aurel32 | } dbdma_cmd; |
108 | 28ce5ce6 | aurel32 | |
109 | 28ce5ce6 | aurel32 | /* DBDMA command values in command field */
|
110 | 28ce5ce6 | aurel32 | |
111 | 28ce5ce6 | aurel32 | #define COMMAND_MASK 0xf000 |
112 | 28ce5ce6 | aurel32 | #define OUTPUT_MORE 0x0000 /* transfer memory data to stream */ |
113 | 28ce5ce6 | aurel32 | #define OUTPUT_LAST 0x1000 /* ditto followed by end marker */ |
114 | 28ce5ce6 | aurel32 | #define INPUT_MORE 0x2000 /* transfer stream data to memory */ |
115 | 28ce5ce6 | aurel32 | #define INPUT_LAST 0x3000 /* ditto, expect end marker */ |
116 | 28ce5ce6 | aurel32 | #define STORE_WORD 0x4000 /* write word (4 bytes) to device reg */ |
117 | 28ce5ce6 | aurel32 | #define LOAD_WORD 0x5000 /* read word (4 bytes) from device reg */ |
118 | 28ce5ce6 | aurel32 | #define DBDMA_NOP 0x6000 /* do nothing */ |
119 | 28ce5ce6 | aurel32 | #define DBDMA_STOP 0x7000 /* suspend processing */ |
120 | 28ce5ce6 | aurel32 | |
121 | 28ce5ce6 | aurel32 | /* Key values in command field */
|
122 | 28ce5ce6 | aurel32 | |
123 | 28ce5ce6 | aurel32 | #define KEY_MASK 0x0700 |
124 | 28ce5ce6 | aurel32 | #define KEY_STREAM0 0x0000 /* usual data stream */ |
125 | 28ce5ce6 | aurel32 | #define KEY_STREAM1 0x0100 /* control/status stream */ |
126 | 28ce5ce6 | aurel32 | #define KEY_STREAM2 0x0200 /* device-dependent stream */ |
127 | 28ce5ce6 | aurel32 | #define KEY_STREAM3 0x0300 /* device-dependent stream */ |
128 | 28ce5ce6 | aurel32 | #define KEY_STREAM4 0x0400 /* reserved */ |
129 | 28ce5ce6 | aurel32 | #define KEY_REGS 0x0500 /* device register space */ |
130 | 28ce5ce6 | aurel32 | #define KEY_SYSTEM 0x0600 /* system memory-mapped space */ |
131 | 28ce5ce6 | aurel32 | #define KEY_DEVICE 0x0700 /* device memory-mapped space */ |
132 | 28ce5ce6 | aurel32 | |
133 | 28ce5ce6 | aurel32 | /* Interrupt control values in command field */
|
134 | 28ce5ce6 | aurel32 | |
135 | 28ce5ce6 | aurel32 | #define INTR_MASK 0x0030 |
136 | 28ce5ce6 | aurel32 | #define INTR_NEVER 0x0000 /* don't interrupt */ |
137 | 28ce5ce6 | aurel32 | #define INTR_IFSET 0x0010 /* intr if condition bit is 1 */ |
138 | 28ce5ce6 | aurel32 | #define INTR_IFCLR 0x0020 /* intr if condition bit is 0 */ |
139 | 28ce5ce6 | aurel32 | #define INTR_ALWAYS 0x0030 /* always interrupt */ |
140 | 28ce5ce6 | aurel32 | |
141 | 28ce5ce6 | aurel32 | /* Branch control values in command field */
|
142 | 28ce5ce6 | aurel32 | |
143 | 28ce5ce6 | aurel32 | #define BR_MASK 0x000c |
144 | 28ce5ce6 | aurel32 | #define BR_NEVER 0x0000 /* don't branch */ |
145 | 28ce5ce6 | aurel32 | #define BR_IFSET 0x0004 /* branch if condition bit is 1 */ |
146 | 28ce5ce6 | aurel32 | #define BR_IFCLR 0x0008 /* branch if condition bit is 0 */ |
147 | 28ce5ce6 | aurel32 | #define BR_ALWAYS 0x000c /* always branch */ |
148 | 28ce5ce6 | aurel32 | |
149 | 28ce5ce6 | aurel32 | /* Wait control values in command field */
|
150 | 28ce5ce6 | aurel32 | |
151 | 28ce5ce6 | aurel32 | #define WAIT_MASK 0x0003 |
152 | 28ce5ce6 | aurel32 | #define WAIT_NEVER 0x0000 /* don't wait */ |
153 | 28ce5ce6 | aurel32 | #define WAIT_IFSET 0x0001 /* wait if condition bit is 1 */ |
154 | 28ce5ce6 | aurel32 | #define WAIT_IFCLR 0x0002 /* wait if condition bit is 0 */ |
155 | 28ce5ce6 | aurel32 | #define WAIT_ALWAYS 0x0003 /* always wait */ |
156 | 28ce5ce6 | aurel32 | |
157 | 28ce5ce6 | aurel32 | typedef struct DBDMA_channel { |
158 | 28ce5ce6 | aurel32 | int channel;
|
159 | 28ce5ce6 | aurel32 | uint32_t regs[DBDMA_REGS]; |
160 | 28ce5ce6 | aurel32 | qemu_irq irq; |
161 | b42ec42d | aurel32 | DBDMA_io io; |
162 | b42ec42d | aurel32 | DBDMA_rw rw; |
163 | 862c9280 | aurel32 | DBDMA_flush flush; |
164 | 28ce5ce6 | aurel32 | dbdma_cmd current; |
165 | b42ec42d | aurel32 | int processing;
|
166 | 28ce5ce6 | aurel32 | } DBDMA_channel; |
167 | 28ce5ce6 | aurel32 | |
168 | c20df14b | Juan Quintela | typedef struct { |
169 | 23c5e4ca | Avi Kivity | MemoryRegion mem; |
170 | c20df14b | Juan Quintela | DBDMA_channel channels[DBDMA_CHANNELS]; |
171 | c20df14b | Juan Quintela | } DBDMAState; |
172 | c20df14b | Juan Quintela | |
173 | 28ce5ce6 | aurel32 | #ifdef DEBUG_DBDMA
|
174 | 28ce5ce6 | aurel32 | static void dump_dbdma_cmd(dbdma_cmd *cmd) |
175 | 28ce5ce6 | aurel32 | { |
176 | 28ce5ce6 | aurel32 | printf("dbdma_cmd %p\n", cmd);
|
177 | 28ce5ce6 | aurel32 | printf(" req_count 0x%04x\n", le16_to_cpu(cmd->req_count));
|
178 | 28ce5ce6 | aurel32 | printf(" command 0x%04x\n", le16_to_cpu(cmd->command));
|
179 | 28ce5ce6 | aurel32 | printf(" phy_addr 0x%08x\n", le32_to_cpu(cmd->phy_addr));
|
180 | 28ce5ce6 | aurel32 | printf(" cmd_dep 0x%08x\n", le32_to_cpu(cmd->cmd_dep));
|
181 | 28ce5ce6 | aurel32 | printf(" res_count 0x%04x\n", le16_to_cpu(cmd->res_count));
|
182 | 28ce5ce6 | aurel32 | printf(" xfer_status 0x%04x\n", le16_to_cpu(cmd->xfer_status));
|
183 | 28ce5ce6 | aurel32 | } |
184 | 28ce5ce6 | aurel32 | #else
|
185 | 28ce5ce6 | aurel32 | static void dump_dbdma_cmd(dbdma_cmd *cmd) |
186 | 3cbee15b | j_mayer | { |
187 | 28ce5ce6 | aurel32 | } |
188 | 28ce5ce6 | aurel32 | #endif
|
189 | 28ce5ce6 | aurel32 | static void dbdma_cmdptr_load(DBDMA_channel *ch) |
190 | 28ce5ce6 | aurel32 | { |
191 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("dbdma_cmdptr_load 0x%08x\n",
|
192 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_CMDPTR_LO]); |
193 | ad674e53 | Aurelien Jarno | cpu_physical_memory_read(ch->regs[DBDMA_CMDPTR_LO], |
194 | 28ce5ce6 | aurel32 | (uint8_t*)&ch->current, sizeof(dbdma_cmd));
|
195 | 3cbee15b | j_mayer | } |
196 | 3cbee15b | j_mayer | |
197 | 28ce5ce6 | aurel32 | static void dbdma_cmdptr_save(DBDMA_channel *ch) |
198 | 3cbee15b | j_mayer | { |
199 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("dbdma_cmdptr_save 0x%08x\n",
|
200 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_CMDPTR_LO]); |
201 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("xfer_status 0x%08x res_count 0x%04x\n",
|
202 | 28ce5ce6 | aurel32 | le16_to_cpu(ch->current.xfer_status), |
203 | 28ce5ce6 | aurel32 | le16_to_cpu(ch->current.res_count)); |
204 | ad674e53 | Aurelien Jarno | cpu_physical_memory_write(ch->regs[DBDMA_CMDPTR_LO], |
205 | 28ce5ce6 | aurel32 | (uint8_t*)&ch->current, sizeof(dbdma_cmd));
|
206 | 3cbee15b | j_mayer | } |
207 | 3cbee15b | j_mayer | |
208 | 28ce5ce6 | aurel32 | static void kill_channel(DBDMA_channel *ch) |
209 | 3cbee15b | j_mayer | { |
210 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("kill_channel\n");
|
211 | 28ce5ce6 | aurel32 | |
212 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] |= DEAD; |
213 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] &= ~ACTIVE; |
214 | 28ce5ce6 | aurel32 | |
215 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
216 | 28ce5ce6 | aurel32 | } |
217 | 28ce5ce6 | aurel32 | |
218 | 28ce5ce6 | aurel32 | static void conditional_interrupt(DBDMA_channel *ch) |
219 | 28ce5ce6 | aurel32 | { |
220 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
221 | 28ce5ce6 | aurel32 | uint16_t intr; |
222 | 28ce5ce6 | aurel32 | uint16_t sel_mask, sel_value; |
223 | 28ce5ce6 | aurel32 | uint32_t status; |
224 | 28ce5ce6 | aurel32 | int cond;
|
225 | 28ce5ce6 | aurel32 | |
226 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("conditional_interrupt\n");
|
227 | 28ce5ce6 | aurel32 | |
228 | b42ec42d | aurel32 | intr = le16_to_cpu(current->command) & INTR_MASK; |
229 | 28ce5ce6 | aurel32 | |
230 | 28ce5ce6 | aurel32 | switch(intr) {
|
231 | 28ce5ce6 | aurel32 | case INTR_NEVER: /* don't interrupt */ |
232 | 28ce5ce6 | aurel32 | return;
|
233 | 28ce5ce6 | aurel32 | case INTR_ALWAYS: /* always interrupt */ |
234 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
235 | 28ce5ce6 | aurel32 | return;
|
236 | 28ce5ce6 | aurel32 | } |
237 | 28ce5ce6 | aurel32 | |
238 | ad674e53 | Aurelien Jarno | status = ch->regs[DBDMA_STATUS] & DEVSTAT; |
239 | 28ce5ce6 | aurel32 | |
240 | ad674e53 | Aurelien Jarno | sel_mask = (ch->regs[DBDMA_INTR_SEL] >> 16) & 0x0f; |
241 | ad674e53 | Aurelien Jarno | sel_value = ch->regs[DBDMA_INTR_SEL] & 0x0f;
|
242 | 28ce5ce6 | aurel32 | |
243 | 28ce5ce6 | aurel32 | cond = (status & sel_mask) == (sel_value & sel_mask); |
244 | 28ce5ce6 | aurel32 | |
245 | 28ce5ce6 | aurel32 | switch(intr) {
|
246 | 28ce5ce6 | aurel32 | case INTR_IFSET: /* intr if condition bit is 1 */ |
247 | 28ce5ce6 | aurel32 | if (cond)
|
248 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
249 | 28ce5ce6 | aurel32 | return;
|
250 | 28ce5ce6 | aurel32 | case INTR_IFCLR: /* intr if condition bit is 0 */ |
251 | 28ce5ce6 | aurel32 | if (!cond)
|
252 | 28ce5ce6 | aurel32 | qemu_irq_raise(ch->irq); |
253 | 28ce5ce6 | aurel32 | return;
|
254 | 28ce5ce6 | aurel32 | } |
255 | 28ce5ce6 | aurel32 | } |
256 | 28ce5ce6 | aurel32 | |
257 | 28ce5ce6 | aurel32 | static int conditional_wait(DBDMA_channel *ch) |
258 | 28ce5ce6 | aurel32 | { |
259 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
260 | 28ce5ce6 | aurel32 | uint16_t wait; |
261 | 28ce5ce6 | aurel32 | uint16_t sel_mask, sel_value; |
262 | 28ce5ce6 | aurel32 | uint32_t status; |
263 | 28ce5ce6 | aurel32 | int cond;
|
264 | 28ce5ce6 | aurel32 | |
265 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("conditional_wait\n");
|
266 | 28ce5ce6 | aurel32 | |
267 | b42ec42d | aurel32 | wait = le16_to_cpu(current->command) & WAIT_MASK; |
268 | 28ce5ce6 | aurel32 | |
269 | 28ce5ce6 | aurel32 | switch(wait) {
|
270 | 28ce5ce6 | aurel32 | case WAIT_NEVER: /* don't wait */ |
271 | 28ce5ce6 | aurel32 | return 0; |
272 | 28ce5ce6 | aurel32 | case WAIT_ALWAYS: /* always wait */ |
273 | 28ce5ce6 | aurel32 | return 1; |
274 | 28ce5ce6 | aurel32 | } |
275 | 28ce5ce6 | aurel32 | |
276 | ad674e53 | Aurelien Jarno | status = ch->regs[DBDMA_STATUS] & DEVSTAT; |
277 | 28ce5ce6 | aurel32 | |
278 | ad674e53 | Aurelien Jarno | sel_mask = (ch->regs[DBDMA_WAIT_SEL] >> 16) & 0x0f; |
279 | ad674e53 | Aurelien Jarno | sel_value = ch->regs[DBDMA_WAIT_SEL] & 0x0f;
|
280 | 28ce5ce6 | aurel32 | |
281 | 28ce5ce6 | aurel32 | cond = (status & sel_mask) == (sel_value & sel_mask); |
282 | 28ce5ce6 | aurel32 | |
283 | 28ce5ce6 | aurel32 | switch(wait) {
|
284 | 28ce5ce6 | aurel32 | case WAIT_IFSET: /* wait if condition bit is 1 */ |
285 | 28ce5ce6 | aurel32 | if (cond)
|
286 | 28ce5ce6 | aurel32 | return 1; |
287 | 28ce5ce6 | aurel32 | return 0; |
288 | 28ce5ce6 | aurel32 | case WAIT_IFCLR: /* wait if condition bit is 0 */ |
289 | 28ce5ce6 | aurel32 | if (!cond)
|
290 | 28ce5ce6 | aurel32 | return 1; |
291 | 28ce5ce6 | aurel32 | return 0; |
292 | 28ce5ce6 | aurel32 | } |
293 | 28ce5ce6 | aurel32 | return 0; |
294 | 28ce5ce6 | aurel32 | } |
295 | 28ce5ce6 | aurel32 | |
296 | 28ce5ce6 | aurel32 | static void next(DBDMA_channel *ch) |
297 | 28ce5ce6 | aurel32 | { |
298 | 28ce5ce6 | aurel32 | uint32_t cp; |
299 | 28ce5ce6 | aurel32 | |
300 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] &= ~BT; |
301 | 28ce5ce6 | aurel32 | |
302 | ad674e53 | Aurelien Jarno | cp = ch->regs[DBDMA_CMDPTR_LO]; |
303 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_CMDPTR_LO] = cp + sizeof(dbdma_cmd);
|
304 | 28ce5ce6 | aurel32 | dbdma_cmdptr_load(ch); |
305 | 28ce5ce6 | aurel32 | } |
306 | 28ce5ce6 | aurel32 | |
307 | 28ce5ce6 | aurel32 | static void branch(DBDMA_channel *ch) |
308 | 28ce5ce6 | aurel32 | { |
309 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
310 | 28ce5ce6 | aurel32 | |
311 | 28ce5ce6 | aurel32 | ch->regs[DBDMA_CMDPTR_LO] = current->cmd_dep; |
312 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] |= BT; |
313 | 28ce5ce6 | aurel32 | dbdma_cmdptr_load(ch); |
314 | 28ce5ce6 | aurel32 | } |
315 | 28ce5ce6 | aurel32 | |
316 | 28ce5ce6 | aurel32 | static void conditional_branch(DBDMA_channel *ch) |
317 | 28ce5ce6 | aurel32 | { |
318 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
319 | 28ce5ce6 | aurel32 | uint16_t br; |
320 | 28ce5ce6 | aurel32 | uint16_t sel_mask, sel_value; |
321 | 28ce5ce6 | aurel32 | uint32_t status; |
322 | 28ce5ce6 | aurel32 | int cond;
|
323 | 28ce5ce6 | aurel32 | |
324 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("conditional_branch\n");
|
325 | 28ce5ce6 | aurel32 | |
326 | 28ce5ce6 | aurel32 | /* check if we must branch */
|
327 | 28ce5ce6 | aurel32 | |
328 | b42ec42d | aurel32 | br = le16_to_cpu(current->command) & BR_MASK; |
329 | 28ce5ce6 | aurel32 | |
330 | 28ce5ce6 | aurel32 | switch(br) {
|
331 | 28ce5ce6 | aurel32 | case BR_NEVER: /* don't branch */ |
332 | 28ce5ce6 | aurel32 | next(ch); |
333 | 28ce5ce6 | aurel32 | return;
|
334 | 28ce5ce6 | aurel32 | case BR_ALWAYS: /* always branch */ |
335 | 28ce5ce6 | aurel32 | branch(ch); |
336 | 28ce5ce6 | aurel32 | return;
|
337 | 28ce5ce6 | aurel32 | } |
338 | 28ce5ce6 | aurel32 | |
339 | ad674e53 | Aurelien Jarno | status = ch->regs[DBDMA_STATUS] & DEVSTAT; |
340 | 28ce5ce6 | aurel32 | |
341 | ad674e53 | Aurelien Jarno | sel_mask = (ch->regs[DBDMA_BRANCH_SEL] >> 16) & 0x0f; |
342 | ad674e53 | Aurelien Jarno | sel_value = ch->regs[DBDMA_BRANCH_SEL] & 0x0f;
|
343 | 28ce5ce6 | aurel32 | |
344 | 28ce5ce6 | aurel32 | cond = (status & sel_mask) == (sel_value & sel_mask); |
345 | 28ce5ce6 | aurel32 | |
346 | 28ce5ce6 | aurel32 | switch(br) {
|
347 | 28ce5ce6 | aurel32 | case BR_IFSET: /* branch if condition bit is 1 */ |
348 | 28ce5ce6 | aurel32 | if (cond)
|
349 | 28ce5ce6 | aurel32 | branch(ch); |
350 | 28ce5ce6 | aurel32 | else
|
351 | 28ce5ce6 | aurel32 | next(ch); |
352 | 28ce5ce6 | aurel32 | return;
|
353 | 28ce5ce6 | aurel32 | case BR_IFCLR: /* branch if condition bit is 0 */ |
354 | 28ce5ce6 | aurel32 | if (!cond)
|
355 | 28ce5ce6 | aurel32 | branch(ch); |
356 | 28ce5ce6 | aurel32 | else
|
357 | 28ce5ce6 | aurel32 | next(ch); |
358 | 28ce5ce6 | aurel32 | return;
|
359 | 28ce5ce6 | aurel32 | } |
360 | 28ce5ce6 | aurel32 | } |
361 | 28ce5ce6 | aurel32 | |
362 | b42ec42d | aurel32 | static QEMUBH *dbdma_bh;
|
363 | b42ec42d | aurel32 | static void channel_run(DBDMA_channel *ch); |
364 | 28ce5ce6 | aurel32 | |
365 | b42ec42d | aurel32 | static void dbdma_end(DBDMA_io *io) |
366 | 28ce5ce6 | aurel32 | { |
367 | 28ce5ce6 | aurel32 | DBDMA_channel *ch = io->channel; |
368 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
369 | 28ce5ce6 | aurel32 | |
370 | b42ec42d | aurel32 | if (conditional_wait(ch))
|
371 | b42ec42d | aurel32 | goto wait;
|
372 | 28ce5ce6 | aurel32 | |
373 | ad674e53 | Aurelien Jarno | current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); |
374 | ad674e53 | Aurelien Jarno | current->res_count = cpu_to_le16(io->len); |
375 | b42ec42d | aurel32 | dbdma_cmdptr_save(ch); |
376 | 862c9280 | aurel32 | if (io->is_last)
|
377 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] &= ~FLUSH; |
378 | b42ec42d | aurel32 | |
379 | b42ec42d | aurel32 | conditional_interrupt(ch); |
380 | b42ec42d | aurel32 | conditional_branch(ch); |
381 | 28ce5ce6 | aurel32 | |
382 | b42ec42d | aurel32 | wait:
|
383 | b42ec42d | aurel32 | ch->processing = 0;
|
384 | ad674e53 | Aurelien Jarno | if ((ch->regs[DBDMA_STATUS] & RUN) &&
|
385 | ad674e53 | Aurelien Jarno | (ch->regs[DBDMA_STATUS] & ACTIVE)) |
386 | b42ec42d | aurel32 | channel_run(ch); |
387 | 28ce5ce6 | aurel32 | } |
388 | 28ce5ce6 | aurel32 | |
389 | b42ec42d | aurel32 | static void start_output(DBDMA_channel *ch, int key, uint32_t addr, |
390 | 28ce5ce6 | aurel32 | uint16_t req_count, int is_last)
|
391 | 28ce5ce6 | aurel32 | { |
392 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("start_output\n");
|
393 | 28ce5ce6 | aurel32 | |
394 | 28ce5ce6 | aurel32 | /* KEY_REGS, KEY_DEVICE and KEY_STREAM
|
395 | 28ce5ce6 | aurel32 | * are not implemented in the mac-io chip
|
396 | 28ce5ce6 | aurel32 | */
|
397 | 28ce5ce6 | aurel32 | |
398 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("addr 0x%x key 0x%x\n", addr, key);
|
399 | 28ce5ce6 | aurel32 | if (!addr || key > KEY_STREAM3) {
|
400 | 28ce5ce6 | aurel32 | kill_channel(ch); |
401 | b42ec42d | aurel32 | return;
|
402 | 28ce5ce6 | aurel32 | } |
403 | 28ce5ce6 | aurel32 | |
404 | b42ec42d | aurel32 | ch->io.addr = addr; |
405 | 28ce5ce6 | aurel32 | ch->io.len = req_count; |
406 | 28ce5ce6 | aurel32 | ch->io.is_last = is_last; |
407 | b42ec42d | aurel32 | ch->io.dma_end = dbdma_end; |
408 | b42ec42d | aurel32 | ch->io.is_dma_out = 1;
|
409 | b42ec42d | aurel32 | ch->processing = 1;
|
410 | a9ceb76d | Alexander Graf | if (ch->rw) {
|
411 | a9ceb76d | Alexander Graf | ch->rw(&ch->io); |
412 | a9ceb76d | Alexander Graf | } |
413 | 28ce5ce6 | aurel32 | } |
414 | 28ce5ce6 | aurel32 | |
415 | b42ec42d | aurel32 | static void start_input(DBDMA_channel *ch, int key, uint32_t addr, |
416 | 28ce5ce6 | aurel32 | uint16_t req_count, int is_last)
|
417 | 28ce5ce6 | aurel32 | { |
418 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("start_input\n");
|
419 | 28ce5ce6 | aurel32 | |
420 | 28ce5ce6 | aurel32 | /* KEY_REGS, KEY_DEVICE and KEY_STREAM
|
421 | 28ce5ce6 | aurel32 | * are not implemented in the mac-io chip
|
422 | 28ce5ce6 | aurel32 | */
|
423 | 28ce5ce6 | aurel32 | |
424 | 28ce5ce6 | aurel32 | if (!addr || key > KEY_STREAM3) {
|
425 | 28ce5ce6 | aurel32 | kill_channel(ch); |
426 | b42ec42d | aurel32 | return;
|
427 | 28ce5ce6 | aurel32 | } |
428 | 28ce5ce6 | aurel32 | |
429 | b42ec42d | aurel32 | ch->io.addr = addr; |
430 | 28ce5ce6 | aurel32 | ch->io.len = req_count; |
431 | 28ce5ce6 | aurel32 | ch->io.is_last = is_last; |
432 | b42ec42d | aurel32 | ch->io.dma_end = dbdma_end; |
433 | b42ec42d | aurel32 | ch->io.is_dma_out = 0;
|
434 | b42ec42d | aurel32 | ch->processing = 1;
|
435 | a9ceb76d | Alexander Graf | if (ch->rw) {
|
436 | a9ceb76d | Alexander Graf | ch->rw(&ch->io); |
437 | a9ceb76d | Alexander Graf | } |
438 | 28ce5ce6 | aurel32 | } |
439 | 28ce5ce6 | aurel32 | |
440 | b42ec42d | aurel32 | static void load_word(DBDMA_channel *ch, int key, uint32_t addr, |
441 | 28ce5ce6 | aurel32 | uint16_t len) |
442 | 28ce5ce6 | aurel32 | { |
443 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
444 | 28ce5ce6 | aurel32 | uint32_t val; |
445 | 28ce5ce6 | aurel32 | |
446 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("load_word\n");
|
447 | 28ce5ce6 | aurel32 | |
448 | 28ce5ce6 | aurel32 | /* only implements KEY_SYSTEM */
|
449 | 28ce5ce6 | aurel32 | |
450 | 28ce5ce6 | aurel32 | if (key != KEY_SYSTEM) {
|
451 | 28ce5ce6 | aurel32 | printf("DBDMA: LOAD_WORD, unimplemented key %x\n", key);
|
452 | 28ce5ce6 | aurel32 | kill_channel(ch); |
453 | b42ec42d | aurel32 | return;
|
454 | 28ce5ce6 | aurel32 | } |
455 | 28ce5ce6 | aurel32 | |
456 | 28ce5ce6 | aurel32 | cpu_physical_memory_read(addr, (uint8_t*)&val, len); |
457 | 28ce5ce6 | aurel32 | |
458 | 28ce5ce6 | aurel32 | if (len == 2) |
459 | 28ce5ce6 | aurel32 | val = (val << 16) | (current->cmd_dep & 0x0000ffff); |
460 | 28ce5ce6 | aurel32 | else if (len == 1) |
461 | 28ce5ce6 | aurel32 | val = (val << 24) | (current->cmd_dep & 0x00ffffff); |
462 | 28ce5ce6 | aurel32 | |
463 | 28ce5ce6 | aurel32 | current->cmd_dep = val; |
464 | 28ce5ce6 | aurel32 | |
465 | 28ce5ce6 | aurel32 | if (conditional_wait(ch))
|
466 | b42ec42d | aurel32 | goto wait;
|
467 | 28ce5ce6 | aurel32 | |
468 | ad674e53 | Aurelien Jarno | current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); |
469 | 28ce5ce6 | aurel32 | dbdma_cmdptr_save(ch); |
470 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] &= ~FLUSH; |
471 | 28ce5ce6 | aurel32 | |
472 | 28ce5ce6 | aurel32 | conditional_interrupt(ch); |
473 | 28ce5ce6 | aurel32 | next(ch); |
474 | 28ce5ce6 | aurel32 | |
475 | b42ec42d | aurel32 | wait:
|
476 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
477 | 28ce5ce6 | aurel32 | } |
478 | 28ce5ce6 | aurel32 | |
479 | b42ec42d | aurel32 | static void store_word(DBDMA_channel *ch, int key, uint32_t addr, |
480 | 28ce5ce6 | aurel32 | uint16_t len) |
481 | 28ce5ce6 | aurel32 | { |
482 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
483 | 28ce5ce6 | aurel32 | uint32_t val; |
484 | 28ce5ce6 | aurel32 | |
485 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("store_word\n");
|
486 | 28ce5ce6 | aurel32 | |
487 | 28ce5ce6 | aurel32 | /* only implements KEY_SYSTEM */
|
488 | 28ce5ce6 | aurel32 | |
489 | 28ce5ce6 | aurel32 | if (key != KEY_SYSTEM) {
|
490 | 28ce5ce6 | aurel32 | printf("DBDMA: STORE_WORD, unimplemented key %x\n", key);
|
491 | 28ce5ce6 | aurel32 | kill_channel(ch); |
492 | b42ec42d | aurel32 | return;
|
493 | 28ce5ce6 | aurel32 | } |
494 | 28ce5ce6 | aurel32 | |
495 | 28ce5ce6 | aurel32 | val = current->cmd_dep; |
496 | 28ce5ce6 | aurel32 | if (len == 2) |
497 | 28ce5ce6 | aurel32 | val >>= 16;
|
498 | 28ce5ce6 | aurel32 | else if (len == 1) |
499 | 28ce5ce6 | aurel32 | val >>= 24;
|
500 | 28ce5ce6 | aurel32 | |
501 | 28ce5ce6 | aurel32 | cpu_physical_memory_write(addr, (uint8_t*)&val, len); |
502 | 28ce5ce6 | aurel32 | |
503 | 28ce5ce6 | aurel32 | if (conditional_wait(ch))
|
504 | b42ec42d | aurel32 | goto wait;
|
505 | 28ce5ce6 | aurel32 | |
506 | ad674e53 | Aurelien Jarno | current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); |
507 | 28ce5ce6 | aurel32 | dbdma_cmdptr_save(ch); |
508 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] &= ~FLUSH; |
509 | 28ce5ce6 | aurel32 | |
510 | 28ce5ce6 | aurel32 | conditional_interrupt(ch); |
511 | 28ce5ce6 | aurel32 | next(ch); |
512 | 28ce5ce6 | aurel32 | |
513 | b42ec42d | aurel32 | wait:
|
514 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
515 | 28ce5ce6 | aurel32 | } |
516 | 28ce5ce6 | aurel32 | |
517 | b42ec42d | aurel32 | static void nop(DBDMA_channel *ch) |
518 | 28ce5ce6 | aurel32 | { |
519 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
520 | 28ce5ce6 | aurel32 | |
521 | 28ce5ce6 | aurel32 | if (conditional_wait(ch))
|
522 | b42ec42d | aurel32 | goto wait;
|
523 | 28ce5ce6 | aurel32 | |
524 | ad674e53 | Aurelien Jarno | current->xfer_status = cpu_to_le16(ch->regs[DBDMA_STATUS]); |
525 | 28ce5ce6 | aurel32 | dbdma_cmdptr_save(ch); |
526 | 28ce5ce6 | aurel32 | |
527 | 28ce5ce6 | aurel32 | conditional_interrupt(ch); |
528 | 28ce5ce6 | aurel32 | conditional_branch(ch); |
529 | 28ce5ce6 | aurel32 | |
530 | b42ec42d | aurel32 | wait:
|
531 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
532 | 3cbee15b | j_mayer | } |
533 | 3cbee15b | j_mayer | |
534 | b42ec42d | aurel32 | static void stop(DBDMA_channel *ch) |
535 | 3cbee15b | j_mayer | { |
536 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] &= ~(ACTIVE|DEAD|FLUSH); |
537 | 28ce5ce6 | aurel32 | |
538 | 28ce5ce6 | aurel32 | /* the stop command does not increment command pointer */
|
539 | 3cbee15b | j_mayer | } |
540 | 3cbee15b | j_mayer | |
541 | b42ec42d | aurel32 | static void channel_run(DBDMA_channel *ch) |
542 | 3cbee15b | j_mayer | { |
543 | 28ce5ce6 | aurel32 | dbdma_cmd *current = &ch->current; |
544 | 28ce5ce6 | aurel32 | uint16_t cmd, key; |
545 | 28ce5ce6 | aurel32 | uint16_t req_count; |
546 | 28ce5ce6 | aurel32 | uint32_t phy_addr; |
547 | 28ce5ce6 | aurel32 | |
548 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("channel_run\n");
|
549 | 28ce5ce6 | aurel32 | dump_dbdma_cmd(current); |
550 | 28ce5ce6 | aurel32 | |
551 | 28ce5ce6 | aurel32 | /* clear WAKE flag at command fetch */
|
552 | 28ce5ce6 | aurel32 | |
553 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] &= ~WAKE; |
554 | 28ce5ce6 | aurel32 | |
555 | 28ce5ce6 | aurel32 | cmd = le16_to_cpu(current->command) & COMMAND_MASK; |
556 | 28ce5ce6 | aurel32 | |
557 | 28ce5ce6 | aurel32 | switch (cmd) {
|
558 | 28ce5ce6 | aurel32 | case DBDMA_NOP:
|
559 | b42ec42d | aurel32 | nop(ch); |
560 | b42ec42d | aurel32 | return;
|
561 | 28ce5ce6 | aurel32 | |
562 | 28ce5ce6 | aurel32 | case DBDMA_STOP:
|
563 | b42ec42d | aurel32 | stop(ch); |
564 | b42ec42d | aurel32 | return;
|
565 | 28ce5ce6 | aurel32 | } |
566 | 28ce5ce6 | aurel32 | |
567 | 28ce5ce6 | aurel32 | key = le16_to_cpu(current->command) & 0x0700;
|
568 | 28ce5ce6 | aurel32 | req_count = le16_to_cpu(current->req_count); |
569 | 28ce5ce6 | aurel32 | phy_addr = le32_to_cpu(current->phy_addr); |
570 | 28ce5ce6 | aurel32 | |
571 | 28ce5ce6 | aurel32 | if (key == KEY_STREAM4) {
|
572 | 28ce5ce6 | aurel32 | printf("command %x, invalid key 4\n", cmd);
|
573 | 28ce5ce6 | aurel32 | kill_channel(ch); |
574 | b42ec42d | aurel32 | return;
|
575 | 28ce5ce6 | aurel32 | } |
576 | 28ce5ce6 | aurel32 | |
577 | 28ce5ce6 | aurel32 | switch (cmd) {
|
578 | 28ce5ce6 | aurel32 | case OUTPUT_MORE:
|
579 | b42ec42d | aurel32 | start_output(ch, key, phy_addr, req_count, 0);
|
580 | b42ec42d | aurel32 | return;
|
581 | 28ce5ce6 | aurel32 | |
582 | 28ce5ce6 | aurel32 | case OUTPUT_LAST:
|
583 | b42ec42d | aurel32 | start_output(ch, key, phy_addr, req_count, 1);
|
584 | b42ec42d | aurel32 | return;
|
585 | 28ce5ce6 | aurel32 | |
586 | 28ce5ce6 | aurel32 | case INPUT_MORE:
|
587 | b42ec42d | aurel32 | start_input(ch, key, phy_addr, req_count, 0);
|
588 | b42ec42d | aurel32 | return;
|
589 | 28ce5ce6 | aurel32 | |
590 | 28ce5ce6 | aurel32 | case INPUT_LAST:
|
591 | b42ec42d | aurel32 | start_input(ch, key, phy_addr, req_count, 1);
|
592 | b42ec42d | aurel32 | return;
|
593 | 28ce5ce6 | aurel32 | } |
594 | 28ce5ce6 | aurel32 | |
595 | 28ce5ce6 | aurel32 | if (key < KEY_REGS) {
|
596 | 28ce5ce6 | aurel32 | printf("command %x, invalid key %x\n", cmd, key);
|
597 | 28ce5ce6 | aurel32 | key = KEY_SYSTEM; |
598 | 28ce5ce6 | aurel32 | } |
599 | 28ce5ce6 | aurel32 | |
600 | 28ce5ce6 | aurel32 | /* for LOAD_WORD and STORE_WORD, req_count is on 3 bits
|
601 | 28ce5ce6 | aurel32 | * and BRANCH is invalid
|
602 | 28ce5ce6 | aurel32 | */
|
603 | 28ce5ce6 | aurel32 | |
604 | 28ce5ce6 | aurel32 | req_count = req_count & 0x0007;
|
605 | 28ce5ce6 | aurel32 | if (req_count & 0x4) { |
606 | 28ce5ce6 | aurel32 | req_count = 4;
|
607 | 28ce5ce6 | aurel32 | phy_addr &= ~3;
|
608 | 28ce5ce6 | aurel32 | } else if (req_count & 0x2) { |
609 | 28ce5ce6 | aurel32 | req_count = 2;
|
610 | 28ce5ce6 | aurel32 | phy_addr &= ~1;
|
611 | 28ce5ce6 | aurel32 | } else
|
612 | 28ce5ce6 | aurel32 | req_count = 1;
|
613 | 28ce5ce6 | aurel32 | |
614 | 28ce5ce6 | aurel32 | switch (cmd) {
|
615 | 28ce5ce6 | aurel32 | case LOAD_WORD:
|
616 | b42ec42d | aurel32 | load_word(ch, key, phy_addr, req_count); |
617 | b42ec42d | aurel32 | return;
|
618 | 28ce5ce6 | aurel32 | |
619 | 28ce5ce6 | aurel32 | case STORE_WORD:
|
620 | b42ec42d | aurel32 | store_word(ch, key, phy_addr, req_count); |
621 | b42ec42d | aurel32 | return;
|
622 | 28ce5ce6 | aurel32 | } |
623 | 3cbee15b | j_mayer | } |
624 | 3cbee15b | j_mayer | |
625 | c20df14b | Juan Quintela | static void DBDMA_run(DBDMAState *s) |
626 | 28ce5ce6 | aurel32 | { |
627 | 28ce5ce6 | aurel32 | int channel;
|
628 | 28ce5ce6 | aurel32 | |
629 | c20df14b | Juan Quintela | for (channel = 0; channel < DBDMA_CHANNELS; channel++) { |
630 | c20df14b | Juan Quintela | DBDMA_channel *ch = &s->channels[channel]; |
631 | c20df14b | Juan Quintela | uint32_t status = ch->regs[DBDMA_STATUS]; |
632 | c20df14b | Juan Quintela | if (!ch->processing && (status & RUN) && (status & ACTIVE)) {
|
633 | c20df14b | Juan Quintela | channel_run(ch); |
634 | c20df14b | Juan Quintela | } |
635 | 28ce5ce6 | aurel32 | } |
636 | 28ce5ce6 | aurel32 | } |
637 | 28ce5ce6 | aurel32 | |
638 | 28ce5ce6 | aurel32 | static void DBDMA_run_bh(void *opaque) |
639 | 28ce5ce6 | aurel32 | { |
640 | c20df14b | Juan Quintela | DBDMAState *s = opaque; |
641 | 28ce5ce6 | aurel32 | |
642 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("DBDMA_run_bh\n");
|
643 | 28ce5ce6 | aurel32 | |
644 | c20df14b | Juan Quintela | DBDMA_run(s); |
645 | 28ce5ce6 | aurel32 | } |
646 | 28ce5ce6 | aurel32 | |
647 | 28ce5ce6 | aurel32 | void DBDMA_register_channel(void *dbdma, int nchan, qemu_irq irq, |
648 | 862c9280 | aurel32 | DBDMA_rw rw, DBDMA_flush flush, |
649 | 28ce5ce6 | aurel32 | void *opaque)
|
650 | 28ce5ce6 | aurel32 | { |
651 | c20df14b | Juan Quintela | DBDMAState *s = dbdma; |
652 | c20df14b | Juan Quintela | DBDMA_channel *ch = &s->channels[nchan]; |
653 | 28ce5ce6 | aurel32 | |
654 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("DBDMA_register_channel 0x%x\n", nchan);
|
655 | 28ce5ce6 | aurel32 | |
656 | 28ce5ce6 | aurel32 | ch->irq = irq; |
657 | 28ce5ce6 | aurel32 | ch->channel = nchan; |
658 | b42ec42d | aurel32 | ch->rw = rw; |
659 | 862c9280 | aurel32 | ch->flush = flush; |
660 | 28ce5ce6 | aurel32 | ch->io.opaque = opaque; |
661 | 28ce5ce6 | aurel32 | ch->io.channel = ch; |
662 | 28ce5ce6 | aurel32 | } |
663 | 28ce5ce6 | aurel32 | |
664 | 28ce5ce6 | aurel32 | static void |
665 | 28ce5ce6 | aurel32 | dbdma_control_write(DBDMA_channel *ch) |
666 | 28ce5ce6 | aurel32 | { |
667 | 28ce5ce6 | aurel32 | uint16_t mask, value; |
668 | 28ce5ce6 | aurel32 | uint32_t status; |
669 | 28ce5ce6 | aurel32 | |
670 | ad674e53 | Aurelien Jarno | mask = (ch->regs[DBDMA_CONTROL] >> 16) & 0xffff; |
671 | ad674e53 | Aurelien Jarno | value = ch->regs[DBDMA_CONTROL] & 0xffff;
|
672 | 28ce5ce6 | aurel32 | |
673 | 28ce5ce6 | aurel32 | value &= (RUN | PAUSE | FLUSH | WAKE | DEVSTAT); |
674 | 28ce5ce6 | aurel32 | |
675 | ad674e53 | Aurelien Jarno | status = ch->regs[DBDMA_STATUS]; |
676 | 28ce5ce6 | aurel32 | |
677 | 28ce5ce6 | aurel32 | status = (value & mask) | (status & ~mask); |
678 | 28ce5ce6 | aurel32 | |
679 | 28ce5ce6 | aurel32 | if (status & WAKE)
|
680 | 28ce5ce6 | aurel32 | status |= ACTIVE; |
681 | 28ce5ce6 | aurel32 | if (status & RUN) {
|
682 | 28ce5ce6 | aurel32 | status |= ACTIVE; |
683 | 28ce5ce6 | aurel32 | status &= ~DEAD; |
684 | 28ce5ce6 | aurel32 | } |
685 | 28ce5ce6 | aurel32 | if (status & PAUSE)
|
686 | 28ce5ce6 | aurel32 | status &= ~ACTIVE; |
687 | ad674e53 | Aurelien Jarno | if ((ch->regs[DBDMA_STATUS] & RUN) && !(status & RUN)) {
|
688 | 28ce5ce6 | aurel32 | /* RUN is cleared */
|
689 | 28ce5ce6 | aurel32 | status &= ~(ACTIVE|DEAD); |
690 | 28ce5ce6 | aurel32 | } |
691 | 28ce5ce6 | aurel32 | |
692 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF(" status 0x%08x\n", status);
|
693 | 28ce5ce6 | aurel32 | |
694 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_STATUS] = status; |
695 | 28ce5ce6 | aurel32 | |
696 | b42ec42d | aurel32 | if (status & ACTIVE)
|
697 | b42ec42d | aurel32 | qemu_bh_schedule(dbdma_bh); |
698 | a9ceb76d | Alexander Graf | if ((status & FLUSH) && ch->flush)
|
699 | 862c9280 | aurel32 | ch->flush(&ch->io); |
700 | 28ce5ce6 | aurel32 | } |
701 | 28ce5ce6 | aurel32 | |
702 | 23c5e4ca | Avi Kivity | static void dbdma_write(void *opaque, target_phys_addr_t addr, |
703 | 23c5e4ca | Avi Kivity | uint64_t value, unsigned size)
|
704 | 28ce5ce6 | aurel32 | { |
705 | 28ce5ce6 | aurel32 | int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
706 | c20df14b | Juan Quintela | DBDMAState *s = opaque; |
707 | c20df14b | Juan Quintela | DBDMA_channel *ch = &s->channels[channel]; |
708 | 28ce5ce6 | aurel32 | int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; |
709 | 28ce5ce6 | aurel32 | |
710 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("writel 0x" TARGET_FMT_plx " <= 0x%08x\n", addr, value); |
711 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
|
712 | 28ce5ce6 | aurel32 | (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); |
713 | 28ce5ce6 | aurel32 | |
714 | 28ce5ce6 | aurel32 | /* cmdptr cannot be modified if channel is RUN or ACTIVE */
|
715 | 28ce5ce6 | aurel32 | |
716 | 28ce5ce6 | aurel32 | if (reg == DBDMA_CMDPTR_LO &&
|
717 | ad674e53 | Aurelien Jarno | (ch->regs[DBDMA_STATUS] & (RUN | ACTIVE))) |
718 | 28ce5ce6 | aurel32 | return;
|
719 | 28ce5ce6 | aurel32 | |
720 | 28ce5ce6 | aurel32 | ch->regs[reg] = value; |
721 | 28ce5ce6 | aurel32 | |
722 | 28ce5ce6 | aurel32 | switch(reg) {
|
723 | 28ce5ce6 | aurel32 | case DBDMA_CONTROL:
|
724 | 28ce5ce6 | aurel32 | dbdma_control_write(ch); |
725 | 28ce5ce6 | aurel32 | break;
|
726 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_LO:
|
727 | 28ce5ce6 | aurel32 | /* 16-byte aligned */
|
728 | ad674e53 | Aurelien Jarno | ch->regs[DBDMA_CMDPTR_LO] &= ~0xf;
|
729 | 28ce5ce6 | aurel32 | dbdma_cmdptr_load(ch); |
730 | 28ce5ce6 | aurel32 | break;
|
731 | 28ce5ce6 | aurel32 | case DBDMA_STATUS:
|
732 | 28ce5ce6 | aurel32 | case DBDMA_INTR_SEL:
|
733 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_SEL:
|
734 | 28ce5ce6 | aurel32 | case DBDMA_WAIT_SEL:
|
735 | 28ce5ce6 | aurel32 | /* nothing to do */
|
736 | 28ce5ce6 | aurel32 | break;
|
737 | 28ce5ce6 | aurel32 | case DBDMA_XFER_MODE:
|
738 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_HI:
|
739 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_HI:
|
740 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_LO:
|
741 | 28ce5ce6 | aurel32 | case DBDMA_ADDRESS_HI:
|
742 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_ADDR_HI:
|
743 | 28ce5ce6 | aurel32 | case DBDMA_RES1:
|
744 | 28ce5ce6 | aurel32 | case DBDMA_RES2:
|
745 | 28ce5ce6 | aurel32 | case DBDMA_RES3:
|
746 | 28ce5ce6 | aurel32 | case DBDMA_RES4:
|
747 | 28ce5ce6 | aurel32 | /* unused */
|
748 | 28ce5ce6 | aurel32 | break;
|
749 | 28ce5ce6 | aurel32 | } |
750 | 28ce5ce6 | aurel32 | } |
751 | 28ce5ce6 | aurel32 | |
752 | 23c5e4ca | Avi Kivity | static uint64_t dbdma_read(void *opaque, target_phys_addr_t addr, |
753 | 23c5e4ca | Avi Kivity | unsigned size)
|
754 | 3cbee15b | j_mayer | { |
755 | 28ce5ce6 | aurel32 | uint32_t value; |
756 | 28ce5ce6 | aurel32 | int channel = addr >> DBDMA_CHANNEL_SHIFT;
|
757 | c20df14b | Juan Quintela | DBDMAState *s = opaque; |
758 | c20df14b | Juan Quintela | DBDMA_channel *ch = &s->channels[channel]; |
759 | 28ce5ce6 | aurel32 | int reg = (addr - (channel << DBDMA_CHANNEL_SHIFT)) >> 2; |
760 | ea026b2f | blueswir1 | |
761 | 28ce5ce6 | aurel32 | value = ch->regs[reg]; |
762 | 28ce5ce6 | aurel32 | |
763 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("readl 0x" TARGET_FMT_plx " => 0x%08x\n", addr, value); |
764 | 28ce5ce6 | aurel32 | DBDMA_DPRINTF("channel 0x%x reg 0x%x\n",
|
765 | 28ce5ce6 | aurel32 | (uint32_t)addr >> DBDMA_CHANNEL_SHIFT, reg); |
766 | 28ce5ce6 | aurel32 | |
767 | 28ce5ce6 | aurel32 | switch(reg) {
|
768 | 28ce5ce6 | aurel32 | case DBDMA_CONTROL:
|
769 | 28ce5ce6 | aurel32 | value = 0;
|
770 | 28ce5ce6 | aurel32 | break;
|
771 | 28ce5ce6 | aurel32 | case DBDMA_STATUS:
|
772 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_LO:
|
773 | 28ce5ce6 | aurel32 | case DBDMA_INTR_SEL:
|
774 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_SEL:
|
775 | 28ce5ce6 | aurel32 | case DBDMA_WAIT_SEL:
|
776 | 28ce5ce6 | aurel32 | /* nothing to do */
|
777 | 28ce5ce6 | aurel32 | break;
|
778 | 28ce5ce6 | aurel32 | case DBDMA_XFER_MODE:
|
779 | 28ce5ce6 | aurel32 | case DBDMA_CMDPTR_HI:
|
780 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_HI:
|
781 | 28ce5ce6 | aurel32 | case DBDMA_DATA2PTR_LO:
|
782 | 28ce5ce6 | aurel32 | case DBDMA_ADDRESS_HI:
|
783 | 28ce5ce6 | aurel32 | case DBDMA_BRANCH_ADDR_HI:
|
784 | 28ce5ce6 | aurel32 | /* unused */
|
785 | 28ce5ce6 | aurel32 | value = 0;
|
786 | 28ce5ce6 | aurel32 | break;
|
787 | 28ce5ce6 | aurel32 | case DBDMA_RES1:
|
788 | 28ce5ce6 | aurel32 | case DBDMA_RES2:
|
789 | 28ce5ce6 | aurel32 | case DBDMA_RES3:
|
790 | 28ce5ce6 | aurel32 | case DBDMA_RES4:
|
791 | 28ce5ce6 | aurel32 | /* reserved */
|
792 | 28ce5ce6 | aurel32 | break;
|
793 | 28ce5ce6 | aurel32 | } |
794 | 28ce5ce6 | aurel32 | |
795 | 28ce5ce6 | aurel32 | return value;
|
796 | 3cbee15b | j_mayer | } |
797 | 3cbee15b | j_mayer | |
798 | 23c5e4ca | Avi Kivity | static const MemoryRegionOps dbdma_ops = { |
799 | 23c5e4ca | Avi Kivity | .read = dbdma_read, |
800 | 23c5e4ca | Avi Kivity | .write = dbdma_write, |
801 | 23c5e4ca | Avi Kivity | .endianness = DEVICE_LITTLE_ENDIAN, |
802 | 23c5e4ca | Avi Kivity | .valid = { |
803 | 23c5e4ca | Avi Kivity | .min_access_size = 4,
|
804 | 23c5e4ca | Avi Kivity | .max_access_size = 4,
|
805 | 23c5e4ca | Avi Kivity | }, |
806 | 3cbee15b | j_mayer | }; |
807 | 3cbee15b | j_mayer | |
808 | da26fdc3 | Juan Quintela | static const VMStateDescription vmstate_dbdma_channel = { |
809 | da26fdc3 | Juan Quintela | .name = "dbdma_channel",
|
810 | da26fdc3 | Juan Quintela | .version_id = 0,
|
811 | da26fdc3 | Juan Quintela | .minimum_version_id = 0,
|
812 | da26fdc3 | Juan Quintela | .minimum_version_id_old = 0,
|
813 | da26fdc3 | Juan Quintela | .fields = (VMStateField[]) { |
814 | da26fdc3 | Juan Quintela | VMSTATE_UINT32_ARRAY(regs, struct DBDMA_channel, DBDMA_REGS),
|
815 | da26fdc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
816 | da26fdc3 | Juan Quintela | } |
817 | da26fdc3 | Juan Quintela | }; |
818 | 28ce5ce6 | aurel32 | |
819 | da26fdc3 | Juan Quintela | static const VMStateDescription vmstate_dbdma = { |
820 | da26fdc3 | Juan Quintela | .name = "dbdma",
|
821 | da26fdc3 | Juan Quintela | .version_id = 2,
|
822 | da26fdc3 | Juan Quintela | .minimum_version_id = 2,
|
823 | da26fdc3 | Juan Quintela | .minimum_version_id_old = 2,
|
824 | da26fdc3 | Juan Quintela | .fields = (VMStateField[]) { |
825 | da26fdc3 | Juan Quintela | VMSTATE_STRUCT_ARRAY(channels, DBDMAState, DBDMA_CHANNELS, 1,
|
826 | da26fdc3 | Juan Quintela | vmstate_dbdma_channel, DBDMA_channel), |
827 | da26fdc3 | Juan Quintela | VMSTATE_END_OF_LIST() |
828 | da26fdc3 | Juan Quintela | } |
829 | da26fdc3 | Juan Quintela | }; |
830 | 9b64997f | blueswir1 | |
831 | 6e6b7363 | blueswir1 | static void dbdma_reset(void *opaque) |
832 | 6e6b7363 | blueswir1 | { |
833 | c20df14b | Juan Quintela | DBDMAState *s = opaque; |
834 | 28ce5ce6 | aurel32 | int i;
|
835 | 28ce5ce6 | aurel32 | |
836 | 28ce5ce6 | aurel32 | for (i = 0; i < DBDMA_CHANNELS; i++) |
837 | c20df14b | Juan Quintela | memset(s->channels[i].regs, 0, DBDMA_SIZE);
|
838 | 6e6b7363 | blueswir1 | } |
839 | 6e6b7363 | blueswir1 | |
840 | 23c5e4ca | Avi Kivity | void* DBDMA_init (MemoryRegion **dbdma_mem)
|
841 | 3cbee15b | j_mayer | { |
842 | c20df14b | Juan Quintela | DBDMAState *s; |
843 | 28ce5ce6 | aurel32 | |
844 | 7267c094 | Anthony Liguori | s = g_malloc0(sizeof(DBDMAState));
|
845 | 28ce5ce6 | aurel32 | |
846 | 23c5e4ca | Avi Kivity | memory_region_init_io(&s->mem, &dbdma_ops, s, "dbdma", 0x1000); |
847 | 23c5e4ca | Avi Kivity | *dbdma_mem = &s->mem; |
848 | da26fdc3 | Juan Quintela | vmstate_register(NULL, -1, &vmstate_dbdma, s); |
849 | a08d4367 | Jan Kiszka | qemu_register_reset(dbdma_reset, s); |
850 | 28ce5ce6 | aurel32 | |
851 | 28ce5ce6 | aurel32 | dbdma_bh = qemu_bh_new(DBDMA_run_bh, s); |
852 | 28ce5ce6 | aurel32 | |
853 | 28ce5ce6 | aurel32 | return s;
|
854 | 3cbee15b | j_mayer | } |