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1 | fdf9b3e8 | bellard | /*
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2 | fdf9b3e8 | bellard | * SH4 translation
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3 | 5fafdf24 | ths | *
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4 | fdf9b3e8 | bellard | * Copyright (c) 2005 Samuel Tardieu
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5 | fdf9b3e8 | bellard | *
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6 | fdf9b3e8 | bellard | * This library is free software; you can redistribute it and/or
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7 | fdf9b3e8 | bellard | * modify it under the terms of the GNU Lesser General Public
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8 | fdf9b3e8 | bellard | * License as published by the Free Software Foundation; either
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9 | fdf9b3e8 | bellard | * version 2 of the License, or (at your option) any later version.
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10 | fdf9b3e8 | bellard | *
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11 | fdf9b3e8 | bellard | * This library is distributed in the hope that it will be useful,
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12 | fdf9b3e8 | bellard | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | fdf9b3e8 | bellard | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | fdf9b3e8 | bellard | * Lesser General Public License for more details.
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15 | fdf9b3e8 | bellard | *
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16 | fdf9b3e8 | bellard | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | fdf9b3e8 | bellard | */
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19 | fdf9b3e8 | bellard | #include <stdarg.h> |
20 | fdf9b3e8 | bellard | #include <stdlib.h> |
21 | fdf9b3e8 | bellard | #include <stdio.h> |
22 | fdf9b3e8 | bellard | #include <string.h> |
23 | fdf9b3e8 | bellard | #include <inttypes.h> |
24 | fdf9b3e8 | bellard | |
25 | fdf9b3e8 | bellard | #define DEBUG_DISAS
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26 | fdf9b3e8 | bellard | #define SH4_DEBUG_DISAS
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27 | fdf9b3e8 | bellard | //#define SH4_SINGLE_STEP
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28 | fdf9b3e8 | bellard | |
29 | fdf9b3e8 | bellard | #include "cpu.h" |
30 | fdf9b3e8 | bellard | #include "exec-all.h" |
31 | fdf9b3e8 | bellard | #include "disas.h" |
32 | 57fec1fe | bellard | #include "tcg-op.h" |
33 | ca10f867 | aurel32 | #include "qemu-common.h" |
34 | fdf9b3e8 | bellard | |
35 | a7812ae4 | pbrook | #include "helper.h" |
36 | a7812ae4 | pbrook | #define GEN_HELPER 1 |
37 | a7812ae4 | pbrook | #include "helper.h" |
38 | a7812ae4 | pbrook | |
39 | fdf9b3e8 | bellard | typedef struct DisasContext { |
40 | fdf9b3e8 | bellard | struct TranslationBlock *tb;
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41 | fdf9b3e8 | bellard | target_ulong pc; |
42 | fdf9b3e8 | bellard | uint32_t sr; |
43 | eda9b09b | bellard | uint32_t fpscr; |
44 | fdf9b3e8 | bellard | uint16_t opcode; |
45 | fdf9b3e8 | bellard | uint32_t flags; |
46 | 823029f9 | ths | int bstate;
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47 | fdf9b3e8 | bellard | int memidx;
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48 | fdf9b3e8 | bellard | uint32_t delayed_pc; |
49 | fdf9b3e8 | bellard | int singlestep_enabled;
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50 | 71968fa6 | aurel32 | uint32_t features; |
51 | 852d481f | edgar_igl | int has_movcal;
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52 | fdf9b3e8 | bellard | } DisasContext; |
53 | fdf9b3e8 | bellard | |
54 | fe25591e | aurel32 | #if defined(CONFIG_USER_ONLY)
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55 | fe25591e | aurel32 | #define IS_USER(ctx) 1 |
56 | fe25591e | aurel32 | #else
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57 | fe25591e | aurel32 | #define IS_USER(ctx) (!(ctx->sr & SR_MD))
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58 | fe25591e | aurel32 | #endif
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59 | fe25591e | aurel32 | |
60 | 823029f9 | ths | enum {
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61 | 823029f9 | ths | BS_NONE = 0, /* We go out of the TB without reaching a branch or an |
62 | 823029f9 | ths | * exception condition
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63 | 823029f9 | ths | */
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64 | 823029f9 | ths | BS_STOP = 1, /* We want to stop translation for any reason */ |
65 | 823029f9 | ths | BS_BRANCH = 2, /* We reached a branch condition */ |
66 | 823029f9 | ths | BS_EXCP = 3, /* We reached an exception condition */ |
67 | 823029f9 | ths | }; |
68 | 823029f9 | ths | |
69 | 1e8864f7 | aurel32 | /* global register indexes */
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70 | a7812ae4 | pbrook | static TCGv_ptr cpu_env;
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71 | 1e8864f7 | aurel32 | static TCGv cpu_gregs[24]; |
72 | 3a8a44c4 | aurel32 | static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
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73 | 3a8a44c4 | aurel32 | static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
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74 | 66c7c806 | aurel32 | static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst;
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75 | 66ba317c | aurel32 | static TCGv cpu_fregs[32]; |
76 | 1000822b | aurel32 | |
77 | 1000822b | aurel32 | /* internal register indexes */
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78 | 1000822b | aurel32 | static TCGv cpu_flags, cpu_delayed_pc;
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79 | 1e8864f7 | aurel32 | |
80 | 1a7ff922 | Paolo Bonzini | static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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81 | 1a7ff922 | Paolo Bonzini | |
82 | 2e70f6ef | pbrook | #include "gen-icount.h" |
83 | 2e70f6ef | pbrook | |
84 | a5f1b965 | blueswir1 | static void sh4_translate_init(void) |
85 | 2e70f6ef | pbrook | { |
86 | 1e8864f7 | aurel32 | int i;
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87 | 2e70f6ef | pbrook | static int done_init = 0; |
88 | 559dd74d | aurel32 | static const char * const gregnames[24] = { |
89 | 1e8864f7 | aurel32 | "R0_BANK0", "R1_BANK0", "R2_BANK0", "R3_BANK0", |
90 | 1e8864f7 | aurel32 | "R4_BANK0", "R5_BANK0", "R6_BANK0", "R7_BANK0", |
91 | 1e8864f7 | aurel32 | "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15", |
92 | 1e8864f7 | aurel32 | "R0_BANK1", "R1_BANK1", "R2_BANK1", "R3_BANK1", |
93 | 1e8864f7 | aurel32 | "R4_BANK1", "R5_BANK1", "R6_BANK1", "R7_BANK1" |
94 | 1e8864f7 | aurel32 | }; |
95 | 66ba317c | aurel32 | static const char * const fregnames[32] = { |
96 | 66ba317c | aurel32 | "FPR0_BANK0", "FPR1_BANK0", "FPR2_BANK0", "FPR3_BANK0", |
97 | 66ba317c | aurel32 | "FPR4_BANK0", "FPR5_BANK0", "FPR6_BANK0", "FPR7_BANK0", |
98 | 66ba317c | aurel32 | "FPR8_BANK0", "FPR9_BANK0", "FPR10_BANK0", "FPR11_BANK0", |
99 | 66ba317c | aurel32 | "FPR12_BANK0", "FPR13_BANK0", "FPR14_BANK0", "FPR15_BANK0", |
100 | 66ba317c | aurel32 | "FPR0_BANK1", "FPR1_BANK1", "FPR2_BANK1", "FPR3_BANK1", |
101 | 66ba317c | aurel32 | "FPR4_BANK1", "FPR5_BANK1", "FPR6_BANK1", "FPR7_BANK1", |
102 | 66ba317c | aurel32 | "FPR8_BANK1", "FPR9_BANK1", "FPR10_BANK1", "FPR11_BANK1", |
103 | 66ba317c | aurel32 | "FPR12_BANK1", "FPR13_BANK1", "FPR14_BANK1", "FPR15_BANK1", |
104 | 66ba317c | aurel32 | }; |
105 | 1e8864f7 | aurel32 | |
106 | 2e70f6ef | pbrook | if (done_init)
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107 | 2e70f6ef | pbrook | return;
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108 | 1e8864f7 | aurel32 | |
109 | a7812ae4 | pbrook | cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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110 | 1e8864f7 | aurel32 | |
111 | 1e8864f7 | aurel32 | for (i = 0; i < 24; i++) |
112 | a7812ae4 | pbrook | cpu_gregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
113 | 66ba317c | aurel32 | offsetof(CPUState, gregs[i]), |
114 | 66ba317c | aurel32 | gregnames[i]); |
115 | 988d7eaa | aurel32 | |
116 | a7812ae4 | pbrook | cpu_pc = tcg_global_mem_new_i32(TCG_AREG0, |
117 | a7812ae4 | pbrook | offsetof(CPUState, pc), "PC");
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118 | a7812ae4 | pbrook | cpu_sr = tcg_global_mem_new_i32(TCG_AREG0, |
119 | a7812ae4 | pbrook | offsetof(CPUState, sr), "SR");
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120 | a7812ae4 | pbrook | cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0, |
121 | a7812ae4 | pbrook | offsetof(CPUState, ssr), "SSR");
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122 | a7812ae4 | pbrook | cpu_spc = tcg_global_mem_new_i32(TCG_AREG0, |
123 | a7812ae4 | pbrook | offsetof(CPUState, spc), "SPC");
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124 | a7812ae4 | pbrook | cpu_gbr = tcg_global_mem_new_i32(TCG_AREG0, |
125 | a7812ae4 | pbrook | offsetof(CPUState, gbr), "GBR");
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126 | a7812ae4 | pbrook | cpu_vbr = tcg_global_mem_new_i32(TCG_AREG0, |
127 | a7812ae4 | pbrook | offsetof(CPUState, vbr), "VBR");
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128 | a7812ae4 | pbrook | cpu_sgr = tcg_global_mem_new_i32(TCG_AREG0, |
129 | a7812ae4 | pbrook | offsetof(CPUState, sgr), "SGR");
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130 | a7812ae4 | pbrook | cpu_dbr = tcg_global_mem_new_i32(TCG_AREG0, |
131 | a7812ae4 | pbrook | offsetof(CPUState, dbr), "DBR");
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132 | a7812ae4 | pbrook | cpu_mach = tcg_global_mem_new_i32(TCG_AREG0, |
133 | a7812ae4 | pbrook | offsetof(CPUState, mach), "MACH");
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134 | a7812ae4 | pbrook | cpu_macl = tcg_global_mem_new_i32(TCG_AREG0, |
135 | a7812ae4 | pbrook | offsetof(CPUState, macl), "MACL");
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136 | a7812ae4 | pbrook | cpu_pr = tcg_global_mem_new_i32(TCG_AREG0, |
137 | a7812ae4 | pbrook | offsetof(CPUState, pr), "PR");
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138 | a7812ae4 | pbrook | cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, |
139 | a7812ae4 | pbrook | offsetof(CPUState, fpscr), "FPSCR");
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140 | a7812ae4 | pbrook | cpu_fpul = tcg_global_mem_new_i32(TCG_AREG0, |
141 | a7812ae4 | pbrook | offsetof(CPUState, fpul), "FPUL");
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142 | a7812ae4 | pbrook | |
143 | a7812ae4 | pbrook | cpu_flags = tcg_global_mem_new_i32(TCG_AREG0, |
144 | a7812ae4 | pbrook | offsetof(CPUState, flags), "_flags_");
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145 | a7812ae4 | pbrook | cpu_delayed_pc = tcg_global_mem_new_i32(TCG_AREG0, |
146 | a7812ae4 | pbrook | offsetof(CPUState, delayed_pc), |
147 | a7812ae4 | pbrook | "_delayed_pc_");
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148 | 66c7c806 | aurel32 | cpu_ldst = tcg_global_mem_new_i32(TCG_AREG0, |
149 | 66c7c806 | aurel32 | offsetof(CPUState, ldst), "_ldst_");
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150 | 1000822b | aurel32 | |
151 | 66ba317c | aurel32 | for (i = 0; i < 32; i++) |
152 | 66ba317c | aurel32 | cpu_fregs[i] = tcg_global_mem_new_i32(TCG_AREG0, |
153 | 66ba317c | aurel32 | offsetof(CPUState, fregs[i]), |
154 | 66ba317c | aurel32 | fregnames[i]); |
155 | 66ba317c | aurel32 | |
156 | 988d7eaa | aurel32 | /* register helpers */
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157 | a7812ae4 | pbrook | #define GEN_HELPER 2 |
158 | 988d7eaa | aurel32 | #include "helper.h" |
159 | 988d7eaa | aurel32 | |
160 | 2e70f6ef | pbrook | done_init = 1;
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161 | 2e70f6ef | pbrook | } |
162 | 2e70f6ef | pbrook | |
163 | fdf9b3e8 | bellard | void cpu_dump_state(CPUState * env, FILE * f,
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164 | fdf9b3e8 | bellard | int (*cpu_fprintf) (FILE * f, const char *fmt, ...), |
165 | fdf9b3e8 | bellard | int flags)
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166 | fdf9b3e8 | bellard | { |
167 | fdf9b3e8 | bellard | int i;
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168 | eda9b09b | bellard | cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
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169 | eda9b09b | bellard | env->pc, env->sr, env->pr, env->fpscr); |
170 | 274a9e70 | aurel32 | cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
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171 | 274a9e70 | aurel32 | env->spc, env->ssr, env->gbr, env->vbr); |
172 | 274a9e70 | aurel32 | cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
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173 | 274a9e70 | aurel32 | env->sgr, env->dbr, env->delayed_pc, env->fpul); |
174 | fdf9b3e8 | bellard | for (i = 0; i < 24; i += 4) { |
175 | fdf9b3e8 | bellard | cpu_fprintf(f, "r%d=0x%08x r%d=0x%08x r%d=0x%08x r%d=0x%08x\n",
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176 | fdf9b3e8 | bellard | i, env->gregs[i], i + 1, env->gregs[i + 1], |
177 | fdf9b3e8 | bellard | i + 2, env->gregs[i + 2], i + 3, env->gregs[i + 3]); |
178 | fdf9b3e8 | bellard | } |
179 | fdf9b3e8 | bellard | if (env->flags & DELAY_SLOT) {
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180 | fdf9b3e8 | bellard | cpu_fprintf(f, "in delay slot (delayed_pc=0x%08x)\n",
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181 | fdf9b3e8 | bellard | env->delayed_pc); |
182 | fdf9b3e8 | bellard | } else if (env->flags & DELAY_SLOT_CONDITIONAL) { |
183 | fdf9b3e8 | bellard | cpu_fprintf(f, "in conditional delay slot (delayed_pc=0x%08x)\n",
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184 | fdf9b3e8 | bellard | env->delayed_pc); |
185 | fdf9b3e8 | bellard | } |
186 | fdf9b3e8 | bellard | } |
187 | fdf9b3e8 | bellard | |
188 | 4f6493ff | Aurelien Jarno | void cpu_reset(CPUSH4State * env)
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189 | fdf9b3e8 | bellard | { |
190 | eca1bdf4 | aliguori | if (qemu_loglevel_mask(CPU_LOG_RESET)) {
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191 | eca1bdf4 | aliguori | qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
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192 | eca1bdf4 | aliguori | log_cpu_state(env, 0);
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193 | eca1bdf4 | aliguori | } |
194 | eca1bdf4 | aliguori | |
195 | 4f6493ff | Aurelien Jarno | memset(env, 0, offsetof(CPUSH4State, breakpoints));
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196 | 4f6493ff | Aurelien Jarno | tlb_flush(env, 1);
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197 | 4f6493ff | Aurelien Jarno | |
198 | fdf9b3e8 | bellard | env->pc = 0xA0000000;
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199 | ea6cf6be | ths | #if defined(CONFIG_USER_ONLY)
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200 | ea6cf6be | ths | env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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201 | b0b3de89 | bellard | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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202 | ea6cf6be | ths | #else
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203 | 4f6493ff | Aurelien Jarno | env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0; |
204 | 26ac1ea5 | Aurelien Jarno | env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
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205 | b0b3de89 | bellard | set_float_rounding_mode(float_round_to_zero, &env->fp_status); |
206 | a0d4ac33 | Aurelien Jarno | set_flush_to_zero(1, &env->fp_status);
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207 | ea6cf6be | ths | #endif
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208 | 26ac1ea5 | Aurelien Jarno | set_default_nan_mode(1, &env->fp_status);
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209 | fdf9b3e8 | bellard | } |
210 | fdf9b3e8 | bellard | |
211 | 0fd3ca30 | aurel32 | typedef struct { |
212 | b55266b5 | blueswir1 | const char *name; |
213 | 0fd3ca30 | aurel32 | int id;
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214 | 0fd3ca30 | aurel32 | uint32_t pvr; |
215 | 0fd3ca30 | aurel32 | uint32_t prr; |
216 | 0fd3ca30 | aurel32 | uint32_t cvr; |
217 | 71968fa6 | aurel32 | uint32_t features; |
218 | 0fd3ca30 | aurel32 | } sh4_def_t; |
219 | 0fd3ca30 | aurel32 | |
220 | 0fd3ca30 | aurel32 | static sh4_def_t sh4_defs[] = {
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221 | 0fd3ca30 | aurel32 | { |
222 | 0fd3ca30 | aurel32 | .name = "SH7750R",
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223 | 0fd3ca30 | aurel32 | .id = SH_CPU_SH7750R, |
224 | 0fd3ca30 | aurel32 | .pvr = 0x00050000,
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225 | 0fd3ca30 | aurel32 | .prr = 0x00000100,
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226 | 0fd3ca30 | aurel32 | .cvr = 0x00110000,
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227 | c2432a42 | aurel32 | .features = SH_FEATURE_BCR3_AND_BCR4, |
228 | 0fd3ca30 | aurel32 | }, { |
229 | 0fd3ca30 | aurel32 | .name = "SH7751R",
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230 | 0fd3ca30 | aurel32 | .id = SH_CPU_SH7751R, |
231 | 0fd3ca30 | aurel32 | .pvr = 0x04050005,
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232 | 0fd3ca30 | aurel32 | .prr = 0x00000113,
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233 | 0fd3ca30 | aurel32 | .cvr = 0x00110000, /* Neutered caches, should be 0x20480000 */ |
234 | c2432a42 | aurel32 | .features = SH_FEATURE_BCR3_AND_BCR4, |
235 | a9c43f8e | aurel32 | }, { |
236 | a9c43f8e | aurel32 | .name = "SH7785",
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237 | a9c43f8e | aurel32 | .id = SH_CPU_SH7785, |
238 | a9c43f8e | aurel32 | .pvr = 0x10300700,
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239 | a9c43f8e | aurel32 | .prr = 0x00000200,
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240 | a9c43f8e | aurel32 | .cvr = 0x71440211,
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241 | 71968fa6 | aurel32 | .features = SH_FEATURE_SH4A, |
242 | a9c43f8e | aurel32 | }, |
243 | 0fd3ca30 | aurel32 | }; |
244 | 0fd3ca30 | aurel32 | |
245 | b55266b5 | blueswir1 | static const sh4_def_t *cpu_sh4_find_by_name(const char *name) |
246 | 0fd3ca30 | aurel32 | { |
247 | 0fd3ca30 | aurel32 | int i;
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248 | 0fd3ca30 | aurel32 | |
249 | 0fd3ca30 | aurel32 | if (strcasecmp(name, "any") == 0) |
250 | 0fd3ca30 | aurel32 | return &sh4_defs[0]; |
251 | 0fd3ca30 | aurel32 | |
252 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(sh4_defs); i++) |
253 | 0fd3ca30 | aurel32 | if (strcasecmp(name, sh4_defs[i].name) == 0) |
254 | 0fd3ca30 | aurel32 | return &sh4_defs[i];
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255 | 0fd3ca30 | aurel32 | |
256 | 0fd3ca30 | aurel32 | return NULL; |
257 | 0fd3ca30 | aurel32 | } |
258 | 0fd3ca30 | aurel32 | |
259 | 9a78eead | Stefan Weil | void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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260 | 0fd3ca30 | aurel32 | { |
261 | 0fd3ca30 | aurel32 | int i;
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262 | 0fd3ca30 | aurel32 | |
263 | b1503cda | malc | for (i = 0; i < ARRAY_SIZE(sh4_defs); i++) |
264 | 0fd3ca30 | aurel32 | (*cpu_fprintf)(f, "%s\n", sh4_defs[i].name);
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265 | 0fd3ca30 | aurel32 | } |
266 | 0fd3ca30 | aurel32 | |
267 | 4f6493ff | Aurelien Jarno | static void cpu_register(CPUSH4State *env, const sh4_def_t *def) |
268 | 0fd3ca30 | aurel32 | { |
269 | 0fd3ca30 | aurel32 | env->pvr = def->pvr; |
270 | 0fd3ca30 | aurel32 | env->prr = def->prr; |
271 | 0fd3ca30 | aurel32 | env->cvr = def->cvr; |
272 | 0fd3ca30 | aurel32 | env->id = def->id; |
273 | 0fd3ca30 | aurel32 | } |
274 | 0fd3ca30 | aurel32 | |
275 | aaed909a | bellard | CPUSH4State *cpu_sh4_init(const char *cpu_model) |
276 | fdf9b3e8 | bellard | { |
277 | fdf9b3e8 | bellard | CPUSH4State *env; |
278 | 0fd3ca30 | aurel32 | const sh4_def_t *def;
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279 | fdf9b3e8 | bellard | |
280 | 0fd3ca30 | aurel32 | def = cpu_sh4_find_by_name(cpu_model); |
281 | 0fd3ca30 | aurel32 | if (!def)
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282 | 0fd3ca30 | aurel32 | return NULL; |
283 | fdf9b3e8 | bellard | env = qemu_mallocz(sizeof(CPUSH4State));
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284 | 71968fa6 | aurel32 | env->features = def->features; |
285 | fdf9b3e8 | bellard | cpu_exec_init(env); |
286 | 852d481f | edgar_igl | env->movcal_backup_tail = &(env->movcal_backup); |
287 | 2e70f6ef | pbrook | sh4_translate_init(); |
288 | 7478757e | aurel32 | env->cpu_model_str = cpu_model; |
289 | 4f6493ff | Aurelien Jarno | cpu_reset(env); |
290 | 4f6493ff | Aurelien Jarno | cpu_register(env, def); |
291 | 0bf46a40 | aliguori | qemu_init_vcpu(env); |
292 | fdf9b3e8 | bellard | return env;
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293 | fdf9b3e8 | bellard | } |
294 | fdf9b3e8 | bellard | |
295 | fdf9b3e8 | bellard | static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) |
296 | fdf9b3e8 | bellard | { |
297 | fdf9b3e8 | bellard | TranslationBlock *tb; |
298 | fdf9b3e8 | bellard | tb = ctx->tb; |
299 | fdf9b3e8 | bellard | |
300 | fdf9b3e8 | bellard | if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
|
301 | fdf9b3e8 | bellard | !ctx->singlestep_enabled) { |
302 | fdf9b3e8 | bellard | /* Use a direct jump if in same page and singlestep not enabled */
|
303 | 57fec1fe | bellard | tcg_gen_goto_tb(n); |
304 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
305 | 57fec1fe | bellard | tcg_gen_exit_tb((long) tb + n);
|
306 | fdf9b3e8 | bellard | } else {
|
307 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, dest); |
308 | 57fec1fe | bellard | if (ctx->singlestep_enabled)
|
309 | a7812ae4 | pbrook | gen_helper_debug(); |
310 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
311 | fdf9b3e8 | bellard | } |
312 | fdf9b3e8 | bellard | } |
313 | fdf9b3e8 | bellard | |
314 | fdf9b3e8 | bellard | static void gen_jump(DisasContext * ctx) |
315 | fdf9b3e8 | bellard | { |
316 | fdf9b3e8 | bellard | if (ctx->delayed_pc == (uint32_t) - 1) { |
317 | fdf9b3e8 | bellard | /* Target is not statically known, it comes necessarily from a
|
318 | fdf9b3e8 | bellard | delayed jump as immediate jump are conditinal jumps */
|
319 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_pc, cpu_delayed_pc); |
320 | fdf9b3e8 | bellard | if (ctx->singlestep_enabled)
|
321 | a7812ae4 | pbrook | gen_helper_debug(); |
322 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
323 | fdf9b3e8 | bellard | } else {
|
324 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ctx->delayed_pc);
|
325 | fdf9b3e8 | bellard | } |
326 | fdf9b3e8 | bellard | } |
327 | fdf9b3e8 | bellard | |
328 | 1000822b | aurel32 | static inline void gen_branch_slot(uint32_t delayed_pc, int t) |
329 | 1000822b | aurel32 | { |
330 | c55497ec | aurel32 | TCGv sr; |
331 | 1000822b | aurel32 | int label = gen_new_label();
|
332 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc); |
333 | a7812ae4 | pbrook | sr = tcg_temp_new(); |
334 | c55497ec | aurel32 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
335 | 6f396c8f | Aurelien Jarno | tcg_gen_brcondi_i32(t ? TCG_COND_EQ:TCG_COND_NE, sr, 0, label);
|
336 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
337 | 1000822b | aurel32 | gen_set_label(label); |
338 | 1000822b | aurel32 | } |
339 | 1000822b | aurel32 | |
340 | fdf9b3e8 | bellard | /* Immediate conditional jump (bt or bf) */
|
341 | fdf9b3e8 | bellard | static void gen_conditional_jump(DisasContext * ctx, |
342 | fdf9b3e8 | bellard | target_ulong ift, target_ulong ifnott) |
343 | fdf9b3e8 | bellard | { |
344 | fdf9b3e8 | bellard | int l1;
|
345 | c55497ec | aurel32 | TCGv sr; |
346 | fdf9b3e8 | bellard | |
347 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
348 | a7812ae4 | pbrook | sr = tcg_temp_new(); |
349 | c55497ec | aurel32 | tcg_gen_andi_i32(sr, cpu_sr, SR_T); |
350 | 6f396c8f | Aurelien Jarno | tcg_gen_brcondi_i32(TCG_COND_NE, sr, 0, l1);
|
351 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 0, ifnott);
|
352 | fdf9b3e8 | bellard | gen_set_label(l1); |
353 | fdf9b3e8 | bellard | gen_goto_tb(ctx, 1, ift);
|
354 | fdf9b3e8 | bellard | } |
355 | fdf9b3e8 | bellard | |
356 | fdf9b3e8 | bellard | /* Delayed conditional jump (bt or bf) */
|
357 | fdf9b3e8 | bellard | static void gen_delayed_conditional_jump(DisasContext * ctx) |
358 | fdf9b3e8 | bellard | { |
359 | fdf9b3e8 | bellard | int l1;
|
360 | c55497ec | aurel32 | TCGv ds; |
361 | fdf9b3e8 | bellard | |
362 | fdf9b3e8 | bellard | l1 = gen_new_label(); |
363 | a7812ae4 | pbrook | ds = tcg_temp_new(); |
364 | c55497ec | aurel32 | tcg_gen_andi_i32(ds, cpu_flags, DELAY_SLOT_TRUE); |
365 | 6f396c8f | Aurelien Jarno | tcg_gen_brcondi_i32(TCG_COND_NE, ds, 0, l1);
|
366 | 823029f9 | ths | gen_goto_tb(ctx, 1, ctx->pc + 2); |
367 | fdf9b3e8 | bellard | gen_set_label(l1); |
368 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, ~DELAY_SLOT_TRUE); |
369 | 9c2a9ea1 | pbrook | gen_jump(ctx); |
370 | fdf9b3e8 | bellard | } |
371 | fdf9b3e8 | bellard | |
372 | a4625612 | aurel32 | static inline void gen_set_t(void) |
373 | a4625612 | aurel32 | { |
374 | a4625612 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T); |
375 | a4625612 | aurel32 | } |
376 | a4625612 | aurel32 | |
377 | a4625612 | aurel32 | static inline void gen_clr_t(void) |
378 | a4625612 | aurel32 | { |
379 | a4625612 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
380 | a4625612 | aurel32 | } |
381 | a4625612 | aurel32 | |
382 | a4625612 | aurel32 | static inline void gen_cmp(int cond, TCGv t0, TCGv t1) |
383 | a4625612 | aurel32 | { |
384 | c5c19137 | Aurelien Jarno | TCGv t; |
385 | c5c19137 | Aurelien Jarno | |
386 | c5c19137 | Aurelien Jarno | t = tcg_temp_new(); |
387 | c5c19137 | Aurelien Jarno | tcg_gen_setcond_i32(cond, t, t1, t0); |
388 | c5c19137 | Aurelien Jarno | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
389 | c5c19137 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, t); |
390 | c5c19137 | Aurelien Jarno | |
391 | c5c19137 | Aurelien Jarno | tcg_temp_free(t); |
392 | a4625612 | aurel32 | } |
393 | a4625612 | aurel32 | |
394 | a4625612 | aurel32 | static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm) |
395 | a4625612 | aurel32 | { |
396 | c5c19137 | Aurelien Jarno | TCGv t; |
397 | c5c19137 | Aurelien Jarno | |
398 | c5c19137 | Aurelien Jarno | t = tcg_temp_new(); |
399 | c5c19137 | Aurelien Jarno | tcg_gen_setcondi_i32(cond, t, t0, imm); |
400 | c5c19137 | Aurelien Jarno | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
401 | c5c19137 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, t); |
402 | c5c19137 | Aurelien Jarno | |
403 | c5c19137 | Aurelien Jarno | tcg_temp_free(t); |
404 | a4625612 | aurel32 | } |
405 | a4625612 | aurel32 | |
406 | 1000822b | aurel32 | static inline void gen_store_flags(uint32_t flags) |
407 | 1000822b | aurel32 | { |
408 | 1000822b | aurel32 | tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE); |
409 | 1000822b | aurel32 | tcg_gen_ori_i32(cpu_flags, cpu_flags, flags); |
410 | 1000822b | aurel32 | } |
411 | 1000822b | aurel32 | |
412 | 69d6275b | aurel32 | static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1) |
413 | 69d6275b | aurel32 | { |
414 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
415 | 69d6275b | aurel32 | |
416 | 69d6275b | aurel32 | p0 &= 0x1f;
|
417 | 69d6275b | aurel32 | p1 &= 0x1f;
|
418 | 69d6275b | aurel32 | |
419 | 69d6275b | aurel32 | tcg_gen_andi_i32(tmp, t1, (1 << p1));
|
420 | 69d6275b | aurel32 | tcg_gen_andi_i32(t0, t0, ~(1 << p0));
|
421 | 69d6275b | aurel32 | if (p0 < p1)
|
422 | 69d6275b | aurel32 | tcg_gen_shri_i32(tmp, tmp, p1 - p0); |
423 | 69d6275b | aurel32 | else if (p0 > p1) |
424 | 69d6275b | aurel32 | tcg_gen_shli_i32(tmp, tmp, p0 - p1); |
425 | 69d6275b | aurel32 | tcg_gen_or_i32(t0, t0, tmp); |
426 | 69d6275b | aurel32 | |
427 | 69d6275b | aurel32 | tcg_temp_free(tmp); |
428 | 69d6275b | aurel32 | } |
429 | 69d6275b | aurel32 | |
430 | a7812ae4 | pbrook | static inline void gen_load_fpr64(TCGv_i64 t, int reg) |
431 | cc4ba6a9 | aurel32 | { |
432 | 66ba317c | aurel32 | tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
|
433 | cc4ba6a9 | aurel32 | } |
434 | cc4ba6a9 | aurel32 | |
435 | a7812ae4 | pbrook | static inline void gen_store_fpr64 (TCGv_i64 t, int reg) |
436 | cc4ba6a9 | aurel32 | { |
437 | a7812ae4 | pbrook | TCGv_i32 tmp = tcg_temp_new_i32(); |
438 | cc4ba6a9 | aurel32 | tcg_gen_trunc_i64_i32(tmp, t); |
439 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp);
|
440 | cc4ba6a9 | aurel32 | tcg_gen_shri_i64(t, t, 32);
|
441 | cc4ba6a9 | aurel32 | tcg_gen_trunc_i64_i32(tmp, t); |
442 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[reg], tmp); |
443 | a7812ae4 | pbrook | tcg_temp_free_i32(tmp); |
444 | cc4ba6a9 | aurel32 | } |
445 | cc4ba6a9 | aurel32 | |
446 | fdf9b3e8 | bellard | #define B3_0 (ctx->opcode & 0xf) |
447 | fdf9b3e8 | bellard | #define B6_4 ((ctx->opcode >> 4) & 0x7) |
448 | fdf9b3e8 | bellard | #define B7_4 ((ctx->opcode >> 4) & 0xf) |
449 | fdf9b3e8 | bellard | #define B7_0 (ctx->opcode & 0xff) |
450 | fdf9b3e8 | bellard | #define B7_0s ((int32_t) (int8_t) (ctx->opcode & 0xff)) |
451 | fdf9b3e8 | bellard | #define B11_0s (ctx->opcode & 0x800 ? 0xfffff000 | (ctx->opcode & 0xfff) : \ |
452 | fdf9b3e8 | bellard | (ctx->opcode & 0xfff))
|
453 | fdf9b3e8 | bellard | #define B11_8 ((ctx->opcode >> 8) & 0xf) |
454 | fdf9b3e8 | bellard | #define B15_12 ((ctx->opcode >> 12) & 0xf) |
455 | fdf9b3e8 | bellard | |
456 | fdf9b3e8 | bellard | #define REG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB) ? \ |
457 | 7efbe241 | aurel32 | (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
458 | fdf9b3e8 | bellard | |
459 | fdf9b3e8 | bellard | #define ALTREG(x) ((x) < 8 && (ctx->sr & (SR_MD | SR_RB)) != (SR_MD | SR_RB) \ |
460 | 7efbe241 | aurel32 | ? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
461 | fdf9b3e8 | bellard | |
462 | eda9b09b | bellard | #define FREG(x) (ctx->fpscr & FPSCR_FR ? (x) ^ 0x10 : (x)) |
463 | f09111e0 | ths | #define XHACK(x) ((((x) & 1 ) << 4) | ((x) & 0xe)) |
464 | eda9b09b | bellard | #define XREG(x) (ctx->fpscr & FPSCR_FR ? XHACK(x) ^ 0x10 : XHACK(x)) |
465 | ea6cf6be | ths | #define DREG(x) FREG(x) /* Assumes lsb of (x) is always 0 */ |
466 | eda9b09b | bellard | |
467 | fdf9b3e8 | bellard | #define CHECK_NOT_DELAY_SLOT \
|
468 | d8299bcc | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) \
|
469 | d8299bcc | aurel32 | { \ |
470 | d8299bcc | aurel32 | gen_helper_raise_slot_illegal_instruction(); \ |
471 | d8299bcc | aurel32 | ctx->bstate = BS_EXCP; \ |
472 | d8299bcc | aurel32 | return; \
|
473 | d8299bcc | aurel32 | } |
474 | fdf9b3e8 | bellard | |
475 | 86865c5f | Aurelien Jarno | #define CHECK_PRIVILEGED \
|
476 | 86865c5f | Aurelien Jarno | if (IS_USER(ctx)) { \
|
477 | 86865c5f | Aurelien Jarno | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
|
478 | 86865c5f | Aurelien Jarno | gen_helper_raise_slot_illegal_instruction(); \ |
479 | 86865c5f | Aurelien Jarno | } else { \
|
480 | 86865c5f | Aurelien Jarno | gen_helper_raise_illegal_instruction(); \ |
481 | 86865c5f | Aurelien Jarno | } \ |
482 | 86865c5f | Aurelien Jarno | ctx->bstate = BS_EXCP; \ |
483 | 86865c5f | Aurelien Jarno | return; \
|
484 | fe25591e | aurel32 | } |
485 | fe25591e | aurel32 | |
486 | d8299bcc | aurel32 | #define CHECK_FPU_ENABLED \
|
487 | d8299bcc | aurel32 | if (ctx->flags & SR_FD) { \
|
488 | d8299bcc | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
|
489 | d8299bcc | aurel32 | gen_helper_raise_slot_fpu_disable(); \ |
490 | d8299bcc | aurel32 | } else { \
|
491 | d8299bcc | aurel32 | gen_helper_raise_fpu_disable(); \ |
492 | d8299bcc | aurel32 | } \ |
493 | d8299bcc | aurel32 | ctx->bstate = BS_EXCP; \ |
494 | d8299bcc | aurel32 | return; \
|
495 | d8299bcc | aurel32 | } |
496 | d8299bcc | aurel32 | |
497 | b1d8e52e | blueswir1 | static void _decode_opc(DisasContext * ctx) |
498 | fdf9b3e8 | bellard | { |
499 | 852d481f | edgar_igl | /* This code tries to make movcal emulation sufficiently
|
500 | 852d481f | edgar_igl | accurate for Linux purposes. This instruction writes
|
501 | 852d481f | edgar_igl | memory, and prior to that, always allocates a cache line.
|
502 | 852d481f | edgar_igl | It is used in two contexts:
|
503 | 852d481f | edgar_igl | - in memcpy, where data is copied in blocks, the first write
|
504 | 852d481f | edgar_igl | of to a block uses movca.l for performance.
|
505 | 852d481f | edgar_igl | - in arch/sh/mm/cache-sh4.c, movcal.l + ocbi combination is used
|
506 | 852d481f | edgar_igl | to flush the cache. Here, the data written by movcal.l is never
|
507 | 852d481f | edgar_igl | written to memory, and the data written is just bogus.
|
508 | 852d481f | edgar_igl | |
509 | 852d481f | edgar_igl | To simulate this, we simulate movcal.l, we store the value to memory,
|
510 | 852d481f | edgar_igl | but we also remember the previous content. If we see ocbi, we check
|
511 | 852d481f | edgar_igl | if movcal.l for that address was done previously. If so, the write should
|
512 | 852d481f | edgar_igl | not have hit the memory, so we restore the previous content.
|
513 | 852d481f | edgar_igl | When we see an instruction that is neither movca.l
|
514 | 852d481f | edgar_igl | nor ocbi, the previous content is discarded.
|
515 | 852d481f | edgar_igl | |
516 | 852d481f | edgar_igl | To optimize, we only try to flush stores when we're at the start of
|
517 | 852d481f | edgar_igl | TB, or if we already saw movca.l in this TB and did not flush stores
|
518 | 852d481f | edgar_igl | yet. */
|
519 | 852d481f | edgar_igl | if (ctx->has_movcal)
|
520 | 852d481f | edgar_igl | { |
521 | 852d481f | edgar_igl | int opcode = ctx->opcode & 0xf0ff; |
522 | 852d481f | edgar_igl | if (opcode != 0x0093 /* ocbi */ |
523 | 852d481f | edgar_igl | && opcode != 0x00c3 /* movca.l */) |
524 | 852d481f | edgar_igl | { |
525 | 852d481f | edgar_igl | gen_helper_discard_movcal_backup (); |
526 | 852d481f | edgar_igl | ctx->has_movcal = 0;
|
527 | 852d481f | edgar_igl | } |
528 | 852d481f | edgar_igl | } |
529 | 852d481f | edgar_igl | |
530 | fdf9b3e8 | bellard | #if 0
|
531 | fdf9b3e8 | bellard | fprintf(stderr, "Translating opcode 0x%04x\n", ctx->opcode);
|
532 | fdf9b3e8 | bellard | #endif
|
533 | f6198371 | aurel32 | |
534 | fdf9b3e8 | bellard | switch (ctx->opcode) {
|
535 | fdf9b3e8 | bellard | case 0x0019: /* div0u */ |
536 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T)); |
537 | fdf9b3e8 | bellard | return;
|
538 | fdf9b3e8 | bellard | case 0x000b: /* rts */ |
539 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
540 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_pr); |
541 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
542 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
543 | fdf9b3e8 | bellard | return;
|
544 | fdf9b3e8 | bellard | case 0x0028: /* clrmac */ |
545 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_mach, 0);
|
546 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_macl, 0);
|
547 | fdf9b3e8 | bellard | return;
|
548 | fdf9b3e8 | bellard | case 0x0048: /* clrs */ |
549 | 3a8a44c4 | aurel32 | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S); |
550 | fdf9b3e8 | bellard | return;
|
551 | fdf9b3e8 | bellard | case 0x0008: /* clrt */ |
552 | a4625612 | aurel32 | gen_clr_t(); |
553 | fdf9b3e8 | bellard | return;
|
554 | fdf9b3e8 | bellard | case 0x0038: /* ldtlb */ |
555 | fe25591e | aurel32 | CHECK_PRIVILEGED |
556 | a7812ae4 | pbrook | gen_helper_ldtlb(); |
557 | fdf9b3e8 | bellard | return;
|
558 | c5e814b2 | ths | case 0x002b: /* rte */ |
559 | fe25591e | aurel32 | CHECK_PRIVILEGED |
560 | 1000822b | aurel32 | CHECK_NOT_DELAY_SLOT |
561 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_sr, cpu_ssr); |
562 | 1000822b | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc); |
563 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
564 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
565 | fdf9b3e8 | bellard | return;
|
566 | fdf9b3e8 | bellard | case 0x0058: /* sets */ |
567 | 3a8a44c4 | aurel32 | tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S); |
568 | fdf9b3e8 | bellard | return;
|
569 | fdf9b3e8 | bellard | case 0x0018: /* sett */ |
570 | a4625612 | aurel32 | gen_set_t(); |
571 | fdf9b3e8 | bellard | return;
|
572 | 24988dc2 | aurel32 | case 0xfbfd: /* frchg */ |
573 | 6f06939b | aurel32 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR); |
574 | 823029f9 | ths | ctx->bstate = BS_STOP; |
575 | fdf9b3e8 | bellard | return;
|
576 | 24988dc2 | aurel32 | case 0xf3fd: /* fschg */ |
577 | 6f06939b | aurel32 | tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_SZ); |
578 | 823029f9 | ths | ctx->bstate = BS_STOP; |
579 | fdf9b3e8 | bellard | return;
|
580 | fdf9b3e8 | bellard | case 0x0009: /* nop */ |
581 | fdf9b3e8 | bellard | return;
|
582 | fdf9b3e8 | bellard | case 0x001b: /* sleep */ |
583 | fe25591e | aurel32 | CHECK_PRIVILEGED |
584 | a7812ae4 | pbrook | gen_helper_sleep(tcg_const_i32(ctx->pc + 2));
|
585 | fdf9b3e8 | bellard | return;
|
586 | fdf9b3e8 | bellard | } |
587 | fdf9b3e8 | bellard | |
588 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf000) { |
589 | fdf9b3e8 | bellard | case 0x1000: /* mov.l Rm,@(disp,Rn) */ |
590 | c55497ec | aurel32 | { |
591 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
592 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4);
|
593 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
594 | c55497ec | aurel32 | tcg_temp_free(addr); |
595 | c55497ec | aurel32 | } |
596 | fdf9b3e8 | bellard | return;
|
597 | fdf9b3e8 | bellard | case 0x5000: /* mov.l @(disp,Rm),Rn */ |
598 | c55497ec | aurel32 | { |
599 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
600 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4);
|
601 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
602 | c55497ec | aurel32 | tcg_temp_free(addr); |
603 | c55497ec | aurel32 | } |
604 | fdf9b3e8 | bellard | return;
|
605 | 24988dc2 | aurel32 | case 0xe000: /* mov #imm,Rn */ |
606 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), B7_0s); |
607 | fdf9b3e8 | bellard | return;
|
608 | fdf9b3e8 | bellard | case 0x9000: /* mov.w @(disp,PC),Rn */ |
609 | c55497ec | aurel32 | { |
610 | c55497ec | aurel32 | TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); |
611 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); |
612 | c55497ec | aurel32 | tcg_temp_free(addr); |
613 | c55497ec | aurel32 | } |
614 | fdf9b3e8 | bellard | return;
|
615 | fdf9b3e8 | bellard | case 0xd000: /* mov.l @(disp,PC),Rn */ |
616 | c55497ec | aurel32 | { |
617 | c55497ec | aurel32 | TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); |
618 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
619 | c55497ec | aurel32 | tcg_temp_free(addr); |
620 | c55497ec | aurel32 | } |
621 | fdf9b3e8 | bellard | return;
|
622 | 24988dc2 | aurel32 | case 0x7000: /* add #imm,Rn */ |
623 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); |
624 | fdf9b3e8 | bellard | return;
|
625 | fdf9b3e8 | bellard | case 0xa000: /* bra disp */ |
626 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
627 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
628 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
629 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
630 | fdf9b3e8 | bellard | return;
|
631 | fdf9b3e8 | bellard | case 0xb000: /* bsr disp */ |
632 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
633 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
634 | 1000822b | aurel32 | ctx->delayed_pc = ctx->pc + 4 + B11_0s * 2; |
635 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_delayed_pc, ctx->delayed_pc); |
636 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
637 | fdf9b3e8 | bellard | return;
|
638 | fdf9b3e8 | bellard | } |
639 | fdf9b3e8 | bellard | |
640 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf00f) { |
641 | fdf9b3e8 | bellard | case 0x6003: /* mov Rm,Rn */ |
642 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
643 | fdf9b3e8 | bellard | return;
|
644 | fdf9b3e8 | bellard | case 0x2000: /* mov.b Rm,@Rn */ |
645 | 7efbe241 | aurel32 | tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx); |
646 | fdf9b3e8 | bellard | return;
|
647 | fdf9b3e8 | bellard | case 0x2001: /* mov.w Rm,@Rn */ |
648 | 7efbe241 | aurel32 | tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx); |
649 | fdf9b3e8 | bellard | return;
|
650 | fdf9b3e8 | bellard | case 0x2002: /* mov.l Rm,@Rn */ |
651 | 7efbe241 | aurel32 | tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx); |
652 | fdf9b3e8 | bellard | return;
|
653 | fdf9b3e8 | bellard | case 0x6000: /* mov.b @Rm,Rn */ |
654 | 7efbe241 | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
655 | fdf9b3e8 | bellard | return;
|
656 | fdf9b3e8 | bellard | case 0x6001: /* mov.w @Rm,Rn */ |
657 | 7efbe241 | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
658 | fdf9b3e8 | bellard | return;
|
659 | fdf9b3e8 | bellard | case 0x6002: /* mov.l @Rm,Rn */ |
660 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
661 | fdf9b3e8 | bellard | return;
|
662 | fdf9b3e8 | bellard | case 0x2004: /* mov.b Rm,@-Rn */ |
663 | c55497ec | aurel32 | { |
664 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
665 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 1);
|
666 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */
|
667 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */
|
668 | c55497ec | aurel32 | tcg_temp_free(addr); |
669 | c55497ec | aurel32 | } |
670 | fdf9b3e8 | bellard | return;
|
671 | fdf9b3e8 | bellard | case 0x2005: /* mov.w Rm,@-Rn */ |
672 | c55497ec | aurel32 | { |
673 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
674 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 2);
|
675 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
676 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); |
677 | c55497ec | aurel32 | tcg_temp_free(addr); |
678 | c55497ec | aurel32 | } |
679 | fdf9b3e8 | bellard | return;
|
680 | fdf9b3e8 | bellard | case 0x2006: /* mov.l Rm,@-Rn */ |
681 | c55497ec | aurel32 | { |
682 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
683 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
684 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
685 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); |
686 | c55497ec | aurel32 | } |
687 | fdf9b3e8 | bellard | return;
|
688 | eda9b09b | bellard | case 0x6004: /* mov.b @Rm+,Rn */ |
689 | 7efbe241 | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx); |
690 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
691 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1);
|
692 | fdf9b3e8 | bellard | return;
|
693 | fdf9b3e8 | bellard | case 0x6005: /* mov.w @Rm+,Rn */ |
694 | 7efbe241 | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx); |
695 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
696 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
|
697 | fdf9b3e8 | bellard | return;
|
698 | fdf9b3e8 | bellard | case 0x6006: /* mov.l @Rm+,Rn */ |
699 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx); |
700 | 24988dc2 | aurel32 | if ( B11_8 != B7_4 )
|
701 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
702 | fdf9b3e8 | bellard | return;
|
703 | fdf9b3e8 | bellard | case 0x0004: /* mov.b Rm,@(R0,Rn) */ |
704 | c55497ec | aurel32 | { |
705 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
706 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
707 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); |
708 | c55497ec | aurel32 | tcg_temp_free(addr); |
709 | c55497ec | aurel32 | } |
710 | fdf9b3e8 | bellard | return;
|
711 | fdf9b3e8 | bellard | case 0x0005: /* mov.w Rm,@(R0,Rn) */ |
712 | c55497ec | aurel32 | { |
713 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
714 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
715 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx); |
716 | c55497ec | aurel32 | tcg_temp_free(addr); |
717 | c55497ec | aurel32 | } |
718 | fdf9b3e8 | bellard | return;
|
719 | fdf9b3e8 | bellard | case 0x0006: /* mov.l Rm,@(R0,Rn) */ |
720 | c55497ec | aurel32 | { |
721 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
722 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
723 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx); |
724 | c55497ec | aurel32 | tcg_temp_free(addr); |
725 | c55497ec | aurel32 | } |
726 | fdf9b3e8 | bellard | return;
|
727 | fdf9b3e8 | bellard | case 0x000c: /* mov.b @(R0,Rm),Rn */ |
728 | c55497ec | aurel32 | { |
729 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
730 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
731 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx); |
732 | c55497ec | aurel32 | tcg_temp_free(addr); |
733 | c55497ec | aurel32 | } |
734 | fdf9b3e8 | bellard | return;
|
735 | fdf9b3e8 | bellard | case 0x000d: /* mov.w @(R0,Rm),Rn */ |
736 | c55497ec | aurel32 | { |
737 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
738 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
739 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx); |
740 | c55497ec | aurel32 | tcg_temp_free(addr); |
741 | c55497ec | aurel32 | } |
742 | fdf9b3e8 | bellard | return;
|
743 | fdf9b3e8 | bellard | case 0x000e: /* mov.l @(R0,Rm),Rn */ |
744 | c55497ec | aurel32 | { |
745 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
746 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
747 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx); |
748 | c55497ec | aurel32 | tcg_temp_free(addr); |
749 | c55497ec | aurel32 | } |
750 | fdf9b3e8 | bellard | return;
|
751 | fdf9b3e8 | bellard | case 0x6008: /* swap.b Rm,Rn */ |
752 | c55497ec | aurel32 | { |
753 | 3101e99c | Aurelien Jarno | TCGv high, low; |
754 | a7812ae4 | pbrook | high = tcg_temp_new(); |
755 | 3101e99c | Aurelien Jarno | tcg_gen_andi_i32(high, REG(B7_4), 0xffff0000);
|
756 | a7812ae4 | pbrook | low = tcg_temp_new(); |
757 | 3101e99c | Aurelien Jarno | tcg_gen_ext16u_i32(low, REG(B7_4)); |
758 | 3101e99c | Aurelien Jarno | tcg_gen_bswap16_i32(low, low); |
759 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
760 | c55497ec | aurel32 | tcg_temp_free(low); |
761 | c55497ec | aurel32 | tcg_temp_free(high); |
762 | c55497ec | aurel32 | } |
763 | fdf9b3e8 | bellard | return;
|
764 | fdf9b3e8 | bellard | case 0x6009: /* swap.w Rm,Rn */ |
765 | c55497ec | aurel32 | { |
766 | c55497ec | aurel32 | TCGv high, low; |
767 | a7812ae4 | pbrook | high = tcg_temp_new(); |
768 | 3101e99c | Aurelien Jarno | tcg_gen_shli_i32(high, REG(B7_4), 16);
|
769 | a7812ae4 | pbrook | low = tcg_temp_new(); |
770 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B7_4), 16);
|
771 | c55497ec | aurel32 | tcg_gen_ext16u_i32(low, low); |
772 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
773 | c55497ec | aurel32 | tcg_temp_free(low); |
774 | c55497ec | aurel32 | tcg_temp_free(high); |
775 | c55497ec | aurel32 | } |
776 | fdf9b3e8 | bellard | return;
|
777 | fdf9b3e8 | bellard | case 0x200d: /* xtrct Rm,Rn */ |
778 | c55497ec | aurel32 | { |
779 | c55497ec | aurel32 | TCGv high, low; |
780 | a7812ae4 | pbrook | high = tcg_temp_new(); |
781 | 3101e99c | Aurelien Jarno | tcg_gen_shli_i32(high, REG(B7_4), 16);
|
782 | a7812ae4 | pbrook | low = tcg_temp_new(); |
783 | c55497ec | aurel32 | tcg_gen_shri_i32(low, REG(B11_8), 16);
|
784 | c55497ec | aurel32 | tcg_gen_ext16u_i32(low, low); |
785 | c55497ec | aurel32 | tcg_gen_or_i32(REG(B11_8), high, low); |
786 | c55497ec | aurel32 | tcg_temp_free(low); |
787 | c55497ec | aurel32 | tcg_temp_free(high); |
788 | c55497ec | aurel32 | } |
789 | fdf9b3e8 | bellard | return;
|
790 | fdf9b3e8 | bellard | case 0x300c: /* add Rm,Rn */ |
791 | 7efbe241 | aurel32 | tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
792 | fdf9b3e8 | bellard | return;
|
793 | fdf9b3e8 | bellard | case 0x300e: /* addc Rm,Rn */ |
794 | a7812ae4 | pbrook | gen_helper_addc(REG(B11_8), REG(B7_4), REG(B11_8)); |
795 | fdf9b3e8 | bellard | return;
|
796 | fdf9b3e8 | bellard | case 0x300f: /* addv Rm,Rn */ |
797 | a7812ae4 | pbrook | gen_helper_addv(REG(B11_8), REG(B7_4), REG(B11_8)); |
798 | fdf9b3e8 | bellard | return;
|
799 | fdf9b3e8 | bellard | case 0x2009: /* and Rm,Rn */ |
800 | 7efbe241 | aurel32 | tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
801 | fdf9b3e8 | bellard | return;
|
802 | fdf9b3e8 | bellard | case 0x3000: /* cmp/eq Rm,Rn */ |
803 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8)); |
804 | fdf9b3e8 | bellard | return;
|
805 | fdf9b3e8 | bellard | case 0x3003: /* cmp/ge Rm,Rn */ |
806 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8)); |
807 | fdf9b3e8 | bellard | return;
|
808 | fdf9b3e8 | bellard | case 0x3007: /* cmp/gt Rm,Rn */ |
809 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8)); |
810 | fdf9b3e8 | bellard | return;
|
811 | fdf9b3e8 | bellard | case 0x3006: /* cmp/hi Rm,Rn */ |
812 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8)); |
813 | fdf9b3e8 | bellard | return;
|
814 | fdf9b3e8 | bellard | case 0x3002: /* cmp/hs Rm,Rn */ |
815 | 7efbe241 | aurel32 | gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8)); |
816 | fdf9b3e8 | bellard | return;
|
817 | fdf9b3e8 | bellard | case 0x200c: /* cmp/str Rm,Rn */ |
818 | 69d6275b | aurel32 | { |
819 | c5c19137 | Aurelien Jarno | TCGv cmp1 = tcg_temp_new(); |
820 | c5c19137 | Aurelien Jarno | TCGv cmp2 = tcg_temp_new(); |
821 | c5c19137 | Aurelien Jarno | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
822 | c55497ec | aurel32 | tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8)); |
823 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
|
824 | c5c19137 | Aurelien Jarno | tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
825 | c5c19137 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); |
826 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
|
827 | c5c19137 | Aurelien Jarno | tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
828 | c5c19137 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); |
829 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
|
830 | c5c19137 | Aurelien Jarno | tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
831 | c5c19137 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); |
832 | c55497ec | aurel32 | tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
|
833 | c5c19137 | Aurelien Jarno | tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
834 | c5c19137 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2); |
835 | c55497ec | aurel32 | tcg_temp_free(cmp2); |
836 | c55497ec | aurel32 | tcg_temp_free(cmp1); |
837 | 69d6275b | aurel32 | } |
838 | fdf9b3e8 | bellard | return;
|
839 | fdf9b3e8 | bellard | case 0x2007: /* div0s Rm,Rn */ |
840 | c55497ec | aurel32 | { |
841 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */ |
842 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */ |
843 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
844 | c55497ec | aurel32 | tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8)); |
845 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */ |
846 | c55497ec | aurel32 | tcg_temp_free(val); |
847 | c55497ec | aurel32 | } |
848 | fdf9b3e8 | bellard | return;
|
849 | fdf9b3e8 | bellard | case 0x3004: /* div1 Rm,Rn */ |
850 | a7812ae4 | pbrook | gen_helper_div1(REG(B11_8), REG(B7_4), REG(B11_8)); |
851 | fdf9b3e8 | bellard | return;
|
852 | fdf9b3e8 | bellard | case 0x300d: /* dmuls.l Rm,Rn */ |
853 | 6f06939b | aurel32 | { |
854 | a7812ae4 | pbrook | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
855 | a7812ae4 | pbrook | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
856 | 6f06939b | aurel32 | |
857 | 7efbe241 | aurel32 | tcg_gen_ext_i32_i64(tmp1, REG(B7_4)); |
858 | 7efbe241 | aurel32 | tcg_gen_ext_i32_i64(tmp2, REG(B11_8)); |
859 | 6f06939b | aurel32 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
860 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
861 | 6f06939b | aurel32 | tcg_gen_shri_i64(tmp1, tmp1, 32);
|
862 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
863 | 6f06939b | aurel32 | |
864 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp2); |
865 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp1); |
866 | 6f06939b | aurel32 | } |
867 | fdf9b3e8 | bellard | return;
|
868 | fdf9b3e8 | bellard | case 0x3005: /* dmulu.l Rm,Rn */ |
869 | 6f06939b | aurel32 | { |
870 | a7812ae4 | pbrook | TCGv_i64 tmp1 = tcg_temp_new_i64(); |
871 | a7812ae4 | pbrook | TCGv_i64 tmp2 = tcg_temp_new_i64(); |
872 | 6f06939b | aurel32 | |
873 | 7efbe241 | aurel32 | tcg_gen_extu_i32_i64(tmp1, REG(B7_4)); |
874 | 7efbe241 | aurel32 | tcg_gen_extu_i32_i64(tmp2, REG(B11_8)); |
875 | 6f06939b | aurel32 | tcg_gen_mul_i64(tmp1, tmp1, tmp2); |
876 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_macl, tmp1); |
877 | 6f06939b | aurel32 | tcg_gen_shri_i64(tmp1, tmp1, 32);
|
878 | 6f06939b | aurel32 | tcg_gen_trunc_i64_i32(cpu_mach, tmp1); |
879 | 6f06939b | aurel32 | |
880 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp2); |
881 | a7812ae4 | pbrook | tcg_temp_free_i64(tmp1); |
882 | 6f06939b | aurel32 | } |
883 | fdf9b3e8 | bellard | return;
|
884 | fdf9b3e8 | bellard | case 0x600e: /* exts.b Rm,Rn */ |
885 | 7efbe241 | aurel32 | tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); |
886 | fdf9b3e8 | bellard | return;
|
887 | fdf9b3e8 | bellard | case 0x600f: /* exts.w Rm,Rn */ |
888 | 7efbe241 | aurel32 | tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); |
889 | fdf9b3e8 | bellard | return;
|
890 | fdf9b3e8 | bellard | case 0x600c: /* extu.b Rm,Rn */ |
891 | 7efbe241 | aurel32 | tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); |
892 | fdf9b3e8 | bellard | return;
|
893 | fdf9b3e8 | bellard | case 0x600d: /* extu.w Rm,Rn */ |
894 | 7efbe241 | aurel32 | tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); |
895 | fdf9b3e8 | bellard | return;
|
896 | 24988dc2 | aurel32 | case 0x000f: /* mac.l @Rm+,@Rn+ */ |
897 | c55497ec | aurel32 | { |
898 | c55497ec | aurel32 | TCGv arg0, arg1; |
899 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
900 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
901 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
902 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
903 | a7812ae4 | pbrook | gen_helper_macl(arg0, arg1); |
904 | c55497ec | aurel32 | tcg_temp_free(arg1); |
905 | c55497ec | aurel32 | tcg_temp_free(arg0); |
906 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
907 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
908 | c55497ec | aurel32 | } |
909 | fdf9b3e8 | bellard | return;
|
910 | fdf9b3e8 | bellard | case 0x400f: /* mac.w @Rm+,@Rn+ */ |
911 | c55497ec | aurel32 | { |
912 | c55497ec | aurel32 | TCGv arg0, arg1; |
913 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
914 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx); |
915 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
916 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx); |
917 | a7812ae4 | pbrook | gen_helper_macw(arg0, arg1); |
918 | c55497ec | aurel32 | tcg_temp_free(arg1); |
919 | c55497ec | aurel32 | tcg_temp_free(arg0); |
920 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2);
|
921 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2);
|
922 | c55497ec | aurel32 | } |
923 | fdf9b3e8 | bellard | return;
|
924 | fdf9b3e8 | bellard | case 0x0007: /* mul.l Rm,Rn */ |
925 | 7efbe241 | aurel32 | tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); |
926 | fdf9b3e8 | bellard | return;
|
927 | fdf9b3e8 | bellard | case 0x200f: /* muls.w Rm,Rn */ |
928 | c55497ec | aurel32 | { |
929 | c55497ec | aurel32 | TCGv arg0, arg1; |
930 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
931 | c55497ec | aurel32 | tcg_gen_ext16s_i32(arg0, REG(B7_4)); |
932 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
933 | c55497ec | aurel32 | tcg_gen_ext16s_i32(arg1, REG(B11_8)); |
934 | c55497ec | aurel32 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
935 | c55497ec | aurel32 | tcg_temp_free(arg1); |
936 | c55497ec | aurel32 | tcg_temp_free(arg0); |
937 | c55497ec | aurel32 | } |
938 | fdf9b3e8 | bellard | return;
|
939 | fdf9b3e8 | bellard | case 0x200e: /* mulu.w Rm,Rn */ |
940 | c55497ec | aurel32 | { |
941 | c55497ec | aurel32 | TCGv arg0, arg1; |
942 | a7812ae4 | pbrook | arg0 = tcg_temp_new(); |
943 | c55497ec | aurel32 | tcg_gen_ext16u_i32(arg0, REG(B7_4)); |
944 | a7812ae4 | pbrook | arg1 = tcg_temp_new(); |
945 | c55497ec | aurel32 | tcg_gen_ext16u_i32(arg1, REG(B11_8)); |
946 | c55497ec | aurel32 | tcg_gen_mul_i32(cpu_macl, arg0, arg1); |
947 | c55497ec | aurel32 | tcg_temp_free(arg1); |
948 | c55497ec | aurel32 | tcg_temp_free(arg0); |
949 | c55497ec | aurel32 | } |
950 | fdf9b3e8 | bellard | return;
|
951 | fdf9b3e8 | bellard | case 0x600b: /* neg Rm,Rn */ |
952 | 7efbe241 | aurel32 | tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); |
953 | fdf9b3e8 | bellard | return;
|
954 | fdf9b3e8 | bellard | case 0x600a: /* negc Rm,Rn */ |
955 | b2d9eda5 | Aurelien Jarno | { |
956 | b2d9eda5 | Aurelien Jarno | TCGv t0, t1; |
957 | b2d9eda5 | Aurelien Jarno | t0 = tcg_temp_new(); |
958 | b2d9eda5 | Aurelien Jarno | tcg_gen_neg_i32(t0, REG(B7_4)); |
959 | b2d9eda5 | Aurelien Jarno | t1 = tcg_temp_new(); |
960 | b2d9eda5 | Aurelien Jarno | tcg_gen_andi_i32(t1, cpu_sr, SR_T); |
961 | b2d9eda5 | Aurelien Jarno | tcg_gen_sub_i32(REG(B11_8), t0, t1); |
962 | b2d9eda5 | Aurelien Jarno | tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
963 | 7026259f | Aurelien Jarno | tcg_gen_setcondi_i32(TCG_COND_GTU, t1, t0, 0);
|
964 | b2d9eda5 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, t1); |
965 | 7026259f | Aurelien Jarno | tcg_gen_setcond_i32(TCG_COND_GTU, t1, REG(B11_8), t0); |
966 | b2d9eda5 | Aurelien Jarno | tcg_gen_or_i32(cpu_sr, cpu_sr, t1); |
967 | b2d9eda5 | Aurelien Jarno | tcg_temp_free(t0); |
968 | b2d9eda5 | Aurelien Jarno | tcg_temp_free(t1); |
969 | b2d9eda5 | Aurelien Jarno | } |
970 | fdf9b3e8 | bellard | return;
|
971 | fdf9b3e8 | bellard | case 0x6007: /* not Rm,Rn */ |
972 | 7efbe241 | aurel32 | tcg_gen_not_i32(REG(B11_8), REG(B7_4)); |
973 | fdf9b3e8 | bellard | return;
|
974 | fdf9b3e8 | bellard | case 0x200b: /* or Rm,Rn */ |
975 | 7efbe241 | aurel32 | tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
976 | fdf9b3e8 | bellard | return;
|
977 | fdf9b3e8 | bellard | case 0x400c: /* shad Rm,Rn */ |
978 | 69d6275b | aurel32 | { |
979 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
980 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
981 | 69d6275b | aurel32 | int label3 = gen_new_label();
|
982 | 69d6275b | aurel32 | int label4 = gen_new_label();
|
983 | 3101e99c | Aurelien Jarno | TCGv shift; |
984 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
985 | 69d6275b | aurel32 | /* Rm positive, shift to the left */
|
986 | 3101e99c | Aurelien Jarno | shift = tcg_temp_new(); |
987 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
988 | c55497ec | aurel32 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
989 | 3101e99c | Aurelien Jarno | tcg_temp_free(shift); |
990 | 69d6275b | aurel32 | tcg_gen_br(label4); |
991 | 69d6275b | aurel32 | /* Rm negative, shift to the right */
|
992 | 69d6275b | aurel32 | gen_set_label(label1); |
993 | 3101e99c | Aurelien Jarno | shift = tcg_temp_new(); |
994 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
995 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
|
996 | c55497ec | aurel32 | tcg_gen_not_i32(shift, REG(B7_4)); |
997 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, shift, 0x1f);
|
998 | c55497ec | aurel32 | tcg_gen_addi_i32(shift, shift, 1);
|
999 | c55497ec | aurel32 | tcg_gen_sar_i32(REG(B11_8), REG(B11_8), shift); |
1000 | 3101e99c | Aurelien Jarno | tcg_temp_free(shift); |
1001 | 69d6275b | aurel32 | tcg_gen_br(label4); |
1002 | 69d6275b | aurel32 | /* Rm = -32 */
|
1003 | 69d6275b | aurel32 | gen_set_label(label2); |
1004 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B11_8), 0, label3);
|
1005 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0);
|
1006 | 69d6275b | aurel32 | tcg_gen_br(label4); |
1007 | 69d6275b | aurel32 | gen_set_label(label3); |
1008 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0xffffffff);
|
1009 | 69d6275b | aurel32 | gen_set_label(label4); |
1010 | 69d6275b | aurel32 | } |
1011 | fdf9b3e8 | bellard | return;
|
1012 | fdf9b3e8 | bellard | case 0x400d: /* shld Rm,Rn */ |
1013 | 69d6275b | aurel32 | { |
1014 | 69d6275b | aurel32 | int label1 = gen_new_label();
|
1015 | 69d6275b | aurel32 | int label2 = gen_new_label();
|
1016 | 69d6275b | aurel32 | int label3 = gen_new_label();
|
1017 | 3101e99c | Aurelien Jarno | TCGv shift; |
1018 | 7efbe241 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_LT, REG(B7_4), 0, label1);
|
1019 | 69d6275b | aurel32 | /* Rm positive, shift to the left */
|
1020 | 3101e99c | Aurelien Jarno | shift = tcg_temp_new(); |
1021 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
1022 | c55497ec | aurel32 | tcg_gen_shl_i32(REG(B11_8), REG(B11_8), shift); |
1023 | 3101e99c | Aurelien Jarno | tcg_temp_free(shift); |
1024 | 69d6275b | aurel32 | tcg_gen_br(label3); |
1025 | 69d6275b | aurel32 | /* Rm negative, shift to the right */
|
1026 | 69d6275b | aurel32 | gen_set_label(label1); |
1027 | 3101e99c | Aurelien Jarno | shift = tcg_temp_new(); |
1028 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, REG(B7_4), 0x1f);
|
1029 | c55497ec | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, shift, 0, label2);
|
1030 | c55497ec | aurel32 | tcg_gen_not_i32(shift, REG(B7_4)); |
1031 | c55497ec | aurel32 | tcg_gen_andi_i32(shift, shift, 0x1f);
|
1032 | c55497ec | aurel32 | tcg_gen_addi_i32(shift, shift, 1);
|
1033 | c55497ec | aurel32 | tcg_gen_shr_i32(REG(B11_8), REG(B11_8), shift); |
1034 | 3101e99c | Aurelien Jarno | tcg_temp_free(shift); |
1035 | 69d6275b | aurel32 | tcg_gen_br(label3); |
1036 | 69d6275b | aurel32 | /* Rm = -32 */
|
1037 | 69d6275b | aurel32 | gen_set_label(label2); |
1038 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(B11_8), 0);
|
1039 | 69d6275b | aurel32 | gen_set_label(label3); |
1040 | 69d6275b | aurel32 | } |
1041 | fdf9b3e8 | bellard | return;
|
1042 | fdf9b3e8 | bellard | case 0x3008: /* sub Rm,Rn */ |
1043 | 7efbe241 | aurel32 | tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
1044 | fdf9b3e8 | bellard | return;
|
1045 | fdf9b3e8 | bellard | case 0x300a: /* subc Rm,Rn */ |
1046 | a7812ae4 | pbrook | gen_helper_subc(REG(B11_8), REG(B7_4), REG(B11_8)); |
1047 | fdf9b3e8 | bellard | return;
|
1048 | fdf9b3e8 | bellard | case 0x300b: /* subv Rm,Rn */ |
1049 | a7812ae4 | pbrook | gen_helper_subv(REG(B11_8), REG(B7_4), REG(B11_8)); |
1050 | fdf9b3e8 | bellard | return;
|
1051 | fdf9b3e8 | bellard | case 0x2008: /* tst Rm,Rn */ |
1052 | c55497ec | aurel32 | { |
1053 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1054 | c55497ec | aurel32 | tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); |
1055 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1056 | c55497ec | aurel32 | tcg_temp_free(val); |
1057 | c55497ec | aurel32 | } |
1058 | fdf9b3e8 | bellard | return;
|
1059 | fdf9b3e8 | bellard | case 0x200a: /* xor Rm,Rn */ |
1060 | 7efbe241 | aurel32 | tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); |
1061 | fdf9b3e8 | bellard | return;
|
1062 | e67888a7 | ths | case 0xf00c: /* fmov {F,D,X}Rm,{F,D,X}Rn - FPSCR: Nothing */ |
1063 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1064 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1065 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1066 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, XREG(B7_4)); |
1067 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, XREG(B11_8)); |
1068 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1069 | eda9b09b | bellard | } else {
|
1070 | 66ba317c | aurel32 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1071 | eda9b09b | bellard | } |
1072 | eda9b09b | bellard | return;
|
1073 | e67888a7 | ths | case 0xf00a: /* fmov {F,D,X}Rm,@Rn - FPSCR: Nothing */ |
1074 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1075 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1076 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1077 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1078 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B11_8), 4);
|
1079 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); |
1080 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1081 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1082 | eda9b09b | bellard | } else {
|
1083 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); |
1084 | eda9b09b | bellard | } |
1085 | eda9b09b | bellard | return;
|
1086 | e67888a7 | ths | case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */ |
1087 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1088 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1089 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1090 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1091 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
|
1092 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); |
1093 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1094 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1095 | eda9b09b | bellard | } else {
|
1096 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
1097 | eda9b09b | bellard | } |
1098 | eda9b09b | bellard | return;
|
1099 | e67888a7 | ths | case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */ |
1100 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1101 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1102 | 11bb09f1 | aurel32 | TCGv addr_hi = tcg_temp_new(); |
1103 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1104 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr_hi, REG(B7_4), 4);
|
1105 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx); |
1106 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
1107 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8);
|
1108 | 11bb09f1 | aurel32 | tcg_temp_free(addr_hi); |
1109 | eda9b09b | bellard | } else {
|
1110 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
1111 | cc4ba6a9 | aurel32 | tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4);
|
1112 | eda9b09b | bellard | } |
1113 | eda9b09b | bellard | return;
|
1114 | e67888a7 | ths | case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */ |
1115 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1116 | 022a22c7 | ths | if (ctx->fpscr & FPSCR_SZ) {
|
1117 | 11bb09f1 | aurel32 | TCGv addr = tcg_temp_new_i32(); |
1118 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1119 | 11bb09f1 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1120 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
|
1121 | 3101e99c | Aurelien Jarno | tcg_gen_subi_i32(addr, addr, 4);
|
1122 | 11bb09f1 | aurel32 | tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx); |
1123 | 11bb09f1 | aurel32 | tcg_gen_mov_i32(REG(B11_8), addr); |
1124 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1125 | eda9b09b | bellard | } else {
|
1126 | a7812ae4 | pbrook | TCGv addr; |
1127 | a7812ae4 | pbrook | addr = tcg_temp_new_i32(); |
1128 | cc4ba6a9 | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1129 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
1130 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); |
1131 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1132 | eda9b09b | bellard | } |
1133 | eda9b09b | bellard | return;
|
1134 | e67888a7 | ths | case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */ |
1135 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1136 | cc4ba6a9 | aurel32 | { |
1137 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new_i32(); |
1138 | cc4ba6a9 | aurel32 | tcg_gen_add_i32(addr, REG(B7_4), REG(0));
|
1139 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_SZ) {
|
1140 | 11bb09f1 | aurel32 | int fr = XREG(B11_8);
|
1141 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
1142 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr, addr, 4);
|
1143 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
|
1144 | cc4ba6a9 | aurel32 | } else {
|
1145 | 66ba317c | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); |
1146 | cc4ba6a9 | aurel32 | } |
1147 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1148 | eda9b09b | bellard | } |
1149 | eda9b09b | bellard | return;
|
1150 | e67888a7 | ths | case 0xf007: /* fmov {F,D,X}Rn,@(R0,Rn) - FPSCR: Nothing */ |
1151 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1152 | cc4ba6a9 | aurel32 | { |
1153 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1154 | cc4ba6a9 | aurel32 | tcg_gen_add_i32(addr, REG(B11_8), REG(0));
|
1155 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_SZ) {
|
1156 | 11bb09f1 | aurel32 | int fr = XREG(B7_4);
|
1157 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
1158 | 11bb09f1 | aurel32 | tcg_gen_addi_i32(addr, addr, 4);
|
1159 | 11bb09f1 | aurel32 | tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx);
|
1160 | cc4ba6a9 | aurel32 | } else {
|
1161 | 66ba317c | aurel32 | tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
1162 | cc4ba6a9 | aurel32 | } |
1163 | cc4ba6a9 | aurel32 | tcg_temp_free(addr); |
1164 | eda9b09b | bellard | } |
1165 | eda9b09b | bellard | return;
|
1166 | e67888a7 | ths | case 0xf000: /* fadd Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1167 | e67888a7 | ths | case 0xf001: /* fsub Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1168 | e67888a7 | ths | case 0xf002: /* fmul Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1169 | e67888a7 | ths | case 0xf003: /* fdiv Rm,Rn - FPSCR: R[PR,Enable.O/U/I]/W[Cause,Flag] */ |
1170 | e67888a7 | ths | case 0xf004: /* fcmp/eq Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1171 | e67888a7 | ths | case 0xf005: /* fcmp/gt Rm,Rn - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1172 | cc4ba6a9 | aurel32 | { |
1173 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1174 | cc4ba6a9 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1175 | a7812ae4 | pbrook | TCGv_i64 fp0, fp1; |
1176 | a7812ae4 | pbrook | |
1177 | cc4ba6a9 | aurel32 | if (ctx->opcode & 0x0110) |
1178 | cc4ba6a9 | aurel32 | break; /* illegal instruction */ |
1179 | a7812ae4 | pbrook | fp0 = tcg_temp_new_i64(); |
1180 | a7812ae4 | pbrook | fp1 = tcg_temp_new_i64(); |
1181 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp0, DREG(B11_8)); |
1182 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp1, DREG(B7_4)); |
1183 | a7812ae4 | pbrook | switch (ctx->opcode & 0xf00f) { |
1184 | a7812ae4 | pbrook | case 0xf000: /* fadd Rm,Rn */ |
1185 | a7812ae4 | pbrook | gen_helper_fadd_DT(fp0, fp0, fp1); |
1186 | a7812ae4 | pbrook | break;
|
1187 | a7812ae4 | pbrook | case 0xf001: /* fsub Rm,Rn */ |
1188 | a7812ae4 | pbrook | gen_helper_fsub_DT(fp0, fp0, fp1); |
1189 | a7812ae4 | pbrook | break;
|
1190 | a7812ae4 | pbrook | case 0xf002: /* fmul Rm,Rn */ |
1191 | a7812ae4 | pbrook | gen_helper_fmul_DT(fp0, fp0, fp1); |
1192 | a7812ae4 | pbrook | break;
|
1193 | a7812ae4 | pbrook | case 0xf003: /* fdiv Rm,Rn */ |
1194 | a7812ae4 | pbrook | gen_helper_fdiv_DT(fp0, fp0, fp1); |
1195 | a7812ae4 | pbrook | break;
|
1196 | a7812ae4 | pbrook | case 0xf004: /* fcmp/eq Rm,Rn */ |
1197 | a7812ae4 | pbrook | gen_helper_fcmp_eq_DT(fp0, fp1); |
1198 | a7812ae4 | pbrook | return;
|
1199 | a7812ae4 | pbrook | case 0xf005: /* fcmp/gt Rm,Rn */ |
1200 | a7812ae4 | pbrook | gen_helper_fcmp_gt_DT(fp0, fp1); |
1201 | a7812ae4 | pbrook | return;
|
1202 | a7812ae4 | pbrook | } |
1203 | a7812ae4 | pbrook | gen_store_fpr64(fp0, DREG(B11_8)); |
1204 | a7812ae4 | pbrook | tcg_temp_free_i64(fp0); |
1205 | a7812ae4 | pbrook | tcg_temp_free_i64(fp1); |
1206 | a7812ae4 | pbrook | } else {
|
1207 | a7812ae4 | pbrook | switch (ctx->opcode & 0xf00f) { |
1208 | a7812ae4 | pbrook | case 0xf000: /* fadd Rm,Rn */ |
1209 | 66ba317c | aurel32 | gen_helper_fadd_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1210 | a7812ae4 | pbrook | break;
|
1211 | a7812ae4 | pbrook | case 0xf001: /* fsub Rm,Rn */ |
1212 | 66ba317c | aurel32 | gen_helper_fsub_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1213 | a7812ae4 | pbrook | break;
|
1214 | a7812ae4 | pbrook | case 0xf002: /* fmul Rm,Rn */ |
1215 | 66ba317c | aurel32 | gen_helper_fmul_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1216 | a7812ae4 | pbrook | break;
|
1217 | a7812ae4 | pbrook | case 0xf003: /* fdiv Rm,Rn */ |
1218 | 66ba317c | aurel32 | gen_helper_fdiv_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1219 | a7812ae4 | pbrook | break;
|
1220 | a7812ae4 | pbrook | case 0xf004: /* fcmp/eq Rm,Rn */ |
1221 | 66ba317c | aurel32 | gen_helper_fcmp_eq_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1222 | a7812ae4 | pbrook | return;
|
1223 | a7812ae4 | pbrook | case 0xf005: /* fcmp/gt Rm,Rn */ |
1224 | 66ba317c | aurel32 | gen_helper_fcmp_gt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B7_4)]); |
1225 | a7812ae4 | pbrook | return;
|
1226 | a7812ae4 | pbrook | } |
1227 | cc4ba6a9 | aurel32 | } |
1228 | ea6cf6be | ths | } |
1229 | ea6cf6be | ths | return;
|
1230 | 5b7141a1 | aurel32 | case 0xf00e: /* fmac FR0,RM,Rn */ |
1231 | 5b7141a1 | aurel32 | { |
1232 | 5b7141a1 | aurel32 | CHECK_FPU_ENABLED |
1233 | 5b7141a1 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1234 | 5b7141a1 | aurel32 | break; /* illegal instruction */ |
1235 | 5b7141a1 | aurel32 | } else {
|
1236 | 5b7141a1 | aurel32 | gen_helper_fmac_FT(cpu_fregs[FREG(B11_8)], |
1237 | 5b7141a1 | aurel32 | cpu_fregs[FREG(0)], cpu_fregs[FREG(B7_4)], cpu_fregs[FREG(B11_8)]);
|
1238 | 5b7141a1 | aurel32 | return;
|
1239 | 5b7141a1 | aurel32 | } |
1240 | 5b7141a1 | aurel32 | } |
1241 | fdf9b3e8 | bellard | } |
1242 | fdf9b3e8 | bellard | |
1243 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xff00) { |
1244 | fdf9b3e8 | bellard | case 0xc900: /* and #imm,R0 */ |
1245 | 7efbe241 | aurel32 | tcg_gen_andi_i32(REG(0), REG(0), B7_0); |
1246 | fdf9b3e8 | bellard | return;
|
1247 | 24988dc2 | aurel32 | case 0xcd00: /* and.b #imm,@(R0,GBR) */ |
1248 | c55497ec | aurel32 | { |
1249 | c55497ec | aurel32 | TCGv addr, val; |
1250 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1251 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1252 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1253 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1254 | c55497ec | aurel32 | tcg_gen_andi_i32(val, val, B7_0); |
1255 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1256 | c55497ec | aurel32 | tcg_temp_free(val); |
1257 | c55497ec | aurel32 | tcg_temp_free(addr); |
1258 | c55497ec | aurel32 | } |
1259 | fdf9b3e8 | bellard | return;
|
1260 | fdf9b3e8 | bellard | case 0x8b00: /* bf label */ |
1261 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1262 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 2,
|
1263 | fdf9b3e8 | bellard | ctx->pc + 4 + B7_0s * 2); |
1264 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1265 | fdf9b3e8 | bellard | return;
|
1266 | fdf9b3e8 | bellard | case 0x8f00: /* bf/s label */ |
1267 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1268 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 0); |
1269 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1270 | fdf9b3e8 | bellard | return;
|
1271 | fdf9b3e8 | bellard | case 0x8900: /* bt label */ |
1272 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1273 | fdf9b3e8 | bellard | gen_conditional_jump(ctx, ctx->pc + 4 + B7_0s * 2, |
1274 | fdf9b3e8 | bellard | ctx->pc + 2);
|
1275 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1276 | fdf9b3e8 | bellard | return;
|
1277 | fdf9b3e8 | bellard | case 0x8d00: /* bt/s label */ |
1278 | fdf9b3e8 | bellard | CHECK_NOT_DELAY_SLOT |
1279 | 1000822b | aurel32 | gen_branch_slot(ctx->delayed_pc = ctx->pc + 4 + B7_0s * 2, 1); |
1280 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT_CONDITIONAL; |
1281 | fdf9b3e8 | bellard | return;
|
1282 | fdf9b3e8 | bellard | case 0x8800: /* cmp/eq #imm,R0 */ |
1283 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
|
1284 | fdf9b3e8 | bellard | return;
|
1285 | fdf9b3e8 | bellard | case 0xc400: /* mov.b @(disp,GBR),R0 */ |
1286 | c55497ec | aurel32 | { |
1287 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1288 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1289 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
1290 | c55497ec | aurel32 | tcg_temp_free(addr); |
1291 | c55497ec | aurel32 | } |
1292 | fdf9b3e8 | bellard | return;
|
1293 | fdf9b3e8 | bellard | case 0xc500: /* mov.w @(disp,GBR),R0 */ |
1294 | c55497ec | aurel32 | { |
1295 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1296 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
|
1297 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
1298 | c55497ec | aurel32 | tcg_temp_free(addr); |
1299 | c55497ec | aurel32 | } |
1300 | fdf9b3e8 | bellard | return;
|
1301 | fdf9b3e8 | bellard | case 0xc600: /* mov.l @(disp,GBR),R0 */ |
1302 | c55497ec | aurel32 | { |
1303 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1304 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
|
1305 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
|
1306 | c55497ec | aurel32 | tcg_temp_free(addr); |
1307 | c55497ec | aurel32 | } |
1308 | fdf9b3e8 | bellard | return;
|
1309 | fdf9b3e8 | bellard | case 0xc000: /* mov.b R0,@(disp,GBR) */ |
1310 | c55497ec | aurel32 | { |
1311 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1312 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
1313 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
1314 | c55497ec | aurel32 | tcg_temp_free(addr); |
1315 | c55497ec | aurel32 | } |
1316 | fdf9b3e8 | bellard | return;
|
1317 | fdf9b3e8 | bellard | case 0xc100: /* mov.w R0,@(disp,GBR) */ |
1318 | c55497ec | aurel32 | { |
1319 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1320 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2);
|
1321 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
1322 | c55497ec | aurel32 | tcg_temp_free(addr); |
1323 | c55497ec | aurel32 | } |
1324 | fdf9b3e8 | bellard | return;
|
1325 | fdf9b3e8 | bellard | case 0xc200: /* mov.l R0,@(disp,GBR) */ |
1326 | c55497ec | aurel32 | { |
1327 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1328 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4);
|
1329 | c55497ec | aurel32 | tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
|
1330 | c55497ec | aurel32 | tcg_temp_free(addr); |
1331 | c55497ec | aurel32 | } |
1332 | fdf9b3e8 | bellard | return;
|
1333 | fdf9b3e8 | bellard | case 0x8000: /* mov.b R0,@(disp,Rn) */ |
1334 | c55497ec | aurel32 | { |
1335 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1336 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1337 | c55497ec | aurel32 | tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
1338 | c55497ec | aurel32 | tcg_temp_free(addr); |
1339 | c55497ec | aurel32 | } |
1340 | fdf9b3e8 | bellard | return;
|
1341 | fdf9b3e8 | bellard | case 0x8100: /* mov.w R0,@(disp,Rn) */ |
1342 | c55497ec | aurel32 | { |
1343 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1344 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
|
1345 | c55497ec | aurel32 | tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
1346 | c55497ec | aurel32 | tcg_temp_free(addr); |
1347 | c55497ec | aurel32 | } |
1348 | fdf9b3e8 | bellard | return;
|
1349 | fdf9b3e8 | bellard | case 0x8400: /* mov.b @(disp,Rn),R0 */ |
1350 | c55497ec | aurel32 | { |
1351 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1352 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
1353 | c55497ec | aurel32 | tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
1354 | c55497ec | aurel32 | tcg_temp_free(addr); |
1355 | c55497ec | aurel32 | } |
1356 | fdf9b3e8 | bellard | return;
|
1357 | fdf9b3e8 | bellard | case 0x8500: /* mov.w @(disp,Rn),R0 */ |
1358 | c55497ec | aurel32 | { |
1359 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1360 | c55497ec | aurel32 | tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2);
|
1361 | c55497ec | aurel32 | tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
1362 | c55497ec | aurel32 | tcg_temp_free(addr); |
1363 | c55497ec | aurel32 | } |
1364 | fdf9b3e8 | bellard | return;
|
1365 | fdf9b3e8 | bellard | case 0xc700: /* mova @(disp,PC),R0 */ |
1366 | 7efbe241 | aurel32 | tcg_gen_movi_i32(REG(0), ((ctx->pc & 0xfffffffc) + 4 + B7_0 * 4) & ~3); |
1367 | fdf9b3e8 | bellard | return;
|
1368 | fdf9b3e8 | bellard | case 0xcb00: /* or #imm,R0 */ |
1369 | 7efbe241 | aurel32 | tcg_gen_ori_i32(REG(0), REG(0), B7_0); |
1370 | fdf9b3e8 | bellard | return;
|
1371 | 24988dc2 | aurel32 | case 0xcf00: /* or.b #imm,@(R0,GBR) */ |
1372 | c55497ec | aurel32 | { |
1373 | c55497ec | aurel32 | TCGv addr, val; |
1374 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1375 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1376 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1377 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1378 | c55497ec | aurel32 | tcg_gen_ori_i32(val, val, B7_0); |
1379 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1380 | c55497ec | aurel32 | tcg_temp_free(val); |
1381 | c55497ec | aurel32 | tcg_temp_free(addr); |
1382 | c55497ec | aurel32 | } |
1383 | fdf9b3e8 | bellard | return;
|
1384 | fdf9b3e8 | bellard | case 0xc300: /* trapa #imm */ |
1385 | c55497ec | aurel32 | { |
1386 | c55497ec | aurel32 | TCGv imm; |
1387 | c55497ec | aurel32 | CHECK_NOT_DELAY_SLOT |
1388 | c55497ec | aurel32 | imm = tcg_const_i32(B7_0); |
1389 | a7812ae4 | pbrook | gen_helper_trapa(imm); |
1390 | c55497ec | aurel32 | tcg_temp_free(imm); |
1391 | c55497ec | aurel32 | ctx->bstate = BS_BRANCH; |
1392 | c55497ec | aurel32 | } |
1393 | fdf9b3e8 | bellard | return;
|
1394 | fdf9b3e8 | bellard | case 0xc800: /* tst #imm,R0 */ |
1395 | c55497ec | aurel32 | { |
1396 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1397 | c55497ec | aurel32 | tcg_gen_andi_i32(val, REG(0), B7_0);
|
1398 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1399 | c55497ec | aurel32 | tcg_temp_free(val); |
1400 | c55497ec | aurel32 | } |
1401 | fdf9b3e8 | bellard | return;
|
1402 | 24988dc2 | aurel32 | case 0xcc00: /* tst.b #imm,@(R0,GBR) */ |
1403 | c55497ec | aurel32 | { |
1404 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1405 | c55497ec | aurel32 | tcg_gen_add_i32(val, REG(0), cpu_gbr);
|
1406 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, val, ctx->memidx); |
1407 | c55497ec | aurel32 | tcg_gen_andi_i32(val, val, B7_0); |
1408 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1409 | c55497ec | aurel32 | tcg_temp_free(val); |
1410 | c55497ec | aurel32 | } |
1411 | fdf9b3e8 | bellard | return;
|
1412 | fdf9b3e8 | bellard | case 0xca00: /* xor #imm,R0 */ |
1413 | 7efbe241 | aurel32 | tcg_gen_xori_i32(REG(0), REG(0), B7_0); |
1414 | fdf9b3e8 | bellard | return;
|
1415 | 24988dc2 | aurel32 | case 0xce00: /* xor.b #imm,@(R0,GBR) */ |
1416 | c55497ec | aurel32 | { |
1417 | c55497ec | aurel32 | TCGv addr, val; |
1418 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1419 | c55497ec | aurel32 | tcg_gen_add_i32(addr, REG(0), cpu_gbr);
|
1420 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1421 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1422 | c55497ec | aurel32 | tcg_gen_xori_i32(val, val, B7_0); |
1423 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1424 | c55497ec | aurel32 | tcg_temp_free(val); |
1425 | c55497ec | aurel32 | tcg_temp_free(addr); |
1426 | c55497ec | aurel32 | } |
1427 | fdf9b3e8 | bellard | return;
|
1428 | fdf9b3e8 | bellard | } |
1429 | fdf9b3e8 | bellard | |
1430 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf08f) { |
1431 | fdf9b3e8 | bellard | case 0x408e: /* ldc Rm,Rn_BANK */ |
1432 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1433 | 7efbe241 | aurel32 | tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); |
1434 | fdf9b3e8 | bellard | return;
|
1435 | fdf9b3e8 | bellard | case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
1436 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1437 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx); |
1438 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1439 | fdf9b3e8 | bellard | return;
|
1440 | fdf9b3e8 | bellard | case 0x0082: /* stc Rm_BANK,Rn */ |
1441 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1442 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); |
1443 | fdf9b3e8 | bellard | return;
|
1444 | fdf9b3e8 | bellard | case 0x4083: /* stc.l Rm_BANK,@-Rn */ |
1445 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1446 | c55497ec | aurel32 | { |
1447 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1448 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1449 | c55497ec | aurel32 | tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx); |
1450 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); |
1451 | c55497ec | aurel32 | tcg_temp_free(addr); |
1452 | c55497ec | aurel32 | } |
1453 | fdf9b3e8 | bellard | return;
|
1454 | fdf9b3e8 | bellard | } |
1455 | fdf9b3e8 | bellard | |
1456 | fdf9b3e8 | bellard | switch (ctx->opcode & 0xf0ff) { |
1457 | fdf9b3e8 | bellard | case 0x0023: /* braf Rn */ |
1458 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1459 | 7efbe241 | aurel32 | tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->pc + 4);
|
1460 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1461 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1462 | fdf9b3e8 | bellard | return;
|
1463 | fdf9b3e8 | bellard | case 0x0003: /* bsrf Rn */ |
1464 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1465 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1466 | 7efbe241 | aurel32 | tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); |
1467 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1468 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1469 | fdf9b3e8 | bellard | return;
|
1470 | fdf9b3e8 | bellard | case 0x4015: /* cmp/pl Rn */ |
1471 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
|
1472 | fdf9b3e8 | bellard | return;
|
1473 | fdf9b3e8 | bellard | case 0x4011: /* cmp/pz Rn */ |
1474 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
|
1475 | fdf9b3e8 | bellard | return;
|
1476 | fdf9b3e8 | bellard | case 0x4010: /* dt Rn */ |
1477 | 7efbe241 | aurel32 | tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
|
1478 | 7efbe241 | aurel32 | gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
|
1479 | fdf9b3e8 | bellard | return;
|
1480 | fdf9b3e8 | bellard | case 0x402b: /* jmp @Rn */ |
1481 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1482 | 7efbe241 | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
1483 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1484 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1485 | fdf9b3e8 | bellard | return;
|
1486 | fdf9b3e8 | bellard | case 0x400b: /* jsr @Rn */ |
1487 | 7efbe241 | aurel32 | CHECK_NOT_DELAY_SLOT |
1488 | 1000822b | aurel32 | tcg_gen_movi_i32(cpu_pr, ctx->pc + 4);
|
1489 | 7efbe241 | aurel32 | tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); |
1490 | fdf9b3e8 | bellard | ctx->flags |= DELAY_SLOT; |
1491 | fdf9b3e8 | bellard | ctx->delayed_pc = (uint32_t) - 1;
|
1492 | fdf9b3e8 | bellard | return;
|
1493 | fe25591e | aurel32 | case 0x400e: /* ldc Rm,SR */ |
1494 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1495 | 7efbe241 | aurel32 | tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
|
1496 | 390af821 | aurel32 | ctx->bstate = BS_STOP; |
1497 | 390af821 | aurel32 | return;
|
1498 | fe25591e | aurel32 | case 0x4007: /* ldc.l @Rm+,SR */ |
1499 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1500 | c55497ec | aurel32 | { |
1501 | a7812ae4 | pbrook | TCGv val = tcg_temp_new(); |
1502 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx); |
1503 | c55497ec | aurel32 | tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
|
1504 | c55497ec | aurel32 | tcg_temp_free(val); |
1505 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1506 | c55497ec | aurel32 | ctx->bstate = BS_STOP; |
1507 | c55497ec | aurel32 | } |
1508 | 390af821 | aurel32 | return;
|
1509 | fe25591e | aurel32 | case 0x0002: /* stc SR,Rn */ |
1510 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1511 | 7efbe241 | aurel32 | tcg_gen_mov_i32(REG(B11_8), cpu_sr); |
1512 | 390af821 | aurel32 | return;
|
1513 | fe25591e | aurel32 | case 0x4003: /* stc SR,@-Rn */ |
1514 | fe25591e | aurel32 | CHECK_PRIVILEGED |
1515 | c55497ec | aurel32 | { |
1516 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1517 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1518 | c55497ec | aurel32 | tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx); |
1519 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); |
1520 | c55497ec | aurel32 | tcg_temp_free(addr); |
1521 | c55497ec | aurel32 | } |
1522 | 390af821 | aurel32 | return;
|
1523 | 8e9b0678 | Alexandre Courbot | #define LD(reg,ldnum,ldpnum,prechk) \
|
1524 | fdf9b3e8 | bellard | case ldnum: \
|
1525 | fe25591e | aurel32 | prechk \ |
1526 | 7efbe241 | aurel32 | tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ |
1527 | fdf9b3e8 | bellard | return; \
|
1528 | fdf9b3e8 | bellard | case ldpnum: \
|
1529 | fe25591e | aurel32 | prechk \ |
1530 | 7efbe241 | aurel32 | tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \ |
1531 | 7efbe241 | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \
|
1532 | 8e9b0678 | Alexandre Courbot | return;
|
1533 | 8e9b0678 | Alexandre Courbot | #define ST(reg,stnum,stpnum,prechk) \
|
1534 | fdf9b3e8 | bellard | case stnum: \
|
1535 | fe25591e | aurel32 | prechk \ |
1536 | 7efbe241 | aurel32 | tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ |
1537 | fdf9b3e8 | bellard | return; \
|
1538 | fdf9b3e8 | bellard | case stpnum: \
|
1539 | fe25591e | aurel32 | prechk \ |
1540 | c55497ec | aurel32 | { \ |
1541 | 3101e99c | Aurelien Jarno | TCGv addr = tcg_temp_new(); \ |
1542 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4); \
|
1543 | c55497ec | aurel32 | tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \ |
1544 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); \ |
1545 | c55497ec | aurel32 | tcg_temp_free(addr); \ |
1546 | 86e0abc7 | aurel32 | } \ |
1547 | fdf9b3e8 | bellard | return;
|
1548 | 8e9b0678 | Alexandre Courbot | #define LDST(reg,ldnum,ldpnum,stnum,stpnum,prechk) \
|
1549 | 8e9b0678 | Alexandre Courbot | LD(reg,ldnum,ldpnum,prechk) \ |
1550 | 8e9b0678 | Alexandre Courbot | ST(reg,stnum,stpnum,prechk) |
1551 | fe25591e | aurel32 | LDST(gbr, 0x401e, 0x4017, 0x0012, 0x4013, {}) |
1552 | fe25591e | aurel32 | LDST(vbr, 0x402e, 0x4027, 0x0022, 0x4023, CHECK_PRIVILEGED) |
1553 | fe25591e | aurel32 | LDST(ssr, 0x403e, 0x4037, 0x0032, 0x4033, CHECK_PRIVILEGED) |
1554 | fe25591e | aurel32 | LDST(spc, 0x404e, 0x4047, 0x0042, 0x4043, CHECK_PRIVILEGED) |
1555 | 935fc175 | Alexandre Courbot | ST(sgr, 0x003a, 0x4032, CHECK_PRIVILEGED) |
1556 | 935fc175 | Alexandre Courbot | LD(sgr, 0x403a, 0x4036, CHECK_PRIVILEGED if (!(ctx->features & SH_FEATURE_SH4A)) break;) |
1557 | fe25591e | aurel32 | LDST(dbr, 0x40fa, 0x40f6, 0x00fa, 0x40f2, CHECK_PRIVILEGED) |
1558 | fe25591e | aurel32 | LDST(mach, 0x400a, 0x4006, 0x000a, 0x4002, {}) |
1559 | fe25591e | aurel32 | LDST(macl, 0x401a, 0x4016, 0x001a, 0x4012, {}) |
1560 | fe25591e | aurel32 | LDST(pr, 0x402a, 0x4026, 0x002a, 0x4022, {}) |
1561 | d8299bcc | aurel32 | LDST(fpul, 0x405a, 0x4056, 0x005a, 0x4052, {CHECK_FPU_ENABLED}) |
1562 | 390af821 | aurel32 | case 0x406a: /* lds Rm,FPSCR */ |
1563 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1564 | a7812ae4 | pbrook | gen_helper_ld_fpscr(REG(B11_8)); |
1565 | 390af821 | aurel32 | ctx->bstate = BS_STOP; |
1566 | 390af821 | aurel32 | return;
|
1567 | 390af821 | aurel32 | case 0x4066: /* lds.l @Rm+,FPSCR */ |
1568 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1569 | c55497ec | aurel32 | { |
1570 | a7812ae4 | pbrook | TCGv addr = tcg_temp_new(); |
1571 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx); |
1572 | c55497ec | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1573 | a7812ae4 | pbrook | gen_helper_ld_fpscr(addr); |
1574 | c55497ec | aurel32 | tcg_temp_free(addr); |
1575 | c55497ec | aurel32 | ctx->bstate = BS_STOP; |
1576 | c55497ec | aurel32 | } |
1577 | 390af821 | aurel32 | return;
|
1578 | 390af821 | aurel32 | case 0x006a: /* sts FPSCR,Rn */ |
1579 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1580 | c55497ec | aurel32 | tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff);
|
1581 | 390af821 | aurel32 | return;
|
1582 | 390af821 | aurel32 | case 0x4062: /* sts FPSCR,@-Rn */ |
1583 | d8299bcc | aurel32 | CHECK_FPU_ENABLED |
1584 | c55497ec | aurel32 | { |
1585 | c55497ec | aurel32 | TCGv addr, val; |
1586 | a7812ae4 | pbrook | val = tcg_temp_new(); |
1587 | c55497ec | aurel32 | tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff);
|
1588 | a7812ae4 | pbrook | addr = tcg_temp_new(); |
1589 | c55497ec | aurel32 | tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
1590 | c55497ec | aurel32 | tcg_gen_qemu_st32(val, addr, ctx->memidx); |
1591 | 3101e99c | Aurelien Jarno | tcg_gen_mov_i32(REG(B11_8), addr); |
1592 | c55497ec | aurel32 | tcg_temp_free(addr); |
1593 | c55497ec | aurel32 | tcg_temp_free(val); |
1594 | c55497ec | aurel32 | } |
1595 | 390af821 | aurel32 | return;
|
1596 | fdf9b3e8 | bellard | case 0x00c3: /* movca.l R0,@Rm */ |
1597 | 852d481f | edgar_igl | { |
1598 | 852d481f | edgar_igl | TCGv val = tcg_temp_new(); |
1599 | 852d481f | edgar_igl | tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx); |
1600 | 852d481f | edgar_igl | gen_helper_movcal (REG(B11_8), val); |
1601 | 852d481f | edgar_igl | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
|
1602 | 852d481f | edgar_igl | } |
1603 | 852d481f | edgar_igl | ctx->has_movcal = 1;
|
1604 | fdf9b3e8 | bellard | return;
|
1605 | 7526aa2d | aurel32 | case 0x40a9: |
1606 | 7526aa2d | aurel32 | /* MOVUA.L @Rm,R0 (Rm) -> R0
|
1607 | 7526aa2d | aurel32 | Load non-boundary-aligned data */
|
1608 | 7526aa2d | aurel32 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
1609 | 7526aa2d | aurel32 | return;
|
1610 | 7526aa2d | aurel32 | case 0x40e9: |
1611 | 7526aa2d | aurel32 | /* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm
|
1612 | 7526aa2d | aurel32 | Load non-boundary-aligned data */
|
1613 | 7526aa2d | aurel32 | tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
1614 | 7526aa2d | aurel32 | tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
1615 | 7526aa2d | aurel32 | return;
|
1616 | fdf9b3e8 | bellard | case 0x0029: /* movt Rn */ |
1617 | 7efbe241 | aurel32 | tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T); |
1618 | fdf9b3e8 | bellard | return;
|
1619 | 66c7c806 | aurel32 | case 0x0073: |
1620 | 66c7c806 | aurel32 | /* MOVCO.L
|
1621 | 66c7c806 | aurel32 | LDST -> T
|
1622 | 66c7c806 | aurel32 | If (T == 1) R0 -> (Rn)
|
1623 | 66c7c806 | aurel32 | 0 -> LDST
|
1624 | 66c7c806 | aurel32 | */
|
1625 | 66c7c806 | aurel32 | if (ctx->features & SH_FEATURE_SH4A) {
|
1626 | 66c7c806 | aurel32 | int label = gen_new_label();
|
1627 | 66c7c806 | aurel32 | gen_clr_t(); |
1628 | 66c7c806 | aurel32 | tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst); |
1629 | 66c7c806 | aurel32 | tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
|
1630 | 66c7c806 | aurel32 | tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
|
1631 | 66c7c806 | aurel32 | gen_set_label(label); |
1632 | 66c7c806 | aurel32 | tcg_gen_movi_i32(cpu_ldst, 0);
|
1633 | 66c7c806 | aurel32 | return;
|
1634 | 66c7c806 | aurel32 | } else
|
1635 | 66c7c806 | aurel32 | break;
|
1636 | 66c7c806 | aurel32 | case 0x0063: |
1637 | 66c7c806 | aurel32 | /* MOVLI.L @Rm,R0
|
1638 | 66c7c806 | aurel32 | 1 -> LDST
|
1639 | 66c7c806 | aurel32 | (Rm) -> R0
|
1640 | 66c7c806 | aurel32 | When interrupt/exception
|
1641 | 66c7c806 | aurel32 | occurred 0 -> LDST
|
1642 | 66c7c806 | aurel32 | */
|
1643 | 66c7c806 | aurel32 | if (ctx->features & SH_FEATURE_SH4A) {
|
1644 | 66c7c806 | aurel32 | tcg_gen_movi_i32(cpu_ldst, 0);
|
1645 | 66c7c806 | aurel32 | tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);
|
1646 | 66c7c806 | aurel32 | tcg_gen_movi_i32(cpu_ldst, 1);
|
1647 | 66c7c806 | aurel32 | return;
|
1648 | 66c7c806 | aurel32 | } else
|
1649 | 66c7c806 | aurel32 | break;
|
1650 | fdf9b3e8 | bellard | case 0x0093: /* ocbi @Rn */ |
1651 | c55497ec | aurel32 | { |
1652 | 852d481f | edgar_igl | gen_helper_ocbi (REG(B11_8)); |
1653 | c55497ec | aurel32 | } |
1654 | fdf9b3e8 | bellard | return;
|
1655 | 24988dc2 | aurel32 | case 0x00a3: /* ocbp @Rn */ |
1656 | c55497ec | aurel32 | { |
1657 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1658 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1659 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1660 | c55497ec | aurel32 | } |
1661 | fdf9b3e8 | bellard | return;
|
1662 | fdf9b3e8 | bellard | case 0x00b3: /* ocbwb @Rn */ |
1663 | c55497ec | aurel32 | { |
1664 | a7812ae4 | pbrook | TCGv dummy = tcg_temp_new(); |
1665 | c55497ec | aurel32 | tcg_gen_qemu_ld32s(dummy, REG(B11_8), ctx->memidx); |
1666 | c55497ec | aurel32 | tcg_temp_free(dummy); |
1667 | c55497ec | aurel32 | } |
1668 | fdf9b3e8 | bellard | return;
|
1669 | fdf9b3e8 | bellard | case 0x0083: /* pref @Rn */ |
1670 | fdf9b3e8 | bellard | return;
|
1671 | 71968fa6 | aurel32 | case 0x00d3: /* prefi @Rn */ |
1672 | 71968fa6 | aurel32 | if (ctx->features & SH_FEATURE_SH4A)
|
1673 | 71968fa6 | aurel32 | return;
|
1674 | 71968fa6 | aurel32 | else
|
1675 | 71968fa6 | aurel32 | break;
|
1676 | 71968fa6 | aurel32 | case 0x00e3: /* icbi @Rn */ |
1677 | 71968fa6 | aurel32 | if (ctx->features & SH_FEATURE_SH4A)
|
1678 | 71968fa6 | aurel32 | return;
|
1679 | 71968fa6 | aurel32 | else
|
1680 | 71968fa6 | aurel32 | break;
|
1681 | 71968fa6 | aurel32 | case 0x00ab: /* synco */ |
1682 | 71968fa6 | aurel32 | if (ctx->features & SH_FEATURE_SH4A)
|
1683 | 71968fa6 | aurel32 | return;
|
1684 | 71968fa6 | aurel32 | else
|
1685 | 71968fa6 | aurel32 | break;
|
1686 | fdf9b3e8 | bellard | case 0x4024: /* rotcl Rn */ |
1687 | c55497ec | aurel32 | { |
1688 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1689 | c55497ec | aurel32 | tcg_gen_mov_i32(tmp, cpu_sr); |
1690 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1691 | c55497ec | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1692 | c55497ec | aurel32 | gen_copy_bit_i32(REG(B11_8), 0, tmp, 0); |
1693 | c55497ec | aurel32 | tcg_temp_free(tmp); |
1694 | c55497ec | aurel32 | } |
1695 | fdf9b3e8 | bellard | return;
|
1696 | fdf9b3e8 | bellard | case 0x4025: /* rotcr Rn */ |
1697 | c55497ec | aurel32 | { |
1698 | a7812ae4 | pbrook | TCGv tmp = tcg_temp_new(); |
1699 | c55497ec | aurel32 | tcg_gen_mov_i32(tmp, cpu_sr); |
1700 | c55497ec | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1701 | c55497ec | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1702 | c55497ec | aurel32 | gen_copy_bit_i32(REG(B11_8), 31, tmp, 0); |
1703 | c55497ec | aurel32 | tcg_temp_free(tmp); |
1704 | c55497ec | aurel32 | } |
1705 | fdf9b3e8 | bellard | return;
|
1706 | fdf9b3e8 | bellard | case 0x4004: /* rotl Rn */ |
1707 | 2411fde9 | Aurelien Jarno | tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1);
|
1708 | 2411fde9 | Aurelien Jarno | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1709 | fdf9b3e8 | bellard | return;
|
1710 | fdf9b3e8 | bellard | case 0x4005: /* rotr Rn */ |
1711 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1712 | 2411fde9 | Aurelien Jarno | tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1);
|
1713 | fdf9b3e8 | bellard | return;
|
1714 | fdf9b3e8 | bellard | case 0x4000: /* shll Rn */ |
1715 | fdf9b3e8 | bellard | case 0x4020: /* shal Rn */ |
1716 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31); |
1717 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
1718 | fdf9b3e8 | bellard | return;
|
1719 | fdf9b3e8 | bellard | case 0x4021: /* shar Rn */ |
1720 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1721 | 7efbe241 | aurel32 | tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
|
1722 | fdf9b3e8 | bellard | return;
|
1723 | fdf9b3e8 | bellard | case 0x4001: /* shlr Rn */ |
1724 | 7efbe241 | aurel32 | gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0); |
1725 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
1726 | fdf9b3e8 | bellard | return;
|
1727 | fdf9b3e8 | bellard | case 0x4008: /* shll2 Rn */ |
1728 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2);
|
1729 | fdf9b3e8 | bellard | return;
|
1730 | fdf9b3e8 | bellard | case 0x4018: /* shll8 Rn */ |
1731 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8);
|
1732 | fdf9b3e8 | bellard | return;
|
1733 | fdf9b3e8 | bellard | case 0x4028: /* shll16 Rn */ |
1734 | 7efbe241 | aurel32 | tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16);
|
1735 | fdf9b3e8 | bellard | return;
|
1736 | fdf9b3e8 | bellard | case 0x4009: /* shlr2 Rn */ |
1737 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2);
|
1738 | fdf9b3e8 | bellard | return;
|
1739 | fdf9b3e8 | bellard | case 0x4019: /* shlr8 Rn */ |
1740 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8);
|
1741 | fdf9b3e8 | bellard | return;
|
1742 | fdf9b3e8 | bellard | case 0x4029: /* shlr16 Rn */ |
1743 | 7efbe241 | aurel32 | tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16);
|
1744 | fdf9b3e8 | bellard | return;
|
1745 | fdf9b3e8 | bellard | case 0x401b: /* tas.b @Rn */ |
1746 | c55497ec | aurel32 | { |
1747 | c55497ec | aurel32 | TCGv addr, val; |
1748 | df9247b2 | aurel32 | addr = tcg_temp_local_new(); |
1749 | c55497ec | aurel32 | tcg_gen_mov_i32(addr, REG(B11_8)); |
1750 | df9247b2 | aurel32 | val = tcg_temp_local_new(); |
1751 | c55497ec | aurel32 | tcg_gen_qemu_ld8u(val, addr, ctx->memidx); |
1752 | c55497ec | aurel32 | gen_cmp_imm(TCG_COND_EQ, val, 0);
|
1753 | c55497ec | aurel32 | tcg_gen_ori_i32(val, val, 0x80);
|
1754 | c55497ec | aurel32 | tcg_gen_qemu_st8(val, addr, ctx->memidx); |
1755 | c55497ec | aurel32 | tcg_temp_free(val); |
1756 | c55497ec | aurel32 | tcg_temp_free(addr); |
1757 | c55497ec | aurel32 | } |
1758 | fdf9b3e8 | bellard | return;
|
1759 | e67888a7 | ths | case 0xf00d: /* fsts FPUL,FRn - FPSCR: Nothing */ |
1760 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1761 | f6198371 | aurel32 | tcg_gen_mov_i32(cpu_fregs[FREG(B11_8)], cpu_fpul); |
1762 | eda9b09b | bellard | return;
|
1763 | e67888a7 | ths | case 0xf01d: /* flds FRm,FPUL - FPSCR: Nothing */ |
1764 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1765 | f6198371 | aurel32 | tcg_gen_mov_i32(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
1766 | eda9b09b | bellard | return;
|
1767 | e67888a7 | ths | case 0xf02d: /* float FPUL,FRn/DRn - FPSCR: R[PR,Enable.I]/W[Cause,Flag] */ |
1768 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1769 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1770 | a7812ae4 | pbrook | TCGv_i64 fp; |
1771 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1772 | ea6cf6be | ths | break; /* illegal instruction */ |
1773 | a7812ae4 | pbrook | fp = tcg_temp_new_i64(); |
1774 | a7812ae4 | pbrook | gen_helper_float_DT(fp, cpu_fpul); |
1775 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1776 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1777 | ea6cf6be | ths | } |
1778 | ea6cf6be | ths | else {
|
1779 | 66ba317c | aurel32 | gen_helper_float_FT(cpu_fregs[FREG(B11_8)], cpu_fpul); |
1780 | ea6cf6be | ths | } |
1781 | ea6cf6be | ths | return;
|
1782 | e67888a7 | ths | case 0xf03d: /* ftrc FRm/DRm,FPUL - FPSCR: R[PR,Enable.V]/W[Cause,Flag] */ |
1783 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1784 | ea6cf6be | ths | if (ctx->fpscr & FPSCR_PR) {
|
1785 | a7812ae4 | pbrook | TCGv_i64 fp; |
1786 | ea6cf6be | ths | if (ctx->opcode & 0x0100) |
1787 | ea6cf6be | ths | break; /* illegal instruction */ |
1788 | a7812ae4 | pbrook | fp = tcg_temp_new_i64(); |
1789 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1790 | a7812ae4 | pbrook | gen_helper_ftrc_DT(cpu_fpul, fp); |
1791 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1792 | ea6cf6be | ths | } |
1793 | ea6cf6be | ths | else {
|
1794 | 66ba317c | aurel32 | gen_helper_ftrc_FT(cpu_fpul, cpu_fregs[FREG(B11_8)]); |
1795 | ea6cf6be | ths | } |
1796 | ea6cf6be | ths | return;
|
1797 | 24988dc2 | aurel32 | case 0xf04d: /* fneg FRn/DRn - FPSCR: Nothing */ |
1798 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1799 | 7fdf924f | aurel32 | { |
1800 | 66ba317c | aurel32 | gen_helper_fneg_T(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1801 | 7fdf924f | aurel32 | } |
1802 | 24988dc2 | aurel32 | return;
|
1803 | 24988dc2 | aurel32 | case 0xf05d: /* fabs FRn/DRn */ |
1804 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1805 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1806 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1807 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1808 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1809 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1810 | a7812ae4 | pbrook | gen_helper_fabs_DT(fp, fp); |
1811 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1812 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1813 | 24988dc2 | aurel32 | } else {
|
1814 | 66ba317c | aurel32 | gen_helper_fabs_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1815 | 24988dc2 | aurel32 | } |
1816 | 24988dc2 | aurel32 | return;
|
1817 | 24988dc2 | aurel32 | case 0xf06d: /* fsqrt FRn */ |
1818 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1819 | 24988dc2 | aurel32 | if (ctx->fpscr & FPSCR_PR) {
|
1820 | 24988dc2 | aurel32 | if (ctx->opcode & 0x0100) |
1821 | 24988dc2 | aurel32 | break; /* illegal instruction */ |
1822 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1823 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1824 | a7812ae4 | pbrook | gen_helper_fsqrt_DT(fp, fp); |
1825 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1826 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1827 | 24988dc2 | aurel32 | } else {
|
1828 | 66ba317c | aurel32 | gen_helper_fsqrt_FT(cpu_fregs[FREG(B11_8)], cpu_fregs[FREG(B11_8)]); |
1829 | 24988dc2 | aurel32 | } |
1830 | 24988dc2 | aurel32 | return;
|
1831 | 24988dc2 | aurel32 | case 0xf07d: /* fsrra FRn */ |
1832 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1833 | 24988dc2 | aurel32 | break;
|
1834 | e67888a7 | ths | case 0xf08d: /* fldi0 FRn - FPSCR: R[PR] */ |
1835 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1836 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1837 | 66ba317c | aurel32 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0);
|
1838 | ea6cf6be | ths | } |
1839 | 12d96138 | aurel32 | return;
|
1840 | e67888a7 | ths | case 0xf09d: /* fldi1 FRn - FPSCR: R[PR] */ |
1841 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1842 | ea6cf6be | ths | if (!(ctx->fpscr & FPSCR_PR)) {
|
1843 | 66ba317c | aurel32 | tcg_gen_movi_i32(cpu_fregs[FREG(B11_8)], 0x3f800000);
|
1844 | ea6cf6be | ths | } |
1845 | 12d96138 | aurel32 | return;
|
1846 | 24988dc2 | aurel32 | case 0xf0ad: /* fcnvsd FPUL,DRn */ |
1847 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1848 | cc4ba6a9 | aurel32 | { |
1849 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1850 | a7812ae4 | pbrook | gen_helper_fcnvsd_FT_DT(fp, cpu_fpul); |
1851 | cc4ba6a9 | aurel32 | gen_store_fpr64(fp, DREG(B11_8)); |
1852 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1853 | cc4ba6a9 | aurel32 | } |
1854 | 24988dc2 | aurel32 | return;
|
1855 | 24988dc2 | aurel32 | case 0xf0bd: /* fcnvds DRn,FPUL */ |
1856 | f6198371 | aurel32 | CHECK_FPU_ENABLED |
1857 | cc4ba6a9 | aurel32 | { |
1858 | a7812ae4 | pbrook | TCGv_i64 fp = tcg_temp_new_i64(); |
1859 | cc4ba6a9 | aurel32 | gen_load_fpr64(fp, DREG(B11_8)); |
1860 | a7812ae4 | pbrook | gen_helper_fcnvds_DT_FT(cpu_fpul, fp); |
1861 | a7812ae4 | pbrook | tcg_temp_free_i64(fp); |
1862 | cc4ba6a9 | aurel32 | } |
1863 | 24988dc2 | aurel32 | return;
|
1864 | af8c2bde | Aurelien Jarno | case 0xf0ed: /* fipr FVm,FVn */ |
1865 | af8c2bde | Aurelien Jarno | CHECK_FPU_ENABLED |
1866 | af8c2bde | Aurelien Jarno | if ((ctx->fpscr & FPSCR_PR) == 0) { |
1867 | af8c2bde | Aurelien Jarno | TCGv m, n; |
1868 | af8c2bde | Aurelien Jarno | m = tcg_const_i32((ctx->opcode >> 16) & 3); |
1869 | af8c2bde | Aurelien Jarno | n = tcg_const_i32((ctx->opcode >> 18) & 3); |
1870 | af8c2bde | Aurelien Jarno | gen_helper_fipr(m, n); |
1871 | af8c2bde | Aurelien Jarno | tcg_temp_free(m); |
1872 | af8c2bde | Aurelien Jarno | tcg_temp_free(n); |
1873 | af8c2bde | Aurelien Jarno | return;
|
1874 | af8c2bde | Aurelien Jarno | } |
1875 | af8c2bde | Aurelien Jarno | break;
|
1876 | 17075f10 | Aurelien Jarno | case 0xf0fd: /* ftrv XMTRX,FVn */ |
1877 | 17075f10 | Aurelien Jarno | CHECK_FPU_ENABLED |
1878 | 17075f10 | Aurelien Jarno | if ((ctx->opcode & 0x0300) == 0x0100 && |
1879 | 17075f10 | Aurelien Jarno | (ctx->fpscr & FPSCR_PR) == 0) {
|
1880 | 17075f10 | Aurelien Jarno | TCGv n; |
1881 | 17075f10 | Aurelien Jarno | n = tcg_const_i32((ctx->opcode >> 18) & 3); |
1882 | 17075f10 | Aurelien Jarno | gen_helper_ftrv(n); |
1883 | 17075f10 | Aurelien Jarno | tcg_temp_free(n); |
1884 | 17075f10 | Aurelien Jarno | return;
|
1885 | 17075f10 | Aurelien Jarno | } |
1886 | 17075f10 | Aurelien Jarno | break;
|
1887 | fdf9b3e8 | bellard | } |
1888 | bacc637a | aurel32 | #if 0
|
1889 | fdf9b3e8 | bellard | fprintf(stderr, "unknown instruction 0x%04x at pc 0x%08x\n",
|
1890 | fdf9b3e8 | bellard | ctx->opcode, ctx->pc);
|
1891 | bacc637a | aurel32 | fflush(stderr);
|
1892 | bacc637a | aurel32 | #endif
|
1893 | 86865c5f | Aurelien Jarno | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
1894 | 86865c5f | Aurelien Jarno | gen_helper_raise_slot_illegal_instruction(); |
1895 | 86865c5f | Aurelien Jarno | } else {
|
1896 | 86865c5f | Aurelien Jarno | gen_helper_raise_illegal_instruction(); |
1897 | 86865c5f | Aurelien Jarno | } |
1898 | 823029f9 | ths | ctx->bstate = BS_EXCP; |
1899 | 823029f9 | ths | } |
1900 | 823029f9 | ths | |
1901 | b1d8e52e | blueswir1 | static void decode_opc(DisasContext * ctx) |
1902 | 823029f9 | ths | { |
1903 | 823029f9 | ths | uint32_t old_flags = ctx->flags; |
1904 | 823029f9 | ths | |
1905 | be15c50d | Aurelien Jarno | if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
|
1906 | be15c50d | Aurelien Jarno | tcg_gen_debug_insn_start(ctx->pc); |
1907 | be15c50d | Aurelien Jarno | } |
1908 | be15c50d | Aurelien Jarno | |
1909 | 823029f9 | ths | _decode_opc(ctx); |
1910 | 823029f9 | ths | |
1911 | 823029f9 | ths | if (old_flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
|
1912 | 823029f9 | ths | if (ctx->flags & DELAY_SLOT_CLEARME) {
|
1913 | 1000822b | aurel32 | gen_store_flags(0);
|
1914 | 274a9e70 | aurel32 | } else {
|
1915 | 274a9e70 | aurel32 | /* go out of the delay slot */
|
1916 | 274a9e70 | aurel32 | uint32_t new_flags = ctx->flags; |
1917 | 274a9e70 | aurel32 | new_flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); |
1918 | 1000822b | aurel32 | gen_store_flags(new_flags); |
1919 | 823029f9 | ths | } |
1920 | 823029f9 | ths | ctx->flags = 0;
|
1921 | 823029f9 | ths | ctx->bstate = BS_BRANCH; |
1922 | 823029f9 | ths | if (old_flags & DELAY_SLOT_CONDITIONAL) {
|
1923 | 823029f9 | ths | gen_delayed_conditional_jump(ctx); |
1924 | 823029f9 | ths | } else if (old_flags & DELAY_SLOT) { |
1925 | 823029f9 | ths | gen_jump(ctx); |
1926 | 823029f9 | ths | } |
1927 | 823029f9 | ths | |
1928 | 823029f9 | ths | } |
1929 | 274a9e70 | aurel32 | |
1930 | 274a9e70 | aurel32 | /* go into a delay slot */
|
1931 | 274a9e70 | aurel32 | if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL))
|
1932 | 1000822b | aurel32 | gen_store_flags(ctx->flags); |
1933 | fdf9b3e8 | bellard | } |
1934 | fdf9b3e8 | bellard | |
1935 | 2cfc5f17 | ths | static inline void |
1936 | 820e00f2 | ths | gen_intermediate_code_internal(CPUState * env, TranslationBlock * tb, |
1937 | 820e00f2 | ths | int search_pc)
|
1938 | fdf9b3e8 | bellard | { |
1939 | fdf9b3e8 | bellard | DisasContext ctx; |
1940 | fdf9b3e8 | bellard | target_ulong pc_start; |
1941 | fdf9b3e8 | bellard | static uint16_t *gen_opc_end;
|
1942 | a1d1bb31 | aliguori | CPUBreakpoint *bp; |
1943 | 355fb23d | pbrook | int i, ii;
|
1944 | 2e70f6ef | pbrook | int num_insns;
|
1945 | 2e70f6ef | pbrook | int max_insns;
|
1946 | fdf9b3e8 | bellard | |
1947 | fdf9b3e8 | bellard | pc_start = tb->pc; |
1948 | fdf9b3e8 | bellard | gen_opc_end = gen_opc_buf + OPC_MAX_SIZE; |
1949 | fdf9b3e8 | bellard | ctx.pc = pc_start; |
1950 | 823029f9 | ths | ctx.flags = (uint32_t)tb->flags; |
1951 | 823029f9 | ths | ctx.bstate = BS_NONE; |
1952 | fdf9b3e8 | bellard | ctx.sr = env->sr; |
1953 | eda9b09b | bellard | ctx.fpscr = env->fpscr; |
1954 | 1f486815 | Aurelien Jarno | ctx.memidx = (env->sr & SR_MD) == 0 ? 1 : 0; |
1955 | 9854bc46 | pbrook | /* We don't know if the delayed pc came from a dynamic or static branch,
|
1956 | 9854bc46 | pbrook | so assume it is a dynamic branch. */
|
1957 | 823029f9 | ths | ctx.delayed_pc = -1; /* use delayed pc from env pointer */ |
1958 | fdf9b3e8 | bellard | ctx.tb = tb; |
1959 | fdf9b3e8 | bellard | ctx.singlestep_enabled = env->singlestep_enabled; |
1960 | 71968fa6 | aurel32 | ctx.features = env->features; |
1961 | 852d481f | edgar_igl | ctx.has_movcal = (tb->flags & TB_FLAG_PENDING_MOVCA); |
1962 | fdf9b3e8 | bellard | |
1963 | 355fb23d | pbrook | ii = -1;
|
1964 | 2e70f6ef | pbrook | num_insns = 0;
|
1965 | 2e70f6ef | pbrook | max_insns = tb->cflags & CF_COUNT_MASK; |
1966 | 2e70f6ef | pbrook | if (max_insns == 0) |
1967 | 2e70f6ef | pbrook | max_insns = CF_COUNT_MASK; |
1968 | 2e70f6ef | pbrook | gen_icount_start(); |
1969 | 823029f9 | ths | while (ctx.bstate == BS_NONE && gen_opc_ptr < gen_opc_end) {
|
1970 | 72cf2d4f | Blue Swirl | if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
1971 | 72cf2d4f | Blue Swirl | QTAILQ_FOREACH(bp, &env->breakpoints, entry) { |
1972 | a1d1bb31 | aliguori | if (ctx.pc == bp->pc) {
|
1973 | fdf9b3e8 | bellard | /* We have hit a breakpoint - make sure PC is up-to-date */
|
1974 | 3a8a44c4 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
1975 | a7812ae4 | pbrook | gen_helper_debug(); |
1976 | 823029f9 | ths | ctx.bstate = BS_EXCP; |
1977 | fdf9b3e8 | bellard | break;
|
1978 | fdf9b3e8 | bellard | } |
1979 | fdf9b3e8 | bellard | } |
1980 | fdf9b3e8 | bellard | } |
1981 | 355fb23d | pbrook | if (search_pc) {
|
1982 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
1983 | 355fb23d | pbrook | if (ii < i) {
|
1984 | 355fb23d | pbrook | ii++; |
1985 | 355fb23d | pbrook | while (ii < i)
|
1986 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
1987 | 355fb23d | pbrook | } |
1988 | 355fb23d | pbrook | gen_opc_pc[ii] = ctx.pc; |
1989 | 823029f9 | ths | gen_opc_hflags[ii] = ctx.flags; |
1990 | 355fb23d | pbrook | gen_opc_instr_start[ii] = 1;
|
1991 | 2e70f6ef | pbrook | gen_opc_icount[ii] = num_insns; |
1992 | 355fb23d | pbrook | } |
1993 | 2e70f6ef | pbrook | if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) |
1994 | 2e70f6ef | pbrook | gen_io_start(); |
1995 | fdf9b3e8 | bellard | #if 0
|
1996 | fdf9b3e8 | bellard | fprintf(stderr, "Loading opcode at address 0x%08x\n", ctx.pc);
|
1997 | fdf9b3e8 | bellard | fflush(stderr);
|
1998 | fdf9b3e8 | bellard | #endif
|
1999 | fdf9b3e8 | bellard | ctx.opcode = lduw_code(ctx.pc); |
2000 | fdf9b3e8 | bellard | decode_opc(&ctx); |
2001 | 2e70f6ef | pbrook | num_insns++; |
2002 | fdf9b3e8 | bellard | ctx.pc += 2;
|
2003 | fdf9b3e8 | bellard | if ((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) |
2004 | fdf9b3e8 | bellard | break;
|
2005 | fdf9b3e8 | bellard | if (env->singlestep_enabled)
|
2006 | fdf9b3e8 | bellard | break;
|
2007 | 2e70f6ef | pbrook | if (num_insns >= max_insns)
|
2008 | 2e70f6ef | pbrook | break;
|
2009 | 1b530a6d | aurel32 | if (singlestep)
|
2010 | 1b530a6d | aurel32 | break;
|
2011 | fdf9b3e8 | bellard | } |
2012 | 2e70f6ef | pbrook | if (tb->cflags & CF_LAST_IO)
|
2013 | 2e70f6ef | pbrook | gen_io_end(); |
2014 | fdf9b3e8 | bellard | if (env->singlestep_enabled) {
|
2015 | bdbf22e6 | aurel32 | tcg_gen_movi_i32(cpu_pc, ctx.pc); |
2016 | a7812ae4 | pbrook | gen_helper_debug(); |
2017 | 823029f9 | ths | } else {
|
2018 | 823029f9 | ths | switch (ctx.bstate) {
|
2019 | 823029f9 | ths | case BS_STOP:
|
2020 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
2021 | 823029f9 | ths | /* fall through */
|
2022 | 823029f9 | ths | case BS_NONE:
|
2023 | 823029f9 | ths | if (ctx.flags) {
|
2024 | 1000822b | aurel32 | gen_store_flags(ctx.flags | DELAY_SLOT_CLEARME); |
2025 | 823029f9 | ths | } |
2026 | 823029f9 | ths | gen_goto_tb(&ctx, 0, ctx.pc);
|
2027 | 823029f9 | ths | break;
|
2028 | 823029f9 | ths | case BS_EXCP:
|
2029 | 823029f9 | ths | /* gen_op_interrupt_restart(); */
|
2030 | 57fec1fe | bellard | tcg_gen_exit_tb(0);
|
2031 | 823029f9 | ths | break;
|
2032 | 823029f9 | ths | case BS_BRANCH:
|
2033 | 823029f9 | ths | default:
|
2034 | 823029f9 | ths | break;
|
2035 | 823029f9 | ths | } |
2036 | fdf9b3e8 | bellard | } |
2037 | 823029f9 | ths | |
2038 | 2e70f6ef | pbrook | gen_icount_end(tb, num_insns); |
2039 | fdf9b3e8 | bellard | *gen_opc_ptr = INDEX_op_end; |
2040 | 355fb23d | pbrook | if (search_pc) {
|
2041 | 355fb23d | pbrook | i = gen_opc_ptr - gen_opc_buf; |
2042 | 355fb23d | pbrook | ii++; |
2043 | 355fb23d | pbrook | while (ii <= i)
|
2044 | 355fb23d | pbrook | gen_opc_instr_start[ii++] = 0;
|
2045 | 355fb23d | pbrook | } else {
|
2046 | 355fb23d | pbrook | tb->size = ctx.pc - pc_start; |
2047 | 2e70f6ef | pbrook | tb->icount = num_insns; |
2048 | 355fb23d | pbrook | } |
2049 | fdf9b3e8 | bellard | |
2050 | fdf9b3e8 | bellard | #ifdef DEBUG_DISAS
|
2051 | fdf9b3e8 | bellard | #ifdef SH4_DEBUG_DISAS
|
2052 | 93fcfe39 | aliguori | qemu_log_mask(CPU_LOG_TB_IN_ASM, "\n");
|
2053 | fdf9b3e8 | bellard | #endif
|
2054 | 8fec2b8c | aliguori | if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
|
2055 | 93fcfe39 | aliguori | qemu_log("IN:\n"); /* , lookup_symbol(pc_start)); */ |
2056 | 93fcfe39 | aliguori | log_target_disas(pc_start, ctx.pc - pc_start, 0);
|
2057 | 93fcfe39 | aliguori | qemu_log("\n");
|
2058 | fdf9b3e8 | bellard | } |
2059 | fdf9b3e8 | bellard | #endif
|
2060 | fdf9b3e8 | bellard | } |
2061 | fdf9b3e8 | bellard | |
2062 | 2cfc5f17 | ths | void gen_intermediate_code(CPUState * env, struct TranslationBlock *tb) |
2063 | fdf9b3e8 | bellard | { |
2064 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 0);
|
2065 | fdf9b3e8 | bellard | } |
2066 | fdf9b3e8 | bellard | |
2067 | 2cfc5f17 | ths | void gen_intermediate_code_pc(CPUState * env, struct TranslationBlock *tb) |
2068 | fdf9b3e8 | bellard | { |
2069 | 2cfc5f17 | ths | gen_intermediate_code_internal(env, tb, 1);
|
2070 | fdf9b3e8 | bellard | } |
2071 | d2856f1a | aurel32 | |
2072 | d2856f1a | aurel32 | void gen_pc_load(CPUState *env, TranslationBlock *tb,
|
2073 | d2856f1a | aurel32 | unsigned long searched_pc, int pc_pos, void *puc) |
2074 | d2856f1a | aurel32 | { |
2075 | d2856f1a | aurel32 | env->pc = gen_opc_pc[pc_pos]; |
2076 | d2856f1a | aurel32 | env->flags = gen_opc_hflags[pc_pos]; |
2077 | d2856f1a | aurel32 | } |