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Makefile.objs 195 Bytes
arm-semi.c 16 kB
cpu-qom.h 3 kB
cpu.c 25.8 kB
cpu.h 26.3 kB
helper.c 111.7 kB
helper.h 17 kB
iwmmxt_helper.c 24.8 kB
machine.c 7.8 kB
neon_helper.c 52.9 kB
op_addsub.h 1.8 kB
op_helper.c 10.3 kB
translate.c 344.2 kB

Latest revisions

# Date Author Comment
de9b05b8 07/12/2012 01:59 pm Peter Maydell

target-arm: Implement privileged-execute-never (PXN)

Implement the privileged-execute-never (PXN) translation table bit.
It is implementation-defined whether this is implemented, so we give
it its own ARM_FEATURE_ flag. LPAE requires PXN, so add also an
LPAE feature flag and the implication logic, as a placeholder...
918f5dca 07/12/2012 01:59 pm Peter Maydell

target-arm: Extend feature flags to 64 bits

Extend feature flags to 64 bits, as we've just run out of space
in the 32 bit integer we were using for them.

Signed-off-by: Peter Maydell <>
7ac681cf 07/12/2012 01:59 pm Peter Maydell

target-arm: Add AMAIR0, AMAIR1 LPAE cp15 registers

Add implementations of the AMAIR0 and AMAIR1 LPAE
Auxiliary Memory Attribute Indirection Registers.
These are implementation defined and we choose to
implement them as RAZ/WI, matching the Cortex-A7
and Cortex-A15....
f9fc619a 07/12/2012 01:59 pm Peter Maydell

target-arm: Add 64 bit variants of DBGDRAR and DBGDSAR for LPAE

LPAE extends the DBGDRAR and DBGDSAR debug registers to 64 bits; we
only implement these as dummy RAZ versions; provide dummies for
the 64 bit accesses as well.

Signed-off-by: Peter Maydell <>
891a2fe7 07/12/2012 01:59 pm Peter Maydell

target-arm: Add 64 bit PAR, TTBR0, TTBR1 for LPAE

Under LPAE, the cp15 registers PAR, TTBR0 and TTBR1 are extended
to 64 bits, with a 64 bit (MRRC/MCRR) access path to read the
full width of the register. Add the state fields for the top
half and the 64 bit access path. Actual use of the top half of...
77a71dd1 07/12/2012 01:59 pm Peter Maydell

target-arm: Use target_phys_addr_t in get_phys_addr()

In the implementation of get_phys_addr(), consistently use
target_phys_addr_t to hold the physical address rather than
uint32_t.

Signed-off-by: Peter Maydell <>
702a9357 07/12/2012 01:59 pm Peter Maydell

target-arm: Implement long-descriptor PAR format

Implement the different format of the PAR when long descriptor
translation tables are in use. Note that we assume that
get_phys_addr() returns a long-descriptor format DFSR value on
failure if long descriptors are in use; this added subtlety tips...
e42c4db3 07/12/2012 01:59 pm Peter Maydell

target-arm: Implement TTBCR changes for LPAE

Implement the changes to the TTBCR register required for LPAE: * many fewer bits should be RAZ/WI * since TTBCR changes can result in a change of ASID, we must
flush the TLB on writes to it

Signed-off-by: Peter Maydell <>
3dde962f 07/12/2012 01:59 pm Peter Maydell

target-arm: Add support for long format translation table walks

Implement the actual table walk code for LPAE's long format
translation tables.

Signed-off-by: Peter Maydell <>
3cc0cd61 07/12/2012 01:59 pm Peter Maydell

ARM: Make target_phys_addr_t 64 bits and physaddrs 40 bits

Make target_phys_addr_t 64 bits for ARM targets, and set
TARGET_PHYS_ADDR_SPACE_BITS to 40. This should have no effect for ARM
boards where physical addresses really are 32 bits (except perhaps a...

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