root / hw / alpha_pci.c @ 0ef654e3
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1 | 80bb2ff7 | Richard Henderson | /*
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2 | 80bb2ff7 | Richard Henderson | * QEMU Alpha PCI support functions.
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3 | 80bb2ff7 | Richard Henderson | *
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4 | 80bb2ff7 | Richard Henderson | * Some of this isn't very Alpha specific at all.
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5 | 80bb2ff7 | Richard Henderson | *
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6 | 80bb2ff7 | Richard Henderson | * ??? Sparse memory access not implemented.
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7 | 80bb2ff7 | Richard Henderson | */
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8 | 80bb2ff7 | Richard Henderson | |
9 | 80bb2ff7 | Richard Henderson | #include "config.h" |
10 | 80bb2ff7 | Richard Henderson | #include "alpha_sys.h" |
11 | 80bb2ff7 | Richard Henderson | #include "qemu-log.h" |
12 | 80bb2ff7 | Richard Henderson | #include "sysemu.h" |
13 | 80bb2ff7 | Richard Henderson | #include "vmware_vga.h" |
14 | 80bb2ff7 | Richard Henderson | |
15 | 80bb2ff7 | Richard Henderson | |
16 | 80bb2ff7 | Richard Henderson | /* PCI IO reads/writes, to byte-word addressable memory. */
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17 | 80bb2ff7 | Richard Henderson | /* ??? Doesn't handle multiple PCI busses. */
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18 | 80bb2ff7 | Richard Henderson | |
19 | 80bb2ff7 | Richard Henderson | static uint64_t bw_io_read(void *opaque, target_phys_addr_t addr, unsigned size) |
20 | 80bb2ff7 | Richard Henderson | { |
21 | 80bb2ff7 | Richard Henderson | switch (size) {
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22 | 80bb2ff7 | Richard Henderson | case 1: |
23 | 80bb2ff7 | Richard Henderson | return cpu_inb(addr);
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24 | 80bb2ff7 | Richard Henderson | case 2: |
25 | 80bb2ff7 | Richard Henderson | return cpu_inw(addr);
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26 | 80bb2ff7 | Richard Henderson | case 4: |
27 | 80bb2ff7 | Richard Henderson | return cpu_inl(addr);
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28 | 80bb2ff7 | Richard Henderson | } |
29 | 80bb2ff7 | Richard Henderson | abort(); |
30 | 80bb2ff7 | Richard Henderson | } |
31 | 80bb2ff7 | Richard Henderson | |
32 | 80bb2ff7 | Richard Henderson | static void bw_io_write(void *opaque, target_phys_addr_t addr, |
33 | 80bb2ff7 | Richard Henderson | uint64_t val, unsigned size)
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34 | 80bb2ff7 | Richard Henderson | { |
35 | 80bb2ff7 | Richard Henderson | switch (size) {
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36 | 80bb2ff7 | Richard Henderson | case 1: |
37 | 80bb2ff7 | Richard Henderson | cpu_outb(addr, val); |
38 | 80bb2ff7 | Richard Henderson | break;
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39 | 80bb2ff7 | Richard Henderson | case 2: |
40 | 80bb2ff7 | Richard Henderson | cpu_outw(addr, val); |
41 | 80bb2ff7 | Richard Henderson | break;
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42 | 80bb2ff7 | Richard Henderson | case 4: |
43 | 80bb2ff7 | Richard Henderson | cpu_outl(addr, val); |
44 | 80bb2ff7 | Richard Henderson | break;
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45 | 80bb2ff7 | Richard Henderson | default:
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46 | 80bb2ff7 | Richard Henderson | abort(); |
47 | 80bb2ff7 | Richard Henderson | } |
48 | 80bb2ff7 | Richard Henderson | } |
49 | 80bb2ff7 | Richard Henderson | |
50 | 80bb2ff7 | Richard Henderson | const MemoryRegionOps alpha_pci_bw_io_ops = {
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51 | 80bb2ff7 | Richard Henderson | .read = bw_io_read, |
52 | 80bb2ff7 | Richard Henderson | .write = bw_io_write, |
53 | 80bb2ff7 | Richard Henderson | .endianness = DEVICE_LITTLE_ENDIAN, |
54 | 80bb2ff7 | Richard Henderson | .impl = { |
55 | 80bb2ff7 | Richard Henderson | .min_access_size = 1,
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56 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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57 | 80bb2ff7 | Richard Henderson | }, |
58 | 80bb2ff7 | Richard Henderson | }; |
59 | 80bb2ff7 | Richard Henderson | |
60 | 80bb2ff7 | Richard Henderson | /* PCI config space reads/writes, to byte-word addressable memory. */
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61 | 80bb2ff7 | Richard Henderson | static uint64_t bw_conf1_read(void *opaque, target_phys_addr_t addr, |
62 | 80bb2ff7 | Richard Henderson | unsigned size)
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63 | 80bb2ff7 | Richard Henderson | { |
64 | 80bb2ff7 | Richard Henderson | PCIBus *b = opaque; |
65 | 80bb2ff7 | Richard Henderson | return pci_data_read(b, addr, size);
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66 | 80bb2ff7 | Richard Henderson | } |
67 | 80bb2ff7 | Richard Henderson | |
68 | 80bb2ff7 | Richard Henderson | static void bw_conf1_write(void *opaque, target_phys_addr_t addr, |
69 | 80bb2ff7 | Richard Henderson | uint64_t val, unsigned size)
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70 | 80bb2ff7 | Richard Henderson | { |
71 | 80bb2ff7 | Richard Henderson | PCIBus *b = opaque; |
72 | 80bb2ff7 | Richard Henderson | pci_data_write(b, addr, val, size); |
73 | 80bb2ff7 | Richard Henderson | } |
74 | 80bb2ff7 | Richard Henderson | |
75 | 80bb2ff7 | Richard Henderson | const MemoryRegionOps alpha_pci_conf1_ops = {
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76 | 80bb2ff7 | Richard Henderson | .read = bw_conf1_read, |
77 | 80bb2ff7 | Richard Henderson | .write = bw_conf1_write, |
78 | 80bb2ff7 | Richard Henderson | .endianness = DEVICE_LITTLE_ENDIAN, |
79 | 80bb2ff7 | Richard Henderson | .impl = { |
80 | 80bb2ff7 | Richard Henderson | .min_access_size = 1,
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81 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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82 | 80bb2ff7 | Richard Henderson | }, |
83 | 80bb2ff7 | Richard Henderson | }; |
84 | 80bb2ff7 | Richard Henderson | |
85 | 80bb2ff7 | Richard Henderson | /* PCI/EISA Interrupt Acknowledge Cycle. */
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86 | 80bb2ff7 | Richard Henderson | |
87 | 80bb2ff7 | Richard Henderson | static uint64_t iack_read(void *opaque, target_phys_addr_t addr, unsigned size) |
88 | 80bb2ff7 | Richard Henderson | { |
89 | 80bb2ff7 | Richard Henderson | return pic_read_irq(isa_pic);
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90 | 80bb2ff7 | Richard Henderson | } |
91 | 80bb2ff7 | Richard Henderson | |
92 | 80bb2ff7 | Richard Henderson | static void special_write(void *opaque, target_phys_addr_t addr, |
93 | 80bb2ff7 | Richard Henderson | uint64_t val, unsigned size)
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94 | 80bb2ff7 | Richard Henderson | { |
95 | 80bb2ff7 | Richard Henderson | qemu_log("pci: special write cycle");
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96 | 80bb2ff7 | Richard Henderson | } |
97 | 80bb2ff7 | Richard Henderson | |
98 | 80bb2ff7 | Richard Henderson | const MemoryRegionOps alpha_pci_iack_ops = {
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99 | 80bb2ff7 | Richard Henderson | .read = iack_read, |
100 | 80bb2ff7 | Richard Henderson | .write = special_write, |
101 | 80bb2ff7 | Richard Henderson | .endianness = DEVICE_LITTLE_ENDIAN, |
102 | 80bb2ff7 | Richard Henderson | .valid = { |
103 | 80bb2ff7 | Richard Henderson | .min_access_size = 4,
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104 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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105 | 80bb2ff7 | Richard Henderson | }, |
106 | 80bb2ff7 | Richard Henderson | .impl = { |
107 | 80bb2ff7 | Richard Henderson | .min_access_size = 4,
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108 | 80bb2ff7 | Richard Henderson | .max_access_size = 4,
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109 | 80bb2ff7 | Richard Henderson | }, |
110 | 80bb2ff7 | Richard Henderson | }; |
111 | 80bb2ff7 | Richard Henderson | |
112 | 80bb2ff7 | Richard Henderson | void alpha_pci_vga_setup(PCIBus *pci_bus)
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113 | 80bb2ff7 | Richard Henderson | { |
114 | 80bb2ff7 | Richard Henderson | switch (vga_interface_type) {
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115 | 80bb2ff7 | Richard Henderson | #ifdef CONFIG_SPICE
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116 | 80bb2ff7 | Richard Henderson | case VGA_QXL:
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117 | 80bb2ff7 | Richard Henderson | pci_create_simple(pci_bus, -1, "qxl-vga"); |
118 | 80bb2ff7 | Richard Henderson | return;
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119 | 80bb2ff7 | Richard Henderson | #endif
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120 | 80bb2ff7 | Richard Henderson | case VGA_CIRRUS:
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121 | 80bb2ff7 | Richard Henderson | pci_cirrus_vga_init(pci_bus); |
122 | 80bb2ff7 | Richard Henderson | return;
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123 | 80bb2ff7 | Richard Henderson | case VGA_VMWARE:
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124 | a369da5f | Blue Swirl | pci_vmsvga_init(pci_bus); |
125 | a369da5f | Blue Swirl | return;
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126 | 80bb2ff7 | Richard Henderson | } |
127 | 80bb2ff7 | Richard Henderson | /* If VGA is enabled at all, and one of the above didn't work, then
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128 | 80bb2ff7 | Richard Henderson | fallback to Standard VGA. */
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129 | 80bb2ff7 | Richard Henderson | if (vga_interface_type != VGA_NONE) {
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130 | 80bb2ff7 | Richard Henderson | pci_vga_init(pci_bus); |
131 | 80bb2ff7 | Richard Henderson | } |
132 | 80bb2ff7 | Richard Henderson | } |