root / hw / pxa2xx_lcd.c @ 0ef654e3
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1 | a171fe39 | balrog | /*
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2 | a171fe39 | balrog | * Intel XScale PXA255/270 LCDC emulation.
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3 | a171fe39 | balrog | *
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4 | a171fe39 | balrog | * Copyright (c) 2006 Openedhand Ltd.
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5 | a171fe39 | balrog | * Written by Andrzej Zaborowski <balrog@zabor.org>
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6 | a171fe39 | balrog | *
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7 | a171fe39 | balrog | * This code is licensed under the GPLv2.
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8 | 6b620ca3 | Paolo Bonzini | *
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9 | 6b620ca3 | Paolo Bonzini | * Contributions after 2012-01-13 are licensed under the terms of the
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10 | 6b620ca3 | Paolo Bonzini | * GNU GPL, version 2 or (at your option) any later version.
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11 | a171fe39 | balrog | */
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12 | a171fe39 | balrog | |
13 | 87ecb68b | pbrook | #include "hw.h" |
14 | 87ecb68b | pbrook | #include "console.h" |
15 | 87ecb68b | pbrook | #include "pxa.h" |
16 | e27f01ef | balrog | #include "pixel_ops.h" |
17 | 87ecb68b | pbrook | /* FIXME: For graphic_rotate. Should probably be done in common code. */
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18 | 87ecb68b | pbrook | #include "sysemu.h" |
19 | 714fa308 | pbrook | #include "framebuffer.h" |
20 | a171fe39 | balrog | |
21 | 2b7251e0 | Juan Quintela | struct DMAChannel {
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22 | 2b7251e0 | Juan Quintela | target_phys_addr_t branch; |
23 | 46995409 | Juan Quintela | uint8_t up; |
24 | 2b7251e0 | Juan Quintela | uint8_t palette[1024];
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25 | 2b7251e0 | Juan Quintela | uint8_t pbuffer[1024];
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26 | 2b7251e0 | Juan Quintela | void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
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27 | 2b7251e0 | Juan Quintela | int *miny, int *maxy); |
28 | 2b7251e0 | Juan Quintela | |
29 | 2b7251e0 | Juan Quintela | target_phys_addr_t descriptor; |
30 | 2b7251e0 | Juan Quintela | target_phys_addr_t source; |
31 | 2b7251e0 | Juan Quintela | uint32_t id; |
32 | 2b7251e0 | Juan Quintela | uint32_t command; |
33 | 2b7251e0 | Juan Quintela | }; |
34 | 2b7251e0 | Juan Quintela | |
35 | bc24a225 | Paul Brook | struct PXA2xxLCDState {
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36 | 75c9d6c2 | Avi Kivity | MemoryRegion *sysmem; |
37 | 5a6fdd91 | Benoît Canet | MemoryRegion iomem; |
38 | a171fe39 | balrog | qemu_irq irq; |
39 | a171fe39 | balrog | int irqlevel;
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40 | a171fe39 | balrog | |
41 | a171fe39 | balrog | int invalidated;
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42 | a171fe39 | balrog | DisplayState *ds; |
43 | a171fe39 | balrog | drawfn *line_fn[2];
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44 | a171fe39 | balrog | int dest_width;
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45 | a171fe39 | balrog | int xres, yres;
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46 | a171fe39 | balrog | int pal_for;
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47 | a171fe39 | balrog | int transp;
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48 | a171fe39 | balrog | enum {
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49 | a171fe39 | balrog | pxa_lcdc_2bpp = 1,
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50 | a171fe39 | balrog | pxa_lcdc_4bpp = 2,
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51 | a171fe39 | balrog | pxa_lcdc_8bpp = 3,
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52 | a171fe39 | balrog | pxa_lcdc_16bpp = 4,
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53 | a171fe39 | balrog | pxa_lcdc_18bpp = 5,
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54 | a171fe39 | balrog | pxa_lcdc_18pbpp = 6,
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55 | a171fe39 | balrog | pxa_lcdc_19bpp = 7,
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56 | a171fe39 | balrog | pxa_lcdc_19pbpp = 8,
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57 | a171fe39 | balrog | pxa_lcdc_24bpp = 9,
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58 | a171fe39 | balrog | pxa_lcdc_25bpp = 10,
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59 | a171fe39 | balrog | } bpp; |
60 | a171fe39 | balrog | |
61 | a171fe39 | balrog | uint32_t control[6];
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62 | a171fe39 | balrog | uint32_t status[2];
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63 | a171fe39 | balrog | uint32_t ovl1c[2];
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64 | a171fe39 | balrog | uint32_t ovl2c[2];
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65 | a171fe39 | balrog | uint32_t ccr; |
66 | a171fe39 | balrog | uint32_t cmdcr; |
67 | a171fe39 | balrog | uint32_t trgbr; |
68 | a171fe39 | balrog | uint32_t tcr; |
69 | a171fe39 | balrog | uint32_t liidr; |
70 | a171fe39 | balrog | uint8_t bscntr; |
71 | a171fe39 | balrog | |
72 | 2b7251e0 | Juan Quintela | struct DMAChannel dma_ch[7]; |
73 | a171fe39 | balrog | |
74 | 38641a52 | balrog | qemu_irq vsync_cb; |
75 | a171fe39 | balrog | int orientation;
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76 | a171fe39 | balrog | }; |
77 | a171fe39 | balrog | |
78 | 541dc0d4 | Stefan Weil | typedef struct QEMU_PACKED { |
79 | a171fe39 | balrog | uint32_t fdaddr; |
80 | a171fe39 | balrog | uint32_t fsaddr; |
81 | a171fe39 | balrog | uint32_t fidr; |
82 | a171fe39 | balrog | uint32_t ldcmd; |
83 | bc24a225 | Paul Brook | } PXAFrameDescriptor; |
84 | a171fe39 | balrog | |
85 | a171fe39 | balrog | #define LCCR0 0x000 /* LCD Controller Control register 0 */ |
86 | a171fe39 | balrog | #define LCCR1 0x004 /* LCD Controller Control register 1 */ |
87 | a171fe39 | balrog | #define LCCR2 0x008 /* LCD Controller Control register 2 */ |
88 | a171fe39 | balrog | #define LCCR3 0x00c /* LCD Controller Control register 3 */ |
89 | a171fe39 | balrog | #define LCCR4 0x010 /* LCD Controller Control register 4 */ |
90 | a171fe39 | balrog | #define LCCR5 0x014 /* LCD Controller Control register 5 */ |
91 | a171fe39 | balrog | |
92 | a171fe39 | balrog | #define FBR0 0x020 /* DMA Channel 0 Frame Branch register */ |
93 | a171fe39 | balrog | #define FBR1 0x024 /* DMA Channel 1 Frame Branch register */ |
94 | a171fe39 | balrog | #define FBR2 0x028 /* DMA Channel 2 Frame Branch register */ |
95 | a171fe39 | balrog | #define FBR3 0x02c /* DMA Channel 3 Frame Branch register */ |
96 | a171fe39 | balrog | #define FBR4 0x030 /* DMA Channel 4 Frame Branch register */ |
97 | a171fe39 | balrog | #define FBR5 0x110 /* DMA Channel 5 Frame Branch register */ |
98 | a171fe39 | balrog | #define FBR6 0x114 /* DMA Channel 6 Frame Branch register */ |
99 | a171fe39 | balrog | |
100 | a171fe39 | balrog | #define LCSR1 0x034 /* LCD Controller Status register 1 */ |
101 | a171fe39 | balrog | #define LCSR0 0x038 /* LCD Controller Status register 0 */ |
102 | a171fe39 | balrog | #define LIIDR 0x03c /* LCD Controller Interrupt ID register */ |
103 | a171fe39 | balrog | |
104 | a171fe39 | balrog | #define TRGBR 0x040 /* TMED RGB Seed register */ |
105 | a171fe39 | balrog | #define TCR 0x044 /* TMED Control register */ |
106 | a171fe39 | balrog | |
107 | a171fe39 | balrog | #define OVL1C1 0x050 /* Overlay 1 Control register 1 */ |
108 | a171fe39 | balrog | #define OVL1C2 0x060 /* Overlay 1 Control register 2 */ |
109 | a171fe39 | balrog | #define OVL2C1 0x070 /* Overlay 2 Control register 1 */ |
110 | a171fe39 | balrog | #define OVL2C2 0x080 /* Overlay 2 Control register 2 */ |
111 | a171fe39 | balrog | #define CCR 0x090 /* Cursor Control register */ |
112 | a171fe39 | balrog | |
113 | a171fe39 | balrog | #define CMDCR 0x100 /* Command Control register */ |
114 | a171fe39 | balrog | #define PRSR 0x104 /* Panel Read Status register */ |
115 | a171fe39 | balrog | |
116 | a171fe39 | balrog | #define PXA_LCDDMA_CHANS 7 |
117 | a171fe39 | balrog | #define DMA_FDADR 0x00 /* Frame Descriptor Address register */ |
118 | a171fe39 | balrog | #define DMA_FSADR 0x04 /* Frame Source Address register */ |
119 | a171fe39 | balrog | #define DMA_FIDR 0x08 /* Frame ID register */ |
120 | a171fe39 | balrog | #define DMA_LDCMD 0x0c /* Command register */ |
121 | a171fe39 | balrog | |
122 | a171fe39 | balrog | /* LCD Buffer Strength Control register */
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123 | a171fe39 | balrog | #define BSCNTR 0x04000054 |
124 | a171fe39 | balrog | |
125 | a171fe39 | balrog | /* Bitfield masks */
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126 | a171fe39 | balrog | #define LCCR0_ENB (1 << 0) |
127 | a171fe39 | balrog | #define LCCR0_CMS (1 << 1) |
128 | a171fe39 | balrog | #define LCCR0_SDS (1 << 2) |
129 | a171fe39 | balrog | #define LCCR0_LDM (1 << 3) |
130 | a171fe39 | balrog | #define LCCR0_SOFM0 (1 << 4) |
131 | a171fe39 | balrog | #define LCCR0_IUM (1 << 5) |
132 | a171fe39 | balrog | #define LCCR0_EOFM0 (1 << 6) |
133 | a171fe39 | balrog | #define LCCR0_PAS (1 << 7) |
134 | a171fe39 | balrog | #define LCCR0_DPD (1 << 9) |
135 | a171fe39 | balrog | #define LCCR0_DIS (1 << 10) |
136 | a171fe39 | balrog | #define LCCR0_QDM (1 << 11) |
137 | a171fe39 | balrog | #define LCCR0_PDD (0xff << 12) |
138 | a171fe39 | balrog | #define LCCR0_BSM0 (1 << 20) |
139 | a171fe39 | balrog | #define LCCR0_OUM (1 << 21) |
140 | a171fe39 | balrog | #define LCCR0_LCDT (1 << 22) |
141 | a171fe39 | balrog | #define LCCR0_RDSTM (1 << 23) |
142 | a171fe39 | balrog | #define LCCR0_CMDIM (1 << 24) |
143 | a171fe39 | balrog | #define LCCR0_OUC (1 << 25) |
144 | a171fe39 | balrog | #define LCCR0_LDDALT (1 << 26) |
145 | a171fe39 | balrog | #define LCCR1_PPL(x) ((x) & 0x3ff) |
146 | a171fe39 | balrog | #define LCCR2_LPP(x) ((x) & 0x3ff) |
147 | a171fe39 | balrog | #define LCCR3_API (15 << 16) |
148 | a171fe39 | balrog | #define LCCR3_BPP(x) ((((x) >> 24) & 7) | (((x) >> 26) & 8)) |
149 | a171fe39 | balrog | #define LCCR3_PDFOR(x) (((x) >> 30) & 3) |
150 | a171fe39 | balrog | #define LCCR4_K1(x) (((x) >> 0) & 7) |
151 | a171fe39 | balrog | #define LCCR4_K2(x) (((x) >> 3) & 7) |
152 | a171fe39 | balrog | #define LCCR4_K3(x) (((x) >> 6) & 7) |
153 | a171fe39 | balrog | #define LCCR4_PALFOR(x) (((x) >> 15) & 3) |
154 | a171fe39 | balrog | #define LCCR5_SOFM(ch) (1 << (ch - 1)) |
155 | a171fe39 | balrog | #define LCCR5_EOFM(ch) (1 << (ch + 7)) |
156 | a171fe39 | balrog | #define LCCR5_BSM(ch) (1 << (ch + 15)) |
157 | a171fe39 | balrog | #define LCCR5_IUM(ch) (1 << (ch + 23)) |
158 | a171fe39 | balrog | #define OVLC1_EN (1 << 31) |
159 | a171fe39 | balrog | #define CCR_CEN (1 << 31) |
160 | a171fe39 | balrog | #define FBR_BRA (1 << 0) |
161 | a171fe39 | balrog | #define FBR_BINT (1 << 1) |
162 | a171fe39 | balrog | #define FBR_SRCADDR (0xfffffff << 4) |
163 | a171fe39 | balrog | #define LCSR0_LDD (1 << 0) |
164 | a171fe39 | balrog | #define LCSR0_SOF0 (1 << 1) |
165 | a171fe39 | balrog | #define LCSR0_BER (1 << 2) |
166 | a171fe39 | balrog | #define LCSR0_ABC (1 << 3) |
167 | a171fe39 | balrog | #define LCSR0_IU0 (1 << 4) |
168 | a171fe39 | balrog | #define LCSR0_IU1 (1 << 5) |
169 | a171fe39 | balrog | #define LCSR0_OU (1 << 6) |
170 | a171fe39 | balrog | #define LCSR0_QD (1 << 7) |
171 | a171fe39 | balrog | #define LCSR0_EOF0 (1 << 8) |
172 | a171fe39 | balrog | #define LCSR0_BS0 (1 << 9) |
173 | a171fe39 | balrog | #define LCSR0_SINT (1 << 10) |
174 | a171fe39 | balrog | #define LCSR0_RDST (1 << 11) |
175 | a171fe39 | balrog | #define LCSR0_CMDINT (1 << 12) |
176 | a171fe39 | balrog | #define LCSR0_BERCH(x) (((x) & 7) << 28) |
177 | a171fe39 | balrog | #define LCSR1_SOF(ch) (1 << (ch - 1)) |
178 | a171fe39 | balrog | #define LCSR1_EOF(ch) (1 << (ch + 7)) |
179 | a171fe39 | balrog | #define LCSR1_BS(ch) (1 << (ch + 15)) |
180 | a171fe39 | balrog | #define LCSR1_IU(ch) (1 << (ch + 23)) |
181 | a171fe39 | balrog | #define LDCMD_LENGTH(x) ((x) & 0x001ffffc) |
182 | a171fe39 | balrog | #define LDCMD_EOFINT (1 << 21) |
183 | a171fe39 | balrog | #define LDCMD_SOFINT (1 << 22) |
184 | a171fe39 | balrog | #define LDCMD_PAL (1 << 26) |
185 | a171fe39 | balrog | |
186 | a171fe39 | balrog | /* Route internal interrupt lines to the global IC */
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187 | bc24a225 | Paul Brook | static void pxa2xx_lcdc_int_update(PXA2xxLCDState *s) |
188 | a171fe39 | balrog | { |
189 | a171fe39 | balrog | int level = 0; |
190 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_LDD) && !(s->control[0] & LCCR0_LDM); |
191 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_SOF0) && !(s->control[0] & LCCR0_SOFM0); |
192 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_IU0) && !(s->control[0] & LCCR0_IUM); |
193 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_IU1) && !(s->control[5] & LCCR5_IUM(1)); |
194 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_OU) && !(s->control[0] & LCCR0_OUM); |
195 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_QD) && !(s->control[0] & LCCR0_QDM); |
196 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_EOF0) && !(s->control[0] & LCCR0_EOFM0); |
197 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_BS0) && !(s->control[0] & LCCR0_BSM0); |
198 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_RDST) && !(s->control[0] & LCCR0_RDSTM); |
199 | a171fe39 | balrog | level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM); |
200 | a171fe39 | balrog | level |= (s->status[1] & ~s->control[5]); |
201 | a171fe39 | balrog | |
202 | a171fe39 | balrog | qemu_set_irq(s->irq, !!level); |
203 | a171fe39 | balrog | s->irqlevel = level; |
204 | a171fe39 | balrog | } |
205 | a171fe39 | balrog | |
206 | a171fe39 | balrog | /* Set Branch Status interrupt high and poke associated registers */
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207 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_bs_set(PXA2xxLCDState *s, int ch) |
208 | a171fe39 | balrog | { |
209 | a171fe39 | balrog | int unmasked;
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210 | a171fe39 | balrog | if (ch == 0) { |
211 | a171fe39 | balrog | s->status[0] |= LCSR0_BS0;
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212 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_BSM0);
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213 | a171fe39 | balrog | } else {
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214 | a171fe39 | balrog | s->status[1] |= LCSR1_BS(ch);
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215 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_BSM(ch));
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216 | a171fe39 | balrog | } |
217 | a171fe39 | balrog | |
218 | a171fe39 | balrog | if (unmasked) {
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219 | a171fe39 | balrog | if (s->irqlevel)
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220 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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221 | a171fe39 | balrog | else
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222 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
223 | a171fe39 | balrog | } |
224 | a171fe39 | balrog | } |
225 | a171fe39 | balrog | |
226 | a171fe39 | balrog | /* Set Start Of Frame Status interrupt high and poke associated registers */
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227 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_sof_set(PXA2xxLCDState *s, int ch) |
228 | a171fe39 | balrog | { |
229 | a171fe39 | balrog | int unmasked;
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230 | a171fe39 | balrog | if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
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231 | a171fe39 | balrog | return;
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232 | a171fe39 | balrog | |
233 | a171fe39 | balrog | if (ch == 0) { |
234 | a171fe39 | balrog | s->status[0] |= LCSR0_SOF0;
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235 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_SOFM0);
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236 | a171fe39 | balrog | } else {
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237 | a171fe39 | balrog | s->status[1] |= LCSR1_SOF(ch);
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238 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_SOFM(ch));
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239 | a171fe39 | balrog | } |
240 | a171fe39 | balrog | |
241 | a171fe39 | balrog | if (unmasked) {
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242 | a171fe39 | balrog | if (s->irqlevel)
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243 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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244 | a171fe39 | balrog | else
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245 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
246 | a171fe39 | balrog | } |
247 | a171fe39 | balrog | } |
248 | a171fe39 | balrog | |
249 | a171fe39 | balrog | /* Set End Of Frame Status interrupt high and poke associated registers */
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250 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_eof_set(PXA2xxLCDState *s, int ch) |
251 | a171fe39 | balrog | { |
252 | a171fe39 | balrog | int unmasked;
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253 | a171fe39 | balrog | if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
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254 | a171fe39 | balrog | return;
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255 | a171fe39 | balrog | |
256 | a171fe39 | balrog | if (ch == 0) { |
257 | a171fe39 | balrog | s->status[0] |= LCSR0_EOF0;
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258 | a171fe39 | balrog | unmasked = !(s->control[0] & LCCR0_EOFM0);
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259 | a171fe39 | balrog | } else {
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260 | a171fe39 | balrog | s->status[1] |= LCSR1_EOF(ch);
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261 | a171fe39 | balrog | unmasked = !(s->control[5] & LCCR5_EOFM(ch));
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262 | a171fe39 | balrog | } |
263 | a171fe39 | balrog | |
264 | a171fe39 | balrog | if (unmasked) {
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265 | a171fe39 | balrog | if (s->irqlevel)
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266 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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267 | a171fe39 | balrog | else
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268 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
269 | a171fe39 | balrog | } |
270 | a171fe39 | balrog | } |
271 | a171fe39 | balrog | |
272 | a171fe39 | balrog | /* Set Bus Error Status interrupt high and poke associated registers */
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273 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_ber_set(PXA2xxLCDState *s, int ch) |
274 | a171fe39 | balrog | { |
275 | a171fe39 | balrog | s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
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276 | a171fe39 | balrog | if (s->irqlevel)
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277 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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278 | a171fe39 | balrog | else
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279 | a171fe39 | balrog | s->liidr = s->dma_ch[ch].id; |
280 | a171fe39 | balrog | } |
281 | a171fe39 | balrog | |
282 | a171fe39 | balrog | /* Set Read Status interrupt high and poke associated registers */
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283 | bc24a225 | Paul Brook | static inline void pxa2xx_dma_rdst_set(PXA2xxLCDState *s) |
284 | a171fe39 | balrog | { |
285 | a171fe39 | balrog | s->status[0] |= LCSR0_RDST;
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286 | a171fe39 | balrog | if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM)) |
287 | a171fe39 | balrog | s->status[0] |= LCSR0_SINT;
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288 | a171fe39 | balrog | } |
289 | a171fe39 | balrog | |
290 | a171fe39 | balrog | /* Load new Frame Descriptors from DMA */
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291 | bc24a225 | Paul Brook | static void pxa2xx_descriptor_load(PXA2xxLCDState *s) |
292 | a171fe39 | balrog | { |
293 | bc24a225 | Paul Brook | PXAFrameDescriptor desc; |
294 | c227f099 | Anthony Liguori | target_phys_addr_t descptr; |
295 | a171fe39 | balrog | int i;
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296 | a171fe39 | balrog | |
297 | a171fe39 | balrog | for (i = 0; i < PXA_LCDDMA_CHANS; i ++) { |
298 | a171fe39 | balrog | s->dma_ch[i].source = 0;
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299 | a171fe39 | balrog | |
300 | a171fe39 | balrog | if (!s->dma_ch[i].up)
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301 | a171fe39 | balrog | continue;
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302 | a171fe39 | balrog | |
303 | a171fe39 | balrog | if (s->dma_ch[i].branch & FBR_BRA) {
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304 | a171fe39 | balrog | descptr = s->dma_ch[i].branch & FBR_SRCADDR; |
305 | a171fe39 | balrog | if (s->dma_ch[i].branch & FBR_BINT)
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306 | a171fe39 | balrog | pxa2xx_dma_bs_set(s, i); |
307 | a171fe39 | balrog | s->dma_ch[i].branch &= ~FBR_BRA; |
308 | a171fe39 | balrog | } else
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309 | a171fe39 | balrog | descptr = s->dma_ch[i].descriptor; |
310 | a171fe39 | balrog | |
311 | d95b2f8d | balrog | if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
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312 | b0457b69 | pbrook | sizeof(desc) <= PXA2XX_SDRAM_BASE + ram_size))
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313 | a171fe39 | balrog | continue;
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314 | a171fe39 | balrog | |
315 | d7585251 | pbrook | cpu_physical_memory_read(descptr, (void *)&desc, sizeof(desc)); |
316 | d7585251 | pbrook | s->dma_ch[i].descriptor = tswap32(desc.fdaddr); |
317 | d7585251 | pbrook | s->dma_ch[i].source = tswap32(desc.fsaddr); |
318 | d7585251 | pbrook | s->dma_ch[i].id = tswap32(desc.fidr); |
319 | d7585251 | pbrook | s->dma_ch[i].command = tswap32(desc.ldcmd); |
320 | a171fe39 | balrog | } |
321 | a171fe39 | balrog | } |
322 | a171fe39 | balrog | |
323 | 5a6fdd91 | Benoît Canet | static uint64_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset, |
324 | 5a6fdd91 | Benoît Canet | unsigned size)
|
325 | a171fe39 | balrog | { |
326 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
327 | a171fe39 | balrog | int ch;
|
328 | a171fe39 | balrog | |
329 | a171fe39 | balrog | switch (offset) {
|
330 | a171fe39 | balrog | case LCCR0:
|
331 | a171fe39 | balrog | return s->control[0]; |
332 | a171fe39 | balrog | case LCCR1:
|
333 | a171fe39 | balrog | return s->control[1]; |
334 | a171fe39 | balrog | case LCCR2:
|
335 | a171fe39 | balrog | return s->control[2]; |
336 | a171fe39 | balrog | case LCCR3:
|
337 | a171fe39 | balrog | return s->control[3]; |
338 | a171fe39 | balrog | case LCCR4:
|
339 | a171fe39 | balrog | return s->control[4]; |
340 | a171fe39 | balrog | case LCCR5:
|
341 | a171fe39 | balrog | return s->control[5]; |
342 | a171fe39 | balrog | |
343 | a171fe39 | balrog | case OVL1C1:
|
344 | a171fe39 | balrog | return s->ovl1c[0]; |
345 | a171fe39 | balrog | case OVL1C2:
|
346 | a171fe39 | balrog | return s->ovl1c[1]; |
347 | a171fe39 | balrog | case OVL2C1:
|
348 | a171fe39 | balrog | return s->ovl2c[0]; |
349 | a171fe39 | balrog | case OVL2C2:
|
350 | a171fe39 | balrog | return s->ovl2c[1]; |
351 | a171fe39 | balrog | |
352 | a171fe39 | balrog | case CCR:
|
353 | a171fe39 | balrog | return s->ccr;
|
354 | a171fe39 | balrog | |
355 | a171fe39 | balrog | case CMDCR:
|
356 | a171fe39 | balrog | return s->cmdcr;
|
357 | a171fe39 | balrog | |
358 | a171fe39 | balrog | case TRGBR:
|
359 | a171fe39 | balrog | return s->trgbr;
|
360 | a171fe39 | balrog | case TCR:
|
361 | a171fe39 | balrog | return s->tcr;
|
362 | a171fe39 | balrog | |
363 | a171fe39 | balrog | case 0x200 ... 0x1000: /* DMA per-channel registers */ |
364 | a171fe39 | balrog | ch = (offset - 0x200) >> 4; |
365 | a171fe39 | balrog | if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
366 | a171fe39 | balrog | goto fail;
|
367 | a171fe39 | balrog | |
368 | a171fe39 | balrog | switch (offset & 0xf) { |
369 | a171fe39 | balrog | case DMA_FDADR:
|
370 | a171fe39 | balrog | return s->dma_ch[ch].descriptor;
|
371 | a171fe39 | balrog | case DMA_FSADR:
|
372 | a171fe39 | balrog | return s->dma_ch[ch].source;
|
373 | a171fe39 | balrog | case DMA_FIDR:
|
374 | a171fe39 | balrog | return s->dma_ch[ch].id;
|
375 | a171fe39 | balrog | case DMA_LDCMD:
|
376 | a171fe39 | balrog | return s->dma_ch[ch].command;
|
377 | a171fe39 | balrog | default:
|
378 | a171fe39 | balrog | goto fail;
|
379 | a171fe39 | balrog | } |
380 | a171fe39 | balrog | |
381 | a171fe39 | balrog | case FBR0:
|
382 | a171fe39 | balrog | return s->dma_ch[0].branch; |
383 | a171fe39 | balrog | case FBR1:
|
384 | a171fe39 | balrog | return s->dma_ch[1].branch; |
385 | a171fe39 | balrog | case FBR2:
|
386 | a171fe39 | balrog | return s->dma_ch[2].branch; |
387 | a171fe39 | balrog | case FBR3:
|
388 | a171fe39 | balrog | return s->dma_ch[3].branch; |
389 | a171fe39 | balrog | case FBR4:
|
390 | a171fe39 | balrog | return s->dma_ch[4].branch; |
391 | a171fe39 | balrog | case FBR5:
|
392 | a171fe39 | balrog | return s->dma_ch[5].branch; |
393 | a171fe39 | balrog | case FBR6:
|
394 | a171fe39 | balrog | return s->dma_ch[6].branch; |
395 | a171fe39 | balrog | |
396 | a171fe39 | balrog | case BSCNTR:
|
397 | a171fe39 | balrog | return s->bscntr;
|
398 | a171fe39 | balrog | |
399 | a171fe39 | balrog | case PRSR:
|
400 | a171fe39 | balrog | return 0; |
401 | a171fe39 | balrog | |
402 | a171fe39 | balrog | case LCSR0:
|
403 | a171fe39 | balrog | return s->status[0]; |
404 | a171fe39 | balrog | case LCSR1:
|
405 | a171fe39 | balrog | return s->status[1]; |
406 | a171fe39 | balrog | case LIIDR:
|
407 | a171fe39 | balrog | return s->liidr;
|
408 | a171fe39 | balrog | |
409 | a171fe39 | balrog | default:
|
410 | a171fe39 | balrog | fail:
|
411 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
412 | a171fe39 | balrog | } |
413 | a171fe39 | balrog | |
414 | a171fe39 | balrog | return 0; |
415 | a171fe39 | balrog | } |
416 | a171fe39 | balrog | |
417 | 5a6fdd91 | Benoît Canet | static void pxa2xx_lcdc_write(void *opaque, target_phys_addr_t offset, |
418 | 5a6fdd91 | Benoît Canet | uint64_t value, unsigned size)
|
419 | a171fe39 | balrog | { |
420 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
421 | a171fe39 | balrog | int ch;
|
422 | a171fe39 | balrog | |
423 | a171fe39 | balrog | switch (offset) {
|
424 | a171fe39 | balrog | case LCCR0:
|
425 | a171fe39 | balrog | /* ACK Quick Disable done */
|
426 | a171fe39 | balrog | if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB)) |
427 | a171fe39 | balrog | s->status[0] |= LCSR0_QD;
|
428 | a171fe39 | balrog | |
429 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT)) |
430 | a171fe39 | balrog | printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
|
431 | a171fe39 | balrog | |
432 | a171fe39 | balrog | if ((s->control[3] & LCCR3_API) && |
433 | a171fe39 | balrog | (value & LCCR0_ENB) && !(value & LCCR0_LCDT)) |
434 | a171fe39 | balrog | s->status[0] |= LCSR0_ABC;
|
435 | a171fe39 | balrog | |
436 | a171fe39 | balrog | s->control[0] = value & 0x07ffffff; |
437 | a171fe39 | balrog | pxa2xx_lcdc_int_update(s); |
438 | a171fe39 | balrog | |
439 | a171fe39 | balrog | s->dma_ch[0].up = !!(value & LCCR0_ENB);
|
440 | a171fe39 | balrog | s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS); |
441 | a171fe39 | balrog | break;
|
442 | a171fe39 | balrog | |
443 | a171fe39 | balrog | case LCCR1:
|
444 | a171fe39 | balrog | s->control[1] = value;
|
445 | a171fe39 | balrog | break;
|
446 | a171fe39 | balrog | |
447 | a171fe39 | balrog | case LCCR2:
|
448 | a171fe39 | balrog | s->control[2] = value;
|
449 | a171fe39 | balrog | break;
|
450 | a171fe39 | balrog | |
451 | a171fe39 | balrog | case LCCR3:
|
452 | a171fe39 | balrog | s->control[3] = value & 0xefffffff; |
453 | a171fe39 | balrog | s->bpp = LCCR3_BPP(value); |
454 | a171fe39 | balrog | break;
|
455 | a171fe39 | balrog | |
456 | a171fe39 | balrog | case LCCR4:
|
457 | a171fe39 | balrog | s->control[4] = value & 0x83ff81ff; |
458 | a171fe39 | balrog | break;
|
459 | a171fe39 | balrog | |
460 | a171fe39 | balrog | case LCCR5:
|
461 | a171fe39 | balrog | s->control[5] = value & 0x3f3f3f3f; |
462 | a171fe39 | balrog | break;
|
463 | a171fe39 | balrog | |
464 | a171fe39 | balrog | case OVL1C1:
|
465 | a171fe39 | balrog | if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
466 | a171fe39 | balrog | printf("%s: Overlay 1 not supported\n", __FUNCTION__);
|
467 | a171fe39 | balrog | |
468 | a171fe39 | balrog | s->ovl1c[0] = value & 0x80ffffff; |
469 | a171fe39 | balrog | s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS); |
470 | a171fe39 | balrog | break;
|
471 | a171fe39 | balrog | |
472 | a171fe39 | balrog | case OVL1C2:
|
473 | a171fe39 | balrog | s->ovl1c[1] = value & 0x000fffff; |
474 | a171fe39 | balrog | break;
|
475 | a171fe39 | balrog | |
476 | a171fe39 | balrog | case OVL2C1:
|
477 | a171fe39 | balrog | if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN)) |
478 | a171fe39 | balrog | printf("%s: Overlay 2 not supported\n", __FUNCTION__);
|
479 | a171fe39 | balrog | |
480 | a171fe39 | balrog | s->ovl2c[0] = value & 0x80ffffff; |
481 | a171fe39 | balrog | s->dma_ch[2].up = !!(value & OVLC1_EN);
|
482 | a171fe39 | balrog | s->dma_ch[3].up = !!(value & OVLC1_EN);
|
483 | a171fe39 | balrog | s->dma_ch[4].up = !!(value & OVLC1_EN);
|
484 | a171fe39 | balrog | break;
|
485 | a171fe39 | balrog | |
486 | a171fe39 | balrog | case OVL2C2:
|
487 | a171fe39 | balrog | s->ovl2c[1] = value & 0x007fffff; |
488 | a171fe39 | balrog | break;
|
489 | a171fe39 | balrog | |
490 | a171fe39 | balrog | case CCR:
|
491 | a171fe39 | balrog | if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
|
492 | a171fe39 | balrog | printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
|
493 | a171fe39 | balrog | |
494 | a171fe39 | balrog | s->ccr = value & 0x81ffffe7;
|
495 | a171fe39 | balrog | s->dma_ch[5].up = !!(value & CCR_CEN);
|
496 | a171fe39 | balrog | break;
|
497 | a171fe39 | balrog | |
498 | a171fe39 | balrog | case CMDCR:
|
499 | a171fe39 | balrog | s->cmdcr = value & 0xff;
|
500 | a171fe39 | balrog | break;
|
501 | a171fe39 | balrog | |
502 | a171fe39 | balrog | case TRGBR:
|
503 | a171fe39 | balrog | s->trgbr = value & 0x00ffffff;
|
504 | a171fe39 | balrog | break;
|
505 | a171fe39 | balrog | |
506 | a171fe39 | balrog | case TCR:
|
507 | a171fe39 | balrog | s->tcr = value & 0x7fff;
|
508 | a171fe39 | balrog | break;
|
509 | a171fe39 | balrog | |
510 | a171fe39 | balrog | case 0x200 ... 0x1000: /* DMA per-channel registers */ |
511 | a171fe39 | balrog | ch = (offset - 0x200) >> 4; |
512 | a171fe39 | balrog | if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS)) |
513 | a171fe39 | balrog | goto fail;
|
514 | a171fe39 | balrog | |
515 | a171fe39 | balrog | switch (offset & 0xf) { |
516 | a171fe39 | balrog | case DMA_FDADR:
|
517 | a171fe39 | balrog | s->dma_ch[ch].descriptor = value & 0xfffffff0;
|
518 | a171fe39 | balrog | break;
|
519 | a171fe39 | balrog | |
520 | a171fe39 | balrog | default:
|
521 | a171fe39 | balrog | goto fail;
|
522 | a171fe39 | balrog | } |
523 | a171fe39 | balrog | break;
|
524 | a171fe39 | balrog | |
525 | a171fe39 | balrog | case FBR0:
|
526 | a171fe39 | balrog | s->dma_ch[0].branch = value & 0xfffffff3; |
527 | a171fe39 | balrog | break;
|
528 | a171fe39 | balrog | case FBR1:
|
529 | a171fe39 | balrog | s->dma_ch[1].branch = value & 0xfffffff3; |
530 | a171fe39 | balrog | break;
|
531 | a171fe39 | balrog | case FBR2:
|
532 | a171fe39 | balrog | s->dma_ch[2].branch = value & 0xfffffff3; |
533 | a171fe39 | balrog | break;
|
534 | a171fe39 | balrog | case FBR3:
|
535 | a171fe39 | balrog | s->dma_ch[3].branch = value & 0xfffffff3; |
536 | a171fe39 | balrog | break;
|
537 | a171fe39 | balrog | case FBR4:
|
538 | a171fe39 | balrog | s->dma_ch[4].branch = value & 0xfffffff3; |
539 | a171fe39 | balrog | break;
|
540 | a171fe39 | balrog | case FBR5:
|
541 | a171fe39 | balrog | s->dma_ch[5].branch = value & 0xfffffff3; |
542 | a171fe39 | balrog | break;
|
543 | a171fe39 | balrog | case FBR6:
|
544 | a171fe39 | balrog | s->dma_ch[6].branch = value & 0xfffffff3; |
545 | a171fe39 | balrog | break;
|
546 | a171fe39 | balrog | |
547 | a171fe39 | balrog | case BSCNTR:
|
548 | a171fe39 | balrog | s->bscntr = value & 0xf;
|
549 | a171fe39 | balrog | break;
|
550 | a171fe39 | balrog | |
551 | a171fe39 | balrog | case PRSR:
|
552 | a171fe39 | balrog | break;
|
553 | a171fe39 | balrog | |
554 | a171fe39 | balrog | case LCSR0:
|
555 | a171fe39 | balrog | s->status[0] &= ~(value & 0xfff); |
556 | a171fe39 | balrog | if (value & LCSR0_BER)
|
557 | a171fe39 | balrog | s->status[0] &= ~LCSR0_BERCH(7); |
558 | a171fe39 | balrog | break;
|
559 | a171fe39 | balrog | |
560 | a171fe39 | balrog | case LCSR1:
|
561 | a171fe39 | balrog | s->status[1] &= ~(value & 0x3e3f3f); |
562 | a171fe39 | balrog | break;
|
563 | a171fe39 | balrog | |
564 | a171fe39 | balrog | default:
|
565 | a171fe39 | balrog | fail:
|
566 | 2ac71179 | Paul Brook | hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset); |
567 | a171fe39 | balrog | } |
568 | a171fe39 | balrog | } |
569 | a171fe39 | balrog | |
570 | 5a6fdd91 | Benoît Canet | static const MemoryRegionOps pxa2xx_lcdc_ops = { |
571 | 5a6fdd91 | Benoît Canet | .read = pxa2xx_lcdc_read, |
572 | 5a6fdd91 | Benoît Canet | .write = pxa2xx_lcdc_write, |
573 | 5a6fdd91 | Benoît Canet | .endianness = DEVICE_NATIVE_ENDIAN, |
574 | a171fe39 | balrog | }; |
575 | a171fe39 | balrog | |
576 | a171fe39 | balrog | /* Load new palette for a given DMA channel, convert to internal format */
|
577 | bc24a225 | Paul Brook | static void pxa2xx_palette_parse(PXA2xxLCDState *s, int ch, int bpp) |
578 | a171fe39 | balrog | { |
579 | a171fe39 | balrog | int i, n, format, r, g, b, alpha;
|
580 | 7ab3aedf | Vasily Khoruzhick | uint32_t *dest; |
581 | 7ab3aedf | Vasily Khoruzhick | uint8_t *src; |
582 | a171fe39 | balrog | s->pal_for = LCCR4_PALFOR(s->control[4]);
|
583 | a171fe39 | balrog | format = s->pal_for; |
584 | a171fe39 | balrog | |
585 | a171fe39 | balrog | switch (bpp) {
|
586 | a171fe39 | balrog | case pxa_lcdc_2bpp:
|
587 | a171fe39 | balrog | n = 4;
|
588 | a171fe39 | balrog | break;
|
589 | a171fe39 | balrog | case pxa_lcdc_4bpp:
|
590 | a171fe39 | balrog | n = 16;
|
591 | a171fe39 | balrog | break;
|
592 | a171fe39 | balrog | case pxa_lcdc_8bpp:
|
593 | a171fe39 | balrog | n = 256;
|
594 | a171fe39 | balrog | break;
|
595 | a171fe39 | balrog | default:
|
596 | a171fe39 | balrog | format = 0;
|
597 | a171fe39 | balrog | return;
|
598 | a171fe39 | balrog | } |
599 | a171fe39 | balrog | |
600 | 7ab3aedf | Vasily Khoruzhick | src = (uint8_t *) s->dma_ch[ch].pbuffer; |
601 | a171fe39 | balrog | dest = (uint32_t *) s->dma_ch[ch].palette; |
602 | a171fe39 | balrog | alpha = r = g = b = 0;
|
603 | a171fe39 | balrog | |
604 | a171fe39 | balrog | for (i = 0; i < n; i ++) { |
605 | a171fe39 | balrog | switch (format) {
|
606 | a171fe39 | balrog | case 0: /* 16 bpp, no transparency */ |
607 | a171fe39 | balrog | alpha = 0;
|
608 | 7ab3aedf | Vasily Khoruzhick | if (s->control[0] & LCCR0_CMS) { |
609 | 7ab3aedf | Vasily Khoruzhick | r = g = b = *(uint16_t *) src & 0xff;
|
610 | 7ab3aedf | Vasily Khoruzhick | } |
611 | a171fe39 | balrog | else {
|
612 | 7ab3aedf | Vasily Khoruzhick | r = (*(uint16_t *) src & 0xf800) >> 8; |
613 | 7ab3aedf | Vasily Khoruzhick | g = (*(uint16_t *) src & 0x07e0) >> 3; |
614 | 7ab3aedf | Vasily Khoruzhick | b = (*(uint16_t *) src & 0x001f) << 3; |
615 | a171fe39 | balrog | } |
616 | 7ab3aedf | Vasily Khoruzhick | src += 2;
|
617 | a171fe39 | balrog | break;
|
618 | a171fe39 | balrog | case 1: /* 16 bpp plus transparency */ |
619 | 7ab3aedf | Vasily Khoruzhick | alpha = *(uint16_t *) src & (1 << 24); |
620 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
621 | 7ab3aedf | Vasily Khoruzhick | r = g = b = *(uint16_t *) src & 0xff;
|
622 | a171fe39 | balrog | else {
|
623 | 7ab3aedf | Vasily Khoruzhick | r = (*(uint16_t *) src & 0xf800) >> 8; |
624 | 7ab3aedf | Vasily Khoruzhick | g = (*(uint16_t *) src & 0x07e0) >> 3; |
625 | 7ab3aedf | Vasily Khoruzhick | b = (*(uint16_t *) src & 0x001f) << 3; |
626 | a171fe39 | balrog | } |
627 | 7ab3aedf | Vasily Khoruzhick | src += 2;
|
628 | a171fe39 | balrog | break;
|
629 | a171fe39 | balrog | case 2: /* 18 bpp plus transparency */ |
630 | 7ab3aedf | Vasily Khoruzhick | alpha = *(uint32_t *) src & (1 << 24); |
631 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
632 | 7ab3aedf | Vasily Khoruzhick | r = g = b = *(uint32_t *) src & 0xff;
|
633 | a171fe39 | balrog | else {
|
634 | 7ab3aedf | Vasily Khoruzhick | r = (*(uint32_t *) src & 0xf80000) >> 16; |
635 | 7ab3aedf | Vasily Khoruzhick | g = (*(uint32_t *) src & 0x00fc00) >> 8; |
636 | 7ab3aedf | Vasily Khoruzhick | b = (*(uint32_t *) src & 0x0000f8);
|
637 | a171fe39 | balrog | } |
638 | 7ab3aedf | Vasily Khoruzhick | src += 4;
|
639 | a171fe39 | balrog | break;
|
640 | a171fe39 | balrog | case 3: /* 24 bpp plus transparency */ |
641 | 7ab3aedf | Vasily Khoruzhick | alpha = *(uint32_t *) src & (1 << 24); |
642 | a171fe39 | balrog | if (s->control[0] & LCCR0_CMS) |
643 | 7ab3aedf | Vasily Khoruzhick | r = g = b = *(uint32_t *) src & 0xff;
|
644 | a171fe39 | balrog | else {
|
645 | 7ab3aedf | Vasily Khoruzhick | r = (*(uint32_t *) src & 0xff0000) >> 16; |
646 | 7ab3aedf | Vasily Khoruzhick | g = (*(uint32_t *) src & 0x00ff00) >> 8; |
647 | 7ab3aedf | Vasily Khoruzhick | b = (*(uint32_t *) src & 0x0000ff);
|
648 | a171fe39 | balrog | } |
649 | 7ab3aedf | Vasily Khoruzhick | src += 4;
|
650 | a171fe39 | balrog | break;
|
651 | a171fe39 | balrog | } |
652 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
653 | a171fe39 | balrog | case 8: |
654 | a171fe39 | balrog | *dest = rgb_to_pixel8(r, g, b) | alpha; |
655 | a171fe39 | balrog | break;
|
656 | a171fe39 | balrog | case 15: |
657 | a171fe39 | balrog | *dest = rgb_to_pixel15(r, g, b) | alpha; |
658 | a171fe39 | balrog | break;
|
659 | a171fe39 | balrog | case 16: |
660 | a171fe39 | balrog | *dest = rgb_to_pixel16(r, g, b) | alpha; |
661 | a171fe39 | balrog | break;
|
662 | a171fe39 | balrog | case 24: |
663 | a171fe39 | balrog | *dest = rgb_to_pixel24(r, g, b) | alpha; |
664 | a171fe39 | balrog | break;
|
665 | a171fe39 | balrog | case 32: |
666 | a171fe39 | balrog | *dest = rgb_to_pixel32(r, g, b) | alpha; |
667 | a171fe39 | balrog | break;
|
668 | a171fe39 | balrog | } |
669 | a171fe39 | balrog | dest ++; |
670 | a171fe39 | balrog | } |
671 | a171fe39 | balrog | } |
672 | a171fe39 | balrog | |
673 | 9312805d | Vasily Khoruzhick | static void pxa2xx_lcdc_dma0_redraw_rot0(PXA2xxLCDState *s, |
674 | c227f099 | Anthony Liguori | target_phys_addr_t addr, int *miny, int *maxy) |
675 | a171fe39 | balrog | { |
676 | 714fa308 | pbrook | int src_width, dest_width;
|
677 | b9d38e95 | Blue Swirl | drawfn fn = NULL;
|
678 | a171fe39 | balrog | if (s->dest_width)
|
679 | a171fe39 | balrog | fn = s->line_fn[s->transp][s->bpp]; |
680 | a171fe39 | balrog | if (!fn)
|
681 | a171fe39 | balrog | return;
|
682 | a171fe39 | balrog | |
683 | a171fe39 | balrog | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
684 | a171fe39 | balrog | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
685 | a171fe39 | balrog | src_width *= 3;
|
686 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_16bpp) |
687 | a171fe39 | balrog | src_width *= 4;
|
688 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_8bpp) |
689 | a171fe39 | balrog | src_width *= 2;
|
690 | a171fe39 | balrog | |
691 | a171fe39 | balrog | dest_width = s->xres * s->dest_width; |
692 | 714fa308 | pbrook | *miny = 0;
|
693 | 75c9d6c2 | Avi Kivity | framebuffer_update_display(s->ds, s->sysmem, |
694 | 714fa308 | pbrook | addr, s->xres, s->yres, |
695 | 714fa308 | pbrook | src_width, dest_width, s->dest_width, |
696 | 714fa308 | pbrook | s->invalidated, |
697 | 714fa308 | pbrook | fn, s->dma_ch[0].palette, miny, maxy);
|
698 | a171fe39 | balrog | } |
699 | a171fe39 | balrog | |
700 | 9312805d | Vasily Khoruzhick | static void pxa2xx_lcdc_dma0_redraw_rot90(PXA2xxLCDState *s, |
701 | c227f099 | Anthony Liguori | target_phys_addr_t addr, int *miny, int *maxy) |
702 | a171fe39 | balrog | { |
703 | 714fa308 | pbrook | int src_width, dest_width;
|
704 | b9d38e95 | Blue Swirl | drawfn fn = NULL;
|
705 | a171fe39 | balrog | if (s->dest_width)
|
706 | a171fe39 | balrog | fn = s->line_fn[s->transp][s->bpp]; |
707 | a171fe39 | balrog | if (!fn)
|
708 | a171fe39 | balrog | return;
|
709 | a171fe39 | balrog | |
710 | a171fe39 | balrog | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
711 | a171fe39 | balrog | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
|
712 | a171fe39 | balrog | src_width *= 3;
|
713 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_16bpp) |
714 | a171fe39 | balrog | src_width *= 4;
|
715 | a171fe39 | balrog | else if (s->bpp > pxa_lcdc_8bpp) |
716 | a171fe39 | balrog | src_width *= 2;
|
717 | a171fe39 | balrog | |
718 | a171fe39 | balrog | dest_width = s->yres * s->dest_width; |
719 | 714fa308 | pbrook | *miny = 0;
|
720 | 75c9d6c2 | Avi Kivity | framebuffer_update_display(s->ds, s->sysmem, |
721 | 714fa308 | pbrook | addr, s->xres, s->yres, |
722 | 714fa308 | pbrook | src_width, s->dest_width, -dest_width, |
723 | 714fa308 | pbrook | s->invalidated, |
724 | 714fa308 | pbrook | fn, s->dma_ch[0].palette,
|
725 | 714fa308 | pbrook | miny, maxy); |
726 | a171fe39 | balrog | } |
727 | a171fe39 | balrog | |
728 | 9312805d | Vasily Khoruzhick | static void pxa2xx_lcdc_dma0_redraw_rot180(PXA2xxLCDState *s, |
729 | 9312805d | Vasily Khoruzhick | target_phys_addr_t addr, int *miny, int *maxy) |
730 | 9312805d | Vasily Khoruzhick | { |
731 | 9312805d | Vasily Khoruzhick | int src_width, dest_width;
|
732 | 9312805d | Vasily Khoruzhick | drawfn fn = NULL;
|
733 | 9312805d | Vasily Khoruzhick | if (s->dest_width) {
|
734 | 9312805d | Vasily Khoruzhick | fn = s->line_fn[s->transp][s->bpp]; |
735 | 9312805d | Vasily Khoruzhick | } |
736 | 9312805d | Vasily Khoruzhick | if (!fn) {
|
737 | 9312805d | Vasily Khoruzhick | return;
|
738 | 9312805d | Vasily Khoruzhick | } |
739 | 9312805d | Vasily Khoruzhick | |
740 | 9312805d | Vasily Khoruzhick | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
741 | 9312805d | Vasily Khoruzhick | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
|
742 | 9312805d | Vasily Khoruzhick | src_width *= 3;
|
743 | 9312805d | Vasily Khoruzhick | } else if (s->bpp > pxa_lcdc_16bpp) { |
744 | 9312805d | Vasily Khoruzhick | src_width *= 4;
|
745 | 9312805d | Vasily Khoruzhick | } else if (s->bpp > pxa_lcdc_8bpp) { |
746 | 9312805d | Vasily Khoruzhick | src_width *= 2;
|
747 | 9312805d | Vasily Khoruzhick | } |
748 | 9312805d | Vasily Khoruzhick | |
749 | 9312805d | Vasily Khoruzhick | dest_width = s->xres * s->dest_width; |
750 | 9312805d | Vasily Khoruzhick | *miny = 0;
|
751 | 75c9d6c2 | Avi Kivity | framebuffer_update_display(s->ds, s->sysmem, |
752 | 9312805d | Vasily Khoruzhick | addr, s->xres, s->yres, |
753 | 9312805d | Vasily Khoruzhick | src_width, -dest_width, -s->dest_width, |
754 | 9312805d | Vasily Khoruzhick | s->invalidated, |
755 | 9312805d | Vasily Khoruzhick | fn, s->dma_ch[0].palette, miny, maxy);
|
756 | 9312805d | Vasily Khoruzhick | } |
757 | 9312805d | Vasily Khoruzhick | |
758 | 9312805d | Vasily Khoruzhick | static void pxa2xx_lcdc_dma0_redraw_rot270(PXA2xxLCDState *s, |
759 | 9312805d | Vasily Khoruzhick | target_phys_addr_t addr, int *miny, int *maxy) |
760 | 9312805d | Vasily Khoruzhick | { |
761 | 9312805d | Vasily Khoruzhick | int src_width, dest_width;
|
762 | 9312805d | Vasily Khoruzhick | drawfn fn = NULL;
|
763 | 9312805d | Vasily Khoruzhick | if (s->dest_width) {
|
764 | 9312805d | Vasily Khoruzhick | fn = s->line_fn[s->transp][s->bpp]; |
765 | 9312805d | Vasily Khoruzhick | } |
766 | 9312805d | Vasily Khoruzhick | if (!fn) {
|
767 | 9312805d | Vasily Khoruzhick | return;
|
768 | 9312805d | Vasily Khoruzhick | } |
769 | 9312805d | Vasily Khoruzhick | |
770 | 9312805d | Vasily Khoruzhick | src_width = (s->xres + 3) & ~3; /* Pad to a 4 pixels multiple */ |
771 | 9312805d | Vasily Khoruzhick | if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp) {
|
772 | 9312805d | Vasily Khoruzhick | src_width *= 3;
|
773 | 9312805d | Vasily Khoruzhick | } else if (s->bpp > pxa_lcdc_16bpp) { |
774 | 9312805d | Vasily Khoruzhick | src_width *= 4;
|
775 | 9312805d | Vasily Khoruzhick | } else if (s->bpp > pxa_lcdc_8bpp) { |
776 | 9312805d | Vasily Khoruzhick | src_width *= 2;
|
777 | 9312805d | Vasily Khoruzhick | } |
778 | 9312805d | Vasily Khoruzhick | |
779 | 9312805d | Vasily Khoruzhick | dest_width = s->yres * s->dest_width; |
780 | 9312805d | Vasily Khoruzhick | *miny = 0;
|
781 | 75c9d6c2 | Avi Kivity | framebuffer_update_display(s->ds, s->sysmem, |
782 | 9312805d | Vasily Khoruzhick | addr, s->xres, s->yres, |
783 | 9312805d | Vasily Khoruzhick | src_width, -s->dest_width, dest_width, |
784 | 9312805d | Vasily Khoruzhick | s->invalidated, |
785 | 9312805d | Vasily Khoruzhick | fn, s->dma_ch[0].palette,
|
786 | 9312805d | Vasily Khoruzhick | miny, maxy); |
787 | 9312805d | Vasily Khoruzhick | } |
788 | 9312805d | Vasily Khoruzhick | |
789 | bc24a225 | Paul Brook | static void pxa2xx_lcdc_resize(PXA2xxLCDState *s) |
790 | a171fe39 | balrog | { |
791 | a171fe39 | balrog | int width, height;
|
792 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_ENB)) |
793 | a171fe39 | balrog | return;
|
794 | a171fe39 | balrog | |
795 | a171fe39 | balrog | width = LCCR1_PPL(s->control[1]) + 1; |
796 | a171fe39 | balrog | height = LCCR2_LPP(s->control[2]) + 1; |
797 | a171fe39 | balrog | |
798 | a171fe39 | balrog | if (width != s->xres || height != s->yres) {
|
799 | 9312805d | Vasily Khoruzhick | if (s->orientation == 90 || s->orientation == 270) { |
800 | 3023f332 | aliguori | qemu_console_resize(s->ds, height, width); |
801 | 9312805d | Vasily Khoruzhick | } else {
|
802 | 3023f332 | aliguori | qemu_console_resize(s->ds, width, height); |
803 | 9312805d | Vasily Khoruzhick | } |
804 | a171fe39 | balrog | s->invalidated = 1;
|
805 | a171fe39 | balrog | s->xres = width; |
806 | a171fe39 | balrog | s->yres = height; |
807 | a171fe39 | balrog | } |
808 | a171fe39 | balrog | } |
809 | a171fe39 | balrog | |
810 | a171fe39 | balrog | static void pxa2xx_update_display(void *opaque) |
811 | a171fe39 | balrog | { |
812 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
813 | c227f099 | Anthony Liguori | target_phys_addr_t fbptr; |
814 | a171fe39 | balrog | int miny, maxy;
|
815 | a171fe39 | balrog | int ch;
|
816 | a171fe39 | balrog | if (!(s->control[0] & LCCR0_ENB)) |
817 | a171fe39 | balrog | return;
|
818 | a171fe39 | balrog | |
819 | a171fe39 | balrog | pxa2xx_descriptor_load(s); |
820 | a171fe39 | balrog | |
821 | a171fe39 | balrog | pxa2xx_lcdc_resize(s); |
822 | a171fe39 | balrog | miny = s->yres; |
823 | a171fe39 | balrog | maxy = 0;
|
824 | a171fe39 | balrog | s->transp = s->dma_ch[2].up || s->dma_ch[3].up; |
825 | a171fe39 | balrog | /* Note: With overlay planes the order depends on LCCR0 bit 25. */
|
826 | a171fe39 | balrog | for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++) |
827 | a171fe39 | balrog | if (s->dma_ch[ch].up) {
|
828 | a171fe39 | balrog | if (!s->dma_ch[ch].source) {
|
829 | a171fe39 | balrog | pxa2xx_dma_ber_set(s, ch); |
830 | a171fe39 | balrog | continue;
|
831 | a171fe39 | balrog | } |
832 | a171fe39 | balrog | fbptr = s->dma_ch[ch].source; |
833 | d95b2f8d | balrog | if (!(fbptr >= PXA2XX_SDRAM_BASE &&
|
834 | b0457b69 | pbrook | fbptr <= PXA2XX_SDRAM_BASE + ram_size)) { |
835 | a171fe39 | balrog | pxa2xx_dma_ber_set(s, ch); |
836 | a171fe39 | balrog | continue;
|
837 | a171fe39 | balrog | } |
838 | a171fe39 | balrog | |
839 | a171fe39 | balrog | if (s->dma_ch[ch].command & LDCMD_PAL) {
|
840 | 714fa308 | pbrook | cpu_physical_memory_read(fbptr, s->dma_ch[ch].pbuffer, |
841 | 714fa308 | pbrook | MAX(LDCMD_LENGTH(s->dma_ch[ch].command), |
842 | 714fa308 | pbrook | sizeof(s->dma_ch[ch].pbuffer)));
|
843 | a171fe39 | balrog | pxa2xx_palette_parse(s, ch, s->bpp); |
844 | a171fe39 | balrog | } else {
|
845 | a171fe39 | balrog | /* Do we need to reparse palette */
|
846 | a171fe39 | balrog | if (LCCR4_PALFOR(s->control[4]) != s->pal_for) |
847 | a171fe39 | balrog | pxa2xx_palette_parse(s, ch, s->bpp); |
848 | a171fe39 | balrog | |
849 | a171fe39 | balrog | /* ACK frame start */
|
850 | a171fe39 | balrog | pxa2xx_dma_sof_set(s, ch); |
851 | a171fe39 | balrog | |
852 | 714fa308 | pbrook | s->dma_ch[ch].redraw(s, fbptr, &miny, &maxy); |
853 | a171fe39 | balrog | s->invalidated = 0;
|
854 | a171fe39 | balrog | |
855 | a171fe39 | balrog | /* ACK frame completed */
|
856 | a171fe39 | balrog | pxa2xx_dma_eof_set(s, ch); |
857 | a171fe39 | balrog | } |
858 | a171fe39 | balrog | } |
859 | a171fe39 | balrog | |
860 | a171fe39 | balrog | if (s->control[0] & LCCR0_DIS) { |
861 | a171fe39 | balrog | /* ACK last frame completed */
|
862 | a171fe39 | balrog | s->control[0] &= ~LCCR0_ENB;
|
863 | a171fe39 | balrog | s->status[0] |= LCSR0_LDD;
|
864 | a171fe39 | balrog | } |
865 | a171fe39 | balrog | |
866 | 714fa308 | pbrook | if (miny >= 0) { |
867 | 9312805d | Vasily Khoruzhick | switch (s->orientation) {
|
868 | 9312805d | Vasily Khoruzhick | case 0: |
869 | 9312805d | Vasily Khoruzhick | dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1); |
870 | 9312805d | Vasily Khoruzhick | break;
|
871 | 9312805d | Vasily Khoruzhick | case 90: |
872 | 9312805d | Vasily Khoruzhick | dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres); |
873 | 9312805d | Vasily Khoruzhick | break;
|
874 | 9312805d | Vasily Khoruzhick | case 180: |
875 | 9312805d | Vasily Khoruzhick | maxy = s->yres - maxy - 1;
|
876 | 9312805d | Vasily Khoruzhick | miny = s->yres - miny - 1;
|
877 | 9312805d | Vasily Khoruzhick | dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1); |
878 | 9312805d | Vasily Khoruzhick | break;
|
879 | 9312805d | Vasily Khoruzhick | case 270: |
880 | 9312805d | Vasily Khoruzhick | maxy = s->yres - maxy - 1;
|
881 | 9312805d | Vasily Khoruzhick | miny = s->yres - miny - 1;
|
882 | 9312805d | Vasily Khoruzhick | dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres); |
883 | 9312805d | Vasily Khoruzhick | break;
|
884 | 9312805d | Vasily Khoruzhick | } |
885 | 714fa308 | pbrook | } |
886 | a171fe39 | balrog | pxa2xx_lcdc_int_update(s); |
887 | a171fe39 | balrog | |
888 | 38641a52 | balrog | qemu_irq_raise(s->vsync_cb); |
889 | a171fe39 | balrog | } |
890 | a171fe39 | balrog | |
891 | a171fe39 | balrog | static void pxa2xx_invalidate_display(void *opaque) |
892 | a171fe39 | balrog | { |
893 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
894 | a171fe39 | balrog | s->invalidated = 1;
|
895 | a171fe39 | balrog | } |
896 | a171fe39 | balrog | |
897 | a171fe39 | balrog | static void pxa2xx_screen_dump(void *opaque, const char *filename) |
898 | a171fe39 | balrog | { |
899 | a171fe39 | balrog | /* TODO */
|
900 | a171fe39 | balrog | } |
901 | a171fe39 | balrog | |
902 | 9596ebb7 | pbrook | static void pxa2xx_lcdc_orientation(void *opaque, int angle) |
903 | a171fe39 | balrog | { |
904 | bc24a225 | Paul Brook | PXA2xxLCDState *s = (PXA2xxLCDState *) opaque; |
905 | a171fe39 | balrog | |
906 | 9312805d | Vasily Khoruzhick | switch (angle) {
|
907 | 9312805d | Vasily Khoruzhick | case 0: |
908 | 9312805d | Vasily Khoruzhick | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot0;
|
909 | 9312805d | Vasily Khoruzhick | break;
|
910 | 9312805d | Vasily Khoruzhick | case 90: |
911 | 9312805d | Vasily Khoruzhick | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot90;
|
912 | 9312805d | Vasily Khoruzhick | break;
|
913 | 9312805d | Vasily Khoruzhick | case 180: |
914 | 9312805d | Vasily Khoruzhick | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot180;
|
915 | 9312805d | Vasily Khoruzhick | break;
|
916 | 9312805d | Vasily Khoruzhick | case 270: |
917 | 9312805d | Vasily Khoruzhick | s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_rot270;
|
918 | 9312805d | Vasily Khoruzhick | break;
|
919 | a171fe39 | balrog | } |
920 | a171fe39 | balrog | |
921 | a171fe39 | balrog | s->orientation = angle; |
922 | a171fe39 | balrog | s->xres = s->yres = -1;
|
923 | a171fe39 | balrog | pxa2xx_lcdc_resize(s); |
924 | a171fe39 | balrog | } |
925 | a171fe39 | balrog | |
926 | 99838363 | Juan Quintela | static const VMStateDescription vmstate_dma_channel = { |
927 | 99838363 | Juan Quintela | .name = "dma_channel",
|
928 | 99838363 | Juan Quintela | .version_id = 0,
|
929 | 99838363 | Juan Quintela | .minimum_version_id = 0,
|
930 | 99838363 | Juan Quintela | .minimum_version_id_old = 0,
|
931 | 99838363 | Juan Quintela | .fields = (VMStateField[]) { |
932 | 99838363 | Juan Quintela | VMSTATE_UINTTL(branch, struct DMAChannel),
|
933 | 99838363 | Juan Quintela | VMSTATE_UINT8(up, struct DMAChannel),
|
934 | 99838363 | Juan Quintela | VMSTATE_BUFFER(pbuffer, struct DMAChannel),
|
935 | 99838363 | Juan Quintela | VMSTATE_UINTTL(descriptor, struct DMAChannel),
|
936 | 99838363 | Juan Quintela | VMSTATE_UINTTL(source, struct DMAChannel),
|
937 | 99838363 | Juan Quintela | VMSTATE_UINT32(id, struct DMAChannel),
|
938 | 99838363 | Juan Quintela | VMSTATE_UINT32(command, struct DMAChannel),
|
939 | 99838363 | Juan Quintela | VMSTATE_END_OF_LIST() |
940 | aa941b94 | balrog | } |
941 | 99838363 | Juan Quintela | }; |
942 | aa941b94 | balrog | |
943 | 99838363 | Juan Quintela | static int pxa2xx_lcdc_post_load(void *opaque, int version_id) |
944 | aa941b94 | balrog | { |
945 | 99838363 | Juan Quintela | PXA2xxLCDState *s = opaque; |
946 | aa941b94 | balrog | |
947 | aa941b94 | balrog | s->bpp = LCCR3_BPP(s->control[3]);
|
948 | aa941b94 | balrog | s->xres = s->yres = s->pal_for = -1;
|
949 | aa941b94 | balrog | |
950 | aa941b94 | balrog | return 0; |
951 | aa941b94 | balrog | } |
952 | aa941b94 | balrog | |
953 | 99838363 | Juan Quintela | static const VMStateDescription vmstate_pxa2xx_lcdc = { |
954 | 99838363 | Juan Quintela | .name = "pxa2xx_lcdc",
|
955 | 99838363 | Juan Quintela | .version_id = 0,
|
956 | 99838363 | Juan Quintela | .minimum_version_id = 0,
|
957 | 99838363 | Juan Quintela | .minimum_version_id_old = 0,
|
958 | 99838363 | Juan Quintela | .post_load = pxa2xx_lcdc_post_load, |
959 | 99838363 | Juan Quintela | .fields = (VMStateField[]) { |
960 | 99838363 | Juan Quintela | VMSTATE_INT32(irqlevel, PXA2xxLCDState), |
961 | 99838363 | Juan Quintela | VMSTATE_INT32(transp, PXA2xxLCDState), |
962 | 99838363 | Juan Quintela | VMSTATE_UINT32_ARRAY(control, PXA2xxLCDState, 6),
|
963 | 99838363 | Juan Quintela | VMSTATE_UINT32_ARRAY(status, PXA2xxLCDState, 2),
|
964 | 99838363 | Juan Quintela | VMSTATE_UINT32_ARRAY(ovl1c, PXA2xxLCDState, 2),
|
965 | 99838363 | Juan Quintela | VMSTATE_UINT32_ARRAY(ovl2c, PXA2xxLCDState, 2),
|
966 | 99838363 | Juan Quintela | VMSTATE_UINT32(ccr, PXA2xxLCDState), |
967 | 99838363 | Juan Quintela | VMSTATE_UINT32(cmdcr, PXA2xxLCDState), |
968 | 99838363 | Juan Quintela | VMSTATE_UINT32(trgbr, PXA2xxLCDState), |
969 | 99838363 | Juan Quintela | VMSTATE_UINT32(tcr, PXA2xxLCDState), |
970 | 99838363 | Juan Quintela | VMSTATE_UINT32(liidr, PXA2xxLCDState), |
971 | 99838363 | Juan Quintela | VMSTATE_UINT8(bscntr, PXA2xxLCDState), |
972 | 99838363 | Juan Quintela | VMSTATE_STRUCT_ARRAY(dma_ch, PXA2xxLCDState, 7, 0, |
973 | 99838363 | Juan Quintela | vmstate_dma_channel, struct DMAChannel),
|
974 | 99838363 | Juan Quintela | VMSTATE_END_OF_LIST() |
975 | 99838363 | Juan Quintela | } |
976 | 99838363 | Juan Quintela | }; |
977 | 99838363 | Juan Quintela | |
978 | a171fe39 | balrog | #define BITS 8 |
979 | a171fe39 | balrog | #include "pxa2xx_template.h" |
980 | a171fe39 | balrog | #define BITS 15 |
981 | a171fe39 | balrog | #include "pxa2xx_template.h" |
982 | a171fe39 | balrog | #define BITS 16 |
983 | a171fe39 | balrog | #include "pxa2xx_template.h" |
984 | a171fe39 | balrog | #define BITS 24 |
985 | a171fe39 | balrog | #include "pxa2xx_template.h" |
986 | a171fe39 | balrog | #define BITS 32 |
987 | a171fe39 | balrog | #include "pxa2xx_template.h" |
988 | a171fe39 | balrog | |
989 | 5a6fdd91 | Benoît Canet | PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, |
990 | 5a6fdd91 | Benoît Canet | target_phys_addr_t base, qemu_irq irq) |
991 | a171fe39 | balrog | { |
992 | bc24a225 | Paul Brook | PXA2xxLCDState *s; |
993 | a171fe39 | balrog | |
994 | 7267c094 | Anthony Liguori | s = (PXA2xxLCDState *) g_malloc0(sizeof(PXA2xxLCDState));
|
995 | a171fe39 | balrog | s->invalidated = 1;
|
996 | a171fe39 | balrog | s->irq = irq; |
997 | 75c9d6c2 | Avi Kivity | s->sysmem = sysmem; |
998 | a171fe39 | balrog | |
999 | a171fe39 | balrog | pxa2xx_lcdc_orientation(s, graphic_rotate); |
1000 | a171fe39 | balrog | |
1001 | 5a6fdd91 | Benoît Canet | memory_region_init_io(&s->iomem, &pxa2xx_lcdc_ops, s, |
1002 | 5a6fdd91 | Benoît Canet | "pxa2xx-lcd-controller", 0x00100000); |
1003 | 5a6fdd91 | Benoît Canet | memory_region_add_subregion(sysmem, base, &s->iomem); |
1004 | a171fe39 | balrog | |
1005 | 3023f332 | aliguori | s->ds = graphic_console_init(pxa2xx_update_display, |
1006 | 3023f332 | aliguori | pxa2xx_invalidate_display, |
1007 | 3023f332 | aliguori | pxa2xx_screen_dump, NULL, s);
|
1008 | a171fe39 | balrog | |
1009 | 0e1f5a0c | aliguori | switch (ds_get_bits_per_pixel(s->ds)) {
|
1010 | a171fe39 | balrog | case 0: |
1011 | a171fe39 | balrog | s->dest_width = 0;
|
1012 | a171fe39 | balrog | break;
|
1013 | a171fe39 | balrog | case 8: |
1014 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_8;
|
1015 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_8t;
|
1016 | a171fe39 | balrog | s->dest_width = 1;
|
1017 | a171fe39 | balrog | break;
|
1018 | a171fe39 | balrog | case 15: |
1019 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_15;
|
1020 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_15t;
|
1021 | a171fe39 | balrog | s->dest_width = 2;
|
1022 | a171fe39 | balrog | break;
|
1023 | a171fe39 | balrog | case 16: |
1024 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_16;
|
1025 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_16t;
|
1026 | a171fe39 | balrog | s->dest_width = 2;
|
1027 | a171fe39 | balrog | break;
|
1028 | a171fe39 | balrog | case 24: |
1029 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_24;
|
1030 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_24t;
|
1031 | a171fe39 | balrog | s->dest_width = 3;
|
1032 | a171fe39 | balrog | break;
|
1033 | a171fe39 | balrog | case 32: |
1034 | a171fe39 | balrog | s->line_fn[0] = pxa2xx_draw_fn_32;
|
1035 | a171fe39 | balrog | s->line_fn[1] = pxa2xx_draw_fn_32t;
|
1036 | a171fe39 | balrog | s->dest_width = 4;
|
1037 | a171fe39 | balrog | break;
|
1038 | a171fe39 | balrog | default:
|
1039 | a171fe39 | balrog | fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
|
1040 | a171fe39 | balrog | exit(1);
|
1041 | a171fe39 | balrog | } |
1042 | aa941b94 | balrog | |
1043 | 99838363 | Juan Quintela | vmstate_register(NULL, 0, &vmstate_pxa2xx_lcdc, s); |
1044 | aa941b94 | balrog | |
1045 | a171fe39 | balrog | return s;
|
1046 | a171fe39 | balrog | } |
1047 | a171fe39 | balrog | |
1048 | bc24a225 | Paul Brook | void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler)
|
1049 | 38641a52 | balrog | { |
1050 | 38641a52 | balrog | s->vsync_cb = handler; |
1051 | a171fe39 | balrog | } |