root / hw / piix_pci.c @ 0ef654e3
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/*
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* QEMU i440FX/PIIX3 PCI Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pc.h" |
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#include "pci.h" |
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#include "pci_host.h" |
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#include "isa.h" |
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#include "sysbus.h" |
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#include "range.h" |
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#include "xen.h" |
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/*
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* I440FX chipset data sheet.
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* http://download.intel.com/design/chipsets/datashts/29054901.pdf
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*/
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typedef PCIHostState I440FXState;
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#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */ |
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#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */ |
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#define XEN_PIIX_NUM_PIRQS 128ULL |
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#define PIIX_PIRQC 0x60 |
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typedef struct PIIX3State { |
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PCIDevice dev; |
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/*
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* bitmap to track pic levels.
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* The pic level is the logical OR of all the PCI irqs mapped to it
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* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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*
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* PIRQ is mapped to PIC pins, we track it by
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* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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* pic_irq * PIIX_NUM_PIRQS + pirq
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*/
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#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64 |
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#error "unable to encode pic state in 64bit in pic_levels." |
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#endif
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uint64_t pic_levels; |
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qemu_irq *pic; |
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/* This member isn't used. Just for save/load compatibility */
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int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS]; |
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} PIIX3State; |
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typedef struct PAMMemoryRegion { |
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MemoryRegion mem; |
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bool initialized;
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} PAMMemoryRegion; |
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struct PCII440FXState {
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PCIDevice dev; |
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MemoryRegion *system_memory; |
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MemoryRegion *pci_address_space; |
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MemoryRegion *ram_memory; |
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MemoryRegion pci_hole; |
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MemoryRegion pci_hole_64bit; |
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PAMMemoryRegion pam_regions[13];
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MemoryRegion smram_region; |
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uint8_t smm_enabled; |
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}; |
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#define I440FX_PAM 0x59 |
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#define I440FX_PAM_SIZE 7 |
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#define I440FX_SMRAM 0x72 |
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static void piix3_set_irq(void *opaque, int pirq, int level); |
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static void piix3_write_config_xen(PCIDevice *dev, |
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uint32_t address, uint32_t val, int len);
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/* return the global irq number corresponding to a given device irq
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pin. We could also use the bus number to have a more precise
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mapping. */
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static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx) |
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{ |
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int slot_addend;
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slot_addend = (pci_dev->devfn >> 3) - 1; |
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return (pci_intx + slot_addend) & 3; |
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} |
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static void update_pam(PCII440FXState *d, uint32_t start, uint32_t end, int r, |
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PAMMemoryRegion *mem) |
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{ |
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if (mem->initialized) {
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memory_region_del_subregion(d->system_memory, &mem->mem); |
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memory_region_destroy(&mem->mem); |
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} |
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// printf("ISA mapping %08x-0x%08x: %d\n", start, end, r);
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switch(r) {
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case 3: |
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/* RAM */
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memory_region_init_alias(&mem->mem, "pam-ram", d->ram_memory,
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start, end - start); |
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break;
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case 1: |
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/* ROM (XXX: not quite correct) */
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memory_region_init_alias(&mem->mem, "pam-rom", d->ram_memory,
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start, end - start); |
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memory_region_set_readonly(&mem->mem, true);
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break;
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case 2: |
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case 0: |
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/* XXX: should distinguish read/write cases */
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memory_region_init_alias(&mem->mem, "pam-pci", d->pci_address_space,
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start, end - start); |
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break;
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} |
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memory_region_add_subregion_overlap(d->system_memory, |
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start, &mem->mem, 1);
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mem->initialized = true;
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} |
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static void i440fx_update_memory_mappings(PCII440FXState *d) |
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{ |
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int i, r;
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uint32_t smram; |
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bool smram_enabled;
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memory_region_transaction_begin(); |
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update_pam(d, 0xf0000, 0x100000, (d->dev.config[I440FX_PAM] >> 4) & 3, |
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&d->pam_regions[0]);
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for(i = 0; i < 12; i++) { |
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r = (d->dev.config[(i >> 1) + (I440FX_PAM + 1)] >> ((i & 1) * 4)) & 3; |
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update_pam(d, 0xc0000 + 0x4000 * i, 0xc0000 + 0x4000 * (i + 1), r, |
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&d->pam_regions[i+1]);
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} |
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smram = d->dev.config[I440FX_SMRAM]; |
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smram_enabled = (d->smm_enabled && (smram & 0x08)) || (smram & 0x40); |
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memory_region_set_enabled(&d->smram_region, !smram_enabled); |
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memory_region_transaction_commit(); |
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} |
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static void i440fx_set_smm(int val, void *arg) |
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{ |
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PCII440FXState *d = arg; |
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val = (val != 0);
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if (d->smm_enabled != val) {
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d->smm_enabled = val; |
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i440fx_update_memory_mappings(d); |
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} |
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} |
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static void i440fx_write_config(PCIDevice *dev, |
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uint32_t address, uint32_t val, int len)
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{ |
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PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
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/* XXX: implement SMRAM.D_LOCK */
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pci_default_write_config(dev, address, val, len); |
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if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
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range_covers_byte(address, len, I440FX_SMRAM)) { |
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i440fx_update_memory_mappings(d); |
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} |
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} |
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static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id) |
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{ |
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PCII440FXState *d = opaque; |
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int ret, i;
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ret = pci_device_load(&d->dev, f); |
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if (ret < 0) |
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return ret;
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i440fx_update_memory_mappings(d); |
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qemu_get_8s(f, &d->smm_enabled); |
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if (version_id == 2) { |
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for (i = 0; i < PIIX_NUM_PIRQS; i++) { |
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qemu_get_be32(f); /* dummy load for compatibility */
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} |
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} |
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return 0; |
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} |
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static int i440fx_post_load(void *opaque, int version_id) |
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{ |
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PCII440FXState *d = opaque; |
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i440fx_update_memory_mappings(d); |
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return 0; |
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} |
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static const VMStateDescription vmstate_i440fx = { |
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.name = "I440FX",
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.version_id = 3,
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.minimum_version_id = 3,
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.minimum_version_id_old = 1,
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.load_state_old = i440fx_load_old, |
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.post_load = i440fx_post_load, |
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.fields = (VMStateField []) { |
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VMSTATE_PCI_DEVICE(dev, PCII440FXState), |
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VMSTATE_UINT8(smm_enabled, PCII440FXState), |
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VMSTATE_END_OF_LIST() |
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} |
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}; |
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static int i440fx_pcihost_initfn(SysBusDevice *dev) |
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{ |
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I440FXState *s = FROM_SYSBUS(I440FXState, dev); |
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memory_region_init_io(&s->conf_mem, &pci_host_conf_le_ops, s, |
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"pci-conf-idx", 4); |
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sysbus_add_io(dev, 0xcf8, &s->conf_mem);
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sysbus_init_ioports(&s->busdev, 0xcf8, 4); |
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memory_region_init_io(&s->data_mem, &pci_host_data_le_ops, s, |
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"pci-conf-data", 4); |
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sysbus_add_io(dev, 0xcfc, &s->data_mem);
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sysbus_init_ioports(&s->busdev, 0xcfc, 4); |
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return 0; |
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} |
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static int i440fx_initfn(PCIDevice *dev) |
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{ |
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PCII440FXState *d = DO_UPCAST(PCII440FXState, dev, dev); |
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d->dev.config[I440FX_SMRAM] = 0x02;
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cpu_smm_register(&i440fx_set_smm, d); |
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return 0; |
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} |
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static PCIBus *i440fx_common_init(const char *device_name, |
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PCII440FXState **pi440fx_state, |
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int *piix3_devfn,
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ISABus **isa_bus, qemu_irq *pic, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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ram_addr_t ram_size, |
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target_phys_addr_t pci_hole_start, |
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target_phys_addr_t pci_hole_size, |
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target_phys_addr_t pci_hole64_start, |
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target_phys_addr_t pci_hole64_size, |
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MemoryRegion *pci_address_space, |
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MemoryRegion *ram_memory) |
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{ |
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DeviceState *dev; |
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PCIBus *b; |
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PCIDevice *d; |
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I440FXState *s; |
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PIIX3State *piix3; |
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PCII440FXState *f; |
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dev = qdev_create(NULL, "i440FX-pcihost"); |
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s = FROM_SYSBUS(I440FXState, sysbus_from_qdev(dev)); |
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s->address_space = address_space_mem; |
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b = pci_bus_new(&s->busdev.qdev, NULL, pci_address_space,
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address_space_io, 0);
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s->bus = b; |
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qdev_init_nofail(dev); |
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qdev_property_add_child(qdev_get_root(), "i440fx", dev, NULL); |
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d = pci_create_simple(b, 0, device_name);
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*pi440fx_state = DO_UPCAST(PCII440FXState, dev, d); |
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f = *pi440fx_state; |
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f->system_memory = address_space_mem; |
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f->pci_address_space = pci_address_space; |
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f->ram_memory = ram_memory; |
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memory_region_init_alias(&f->pci_hole, "pci-hole", f->pci_address_space,
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pci_hole_start, pci_hole_size); |
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memory_region_add_subregion(f->system_memory, pci_hole_start, &f->pci_hole); |
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memory_region_init_alias(&f->pci_hole_64bit, "pci-hole64",
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f->pci_address_space, |
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pci_hole64_start, pci_hole64_size); |
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if (pci_hole64_size) {
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memory_region_add_subregion(f->system_memory, pci_hole64_start, |
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&f->pci_hole_64bit); |
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} |
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memory_region_init_alias(&f->smram_region, "smram-region",
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f->pci_address_space, 0xa0000, 0x20000); |
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memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
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&f->smram_region, 1);
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memory_region_set_enabled(&f->smram_region, false);
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/* Xen supports additional interrupt routes from the PCI devices to
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* the IOAPIC: the four pins of each PCI device on the bus are also
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* connected to the IOAPIC directly.
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* These additional routes can be discovered through ACPI. */
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if (xen_enabled()) {
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piix3 = DO_UPCAST(PIIX3State, dev, |
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pci_create_simple_multifunction(b, -1, true, "PIIX3-xen")); |
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pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq, |
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piix3, XEN_PIIX_NUM_PIRQS); |
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} else {
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piix3 = DO_UPCAST(PIIX3State, dev, |
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pci_create_simple_multifunction(b, -1, true, "PIIX3")); |
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pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3, |
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PIIX_NUM_PIRQS); |
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} |
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qdev_property_add_child(dev, "piix3", &piix3->dev.qdev, NULL); |
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piix3->pic = pic; |
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*isa_bus = DO_UPCAST(ISABus, qbus, |
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qdev_get_child_bus(&piix3->dev.qdev, "isa.0"));
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*piix3_devfn = piix3->dev.devfn; |
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ram_size = ram_size / 8 / 1024 / 1024; |
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if (ram_size > 255) |
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ram_size = 255;
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(*pi440fx_state)->dev.config[0x57]=ram_size;
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i440fx_update_memory_mappings(f); |
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return b;
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} |
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PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix3_devfn,
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ISABus **isa_bus, qemu_irq *pic, |
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MemoryRegion *address_space_mem, |
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MemoryRegion *address_space_io, |
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ram_addr_t ram_size, |
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target_phys_addr_t pci_hole_start, |
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target_phys_addr_t pci_hole_size, |
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target_phys_addr_t pci_hole64_start, |
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target_phys_addr_t pci_hole64_size, |
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MemoryRegion *pci_memory, MemoryRegion *ram_memory) |
346 |
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{ |
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PCIBus *b; |
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b = i440fx_common_init("i440FX", pi440fx_state, piix3_devfn, isa_bus, pic,
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address_space_mem, address_space_io, ram_size, |
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pci_hole_start, pci_hole_size, |
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pci_hole64_size, pci_hole64_size, |
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pci_memory, ram_memory); |
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return b;
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} |
357 |
|
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/* PIIX3 PCI to ISA bridge */
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static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq) |
360 |
{ |
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qemu_set_irq(piix3->pic[pic_irq], |
362 |
!!(piix3->pic_levels & |
363 |
(((1ULL << PIIX_NUM_PIRQS) - 1) << |
364 |
(pic_irq * PIIX_NUM_PIRQS)))); |
365 |
} |
366 |
|
367 |
static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level) |
368 |
{ |
369 |
int pic_irq;
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uint64_t mask; |
371 |
|
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pic_irq = piix3->dev.config[PIIX_PIRQC + pirq]; |
373 |
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
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374 |
return;
|
375 |
} |
376 |
|
377 |
mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
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piix3->pic_levels &= ~mask; |
379 |
piix3->pic_levels |= mask * !!level; |
380 |
|
381 |
piix3_set_irq_pic(piix3, pic_irq); |
382 |
} |
383 |
|
384 |
static void piix3_set_irq(void *opaque, int pirq, int level) |
385 |
{ |
386 |
PIIX3State *piix3 = opaque; |
387 |
piix3_set_irq_level(piix3, pirq, level); |
388 |
} |
389 |
|
390 |
/* irq routing is changed. so rebuild bitmap */
|
391 |
static void piix3_update_irq_levels(PIIX3State *piix3) |
392 |
{ |
393 |
int pirq;
|
394 |
|
395 |
piix3->pic_levels = 0;
|
396 |
for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) { |
397 |
piix3_set_irq_level(piix3, pirq, |
398 |
pci_bus_get_irq_level(piix3->dev.bus, pirq)); |
399 |
} |
400 |
} |
401 |
|
402 |
static void piix3_write_config(PCIDevice *dev, |
403 |
uint32_t address, uint32_t val, int len)
|
404 |
{ |
405 |
pci_default_write_config(dev, address, val, len); |
406 |
if (ranges_overlap(address, len, PIIX_PIRQC, 4)) { |
407 |
PIIX3State *piix3 = DO_UPCAST(PIIX3State, dev, dev); |
408 |
int pic_irq;
|
409 |
piix3_update_irq_levels(piix3); |
410 |
for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) { |
411 |
piix3_set_irq_pic(piix3, pic_irq); |
412 |
} |
413 |
} |
414 |
} |
415 |
|
416 |
static void piix3_write_config_xen(PCIDevice *dev, |
417 |
uint32_t address, uint32_t val, int len)
|
418 |
{ |
419 |
xen_piix_pci_write_config_client(address, val, len); |
420 |
piix3_write_config(dev, address, val, len); |
421 |
} |
422 |
|
423 |
static void piix3_reset(void *opaque) |
424 |
{ |
425 |
PIIX3State *d = opaque; |
426 |
uint8_t *pci_conf = d->dev.config; |
427 |
|
428 |
pci_conf[0x04] = 0x07; // master, memory and I/O |
429 |
pci_conf[0x05] = 0x00; |
430 |
pci_conf[0x06] = 0x00; |
431 |
pci_conf[0x07] = 0x02; // PCI_status_devsel_medium |
432 |
pci_conf[0x4c] = 0x4d; |
433 |
pci_conf[0x4e] = 0x03; |
434 |
pci_conf[0x4f] = 0x00; |
435 |
pci_conf[0x60] = 0x80; |
436 |
pci_conf[0x61] = 0x80; |
437 |
pci_conf[0x62] = 0x80; |
438 |
pci_conf[0x63] = 0x80; |
439 |
pci_conf[0x69] = 0x02; |
440 |
pci_conf[0x70] = 0x80; |
441 |
pci_conf[0x76] = 0x0c; |
442 |
pci_conf[0x77] = 0x0c; |
443 |
pci_conf[0x78] = 0x02; |
444 |
pci_conf[0x79] = 0x00; |
445 |
pci_conf[0x80] = 0x00; |
446 |
pci_conf[0x82] = 0x00; |
447 |
pci_conf[0xa0] = 0x08; |
448 |
pci_conf[0xa2] = 0x00; |
449 |
pci_conf[0xa3] = 0x00; |
450 |
pci_conf[0xa4] = 0x00; |
451 |
pci_conf[0xa5] = 0x00; |
452 |
pci_conf[0xa6] = 0x00; |
453 |
pci_conf[0xa7] = 0x00; |
454 |
pci_conf[0xa8] = 0x0f; |
455 |
pci_conf[0xaa] = 0x00; |
456 |
pci_conf[0xab] = 0x00; |
457 |
pci_conf[0xac] = 0x00; |
458 |
pci_conf[0xae] = 0x00; |
459 |
|
460 |
d->pic_levels = 0;
|
461 |
} |
462 |
|
463 |
static int piix3_post_load(void *opaque, int version_id) |
464 |
{ |
465 |
PIIX3State *piix3 = opaque; |
466 |
piix3_update_irq_levels(piix3); |
467 |
return 0; |
468 |
} |
469 |
|
470 |
static void piix3_pre_save(void *opaque) |
471 |
{ |
472 |
int i;
|
473 |
PIIX3State *piix3 = opaque; |
474 |
|
475 |
for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) { |
476 |
piix3->pci_irq_levels_vmstate[i] = |
477 |
pci_bus_get_irq_level(piix3->dev.bus, i); |
478 |
} |
479 |
} |
480 |
|
481 |
static const VMStateDescription vmstate_piix3 = { |
482 |
.name = "PIIX3",
|
483 |
.version_id = 3,
|
484 |
.minimum_version_id = 2,
|
485 |
.minimum_version_id_old = 2,
|
486 |
.post_load = piix3_post_load, |
487 |
.pre_save = piix3_pre_save, |
488 |
.fields = (VMStateField []) { |
489 |
VMSTATE_PCI_DEVICE(dev, PIIX3State), |
490 |
VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State, |
491 |
PIIX_NUM_PIRQS, 3),
|
492 |
VMSTATE_END_OF_LIST() |
493 |
} |
494 |
}; |
495 |
|
496 |
static int piix3_initfn(PCIDevice *dev) |
497 |
{ |
498 |
PIIX3State *d = DO_UPCAST(PIIX3State, dev, dev); |
499 |
|
500 |
isa_bus_new(&d->dev.qdev, pci_address_space_io(dev)); |
501 |
qemu_register_reset(piix3_reset, d); |
502 |
return 0; |
503 |
} |
504 |
|
505 |
static void piix3_class_init(ObjectClass *klass, void *data) |
506 |
{ |
507 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
508 |
|
509 |
k->no_hotplug = 1;
|
510 |
k->init = piix3_initfn; |
511 |
k->config_write = piix3_write_config; |
512 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
513 |
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
|
514 |
k->class_id = PCI_CLASS_BRIDGE_ISA; |
515 |
} |
516 |
|
517 |
static DeviceInfo piix3_info = {
|
518 |
.name = "PIIX3",
|
519 |
.desc = "ISA bridge",
|
520 |
.size = sizeof(PIIX3State),
|
521 |
.vmsd = &vmstate_piix3, |
522 |
.no_user = 1,
|
523 |
.class_init = piix3_class_init, |
524 |
}; |
525 |
|
526 |
static void piix3_xen_class_init(ObjectClass *klass, void *data) |
527 |
{ |
528 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
529 |
|
530 |
k->no_hotplug = 1;
|
531 |
k->init = piix3_initfn; |
532 |
k->config_write = piix3_write_config_xen; |
533 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
534 |
k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
|
535 |
k->class_id = PCI_CLASS_BRIDGE_ISA; |
536 |
}; |
537 |
|
538 |
static DeviceInfo piix3_xen_info = {
|
539 |
.name = "PIIX3-xen",
|
540 |
.desc = "ISA bridge",
|
541 |
.size = sizeof(PIIX3State),
|
542 |
.vmsd = &vmstate_piix3, |
543 |
.no_user = 1,
|
544 |
.class_init = piix3_xen_class_init, |
545 |
}; |
546 |
|
547 |
static void i440fx_class_init(ObjectClass *klass, void *data) |
548 |
{ |
549 |
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); |
550 |
|
551 |
k->no_hotplug = 1;
|
552 |
k->init = i440fx_initfn; |
553 |
k->config_write = i440fx_write_config; |
554 |
k->vendor_id = PCI_VENDOR_ID_INTEL; |
555 |
k->device_id = PCI_DEVICE_ID_INTEL_82441; |
556 |
k->revision = 0x02;
|
557 |
k->class_id = PCI_CLASS_BRIDGE_HOST; |
558 |
} |
559 |
|
560 |
static DeviceInfo i440fx_info = {
|
561 |
.name = "i440FX",
|
562 |
.desc = "Host bridge",
|
563 |
.size = sizeof(PCII440FXState),
|
564 |
.vmsd = &vmstate_i440fx, |
565 |
.no_user = 1,
|
566 |
.class_init = i440fx_class_init, |
567 |
}; |
568 |
|
569 |
static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) |
570 |
{ |
571 |
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); |
572 |
|
573 |
k->init = i440fx_pcihost_initfn; |
574 |
} |
575 |
|
576 |
static DeviceInfo i440fx_pcihost_info = {
|
577 |
.name = "i440FX-pcihost",
|
578 |
.fw_name = "pci",
|
579 |
.size = sizeof(I440FXState),
|
580 |
.no_user = 1,
|
581 |
.class_init = i440fx_pcihost_class_init, |
582 |
}; |
583 |
|
584 |
static void i440fx_register(void) |
585 |
{ |
586 |
pci_qdev_register(&i440fx_info); |
587 |
pci_qdev_register(&piix3_info); |
588 |
pci_qdev_register(&piix3_xen_info); |
589 |
sysbus_register_withprop(&i440fx_pcihost_info); |
590 |
} |
591 |
device_init(i440fx_register); |