Archipelago » qemu

/*

 * QEMU KVM support

 *

 * Copyright (C) 2006-2008 Qumranet Technologies

 * Copyright IBM, Corp. 2008

 *

 * Authors:

 *  Anthony Liguori   <aliguori@us.ibm.com>

 *

 * This work is licensed under the terms of the GNU GPL, version 2 or later.

 * See the COPYING file in the top-level directory.

 *

 */

#include <sys/types.h>

#include <sys/ioctl.h>

#include <sys/mman.h>

#include <sys/utsname.h>

#include <linux/kvm.h>

#include <linux/kvm_para.h>

#include "qemu-common.h"

#include "sysemu/sysemu.h"

#include "sysemu/kvm.h"

#include "kvm_i386.h"

#include "cpu.h"

#include "exec/gdbstub.h"

#include "qemu/host-utils.h"

#include "qemu/config-file.h"

#include "hw/i386/pc.h"

#include "hw/i386/apic.h"

#include "exec/ioport.h"

#include <asm/hyperv.h>

#include "hw/pci/pci.h"

//#define DEBUG_KVM

#ifdef DEBUG_KVM

#define DPRINTF(fmt, ...) \

    do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)

#else

#define DPRINTF(fmt, ...) \

    do { } while (0)

#endif

#define MSR_KVM_WALL_CLOCK  0x11

#define MSR_KVM_SYSTEM_TIME 0x12

#ifndef BUS_MCEERR_AR

#define BUS_MCEERR_AR 4

#endif

#ifndef BUS_MCEERR_AO

#define BUS_MCEERR_AO 5

#endif

const KVMCapabilityInfo kvm_arch_required_capabilities[] = {

    KVM_CAP_INFO(SET_TSS_ADDR),

    KVM_CAP_INFO(EXT_CPUID),

    KVM_CAP_INFO(MP_STATE),

    KVM_CAP_LAST_INFO

};

static bool has_msr_star;

static bool has_msr_hsave_pa;

static bool has_msr_tsc_adjust;

static bool has_msr_tsc_deadline;

static bool has_msr_feature_control;

static bool has_msr_async_pf_en;

static bool has_msr_pv_eoi_en;

static bool has_msr_misc_enable;

static bool has_msr_kvm_steal_time;

static int lm_capable_kernel;

static bool has_msr_architectural_pmu;

static uint32_t num_architectural_pmu_counters;

bool kvm_allows_irq0_override(void)

{

    return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();

}

static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)

{

    struct kvm_cpuid2 *cpuid;

    int r, size;

    size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);

    cpuid = (struct kvm_cpuid2 *)g_malloc0(size);

    cpuid->nent = max;

    r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);

    if (r == 0 && cpuid->nent >= max) {

        r = -E2BIG;

    }

    if (r < 0) {

        if (r == -E2BIG) {

            g_free(cpuid);

            return NULL;

        } else {

            fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",

                    strerror(-r));

            exit(1);

        }

    }

    return cpuid;

}

/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough

 * for all entries.

 */

static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s)

{

    struct kvm_cpuid2 *cpuid;

    int max = 1;

    while ((cpuid = try_get_cpuid(s, max)) == NULL) {

        max *= 2;

    }

    return cpuid;

}

struct kvm_para_features {

    int cap;

    int feature;

} para_features[] = {

    { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },

    { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },

    { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },

    { KVM_CAP_ASYNC_PF, KVM_FEATURE_ASYNC_PF },

    { -1, -1 }

};

static int get_para_features(KVMState *s)

{

    int i, features = 0;

    for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {

        if (kvm_check_extension(s, para_features[i].cap)) {

            features |= (1 << para_features[i].feature);

        }

    }

    return features;

}

/* Returns the value for a specific register on the cpuid entry

 */

static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg)

{

    uint32_t ret = 0;

    switch (reg) {

    case R_EAX:

        ret = entry->eax;

        break;

    case R_EBX:

        ret = entry->ebx;

        break;

    case R_ECX:

        ret = entry->ecx;

        break;

    case R_EDX:

        ret = entry->edx;

        break;

    }

    return ret;

}

/* Find matching entry for function/index on kvm_cpuid2 struct

 */

static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid,

                                                 uint32_t function,

                                                 uint32_t index)

{

    int i;

    for (i = 0; i < cpuid->nent; ++i) {

        if (cpuid->entries[i].function == function &&

            cpuid->entries[i].index == index) {

            return &cpuid->entries[i];

        }

    }

    /* not found: */

    return NULL;

}

uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function,

                                      uint32_t index, int reg)

{

    struct kvm_cpuid2 *cpuid;

    uint32_t ret = 0;

    uint32_t cpuid_1_edx;

    bool found = false;

    cpuid = get_supported_cpuid(s);

    struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index);

    if (entry) {

        found = true;

        ret = cpuid_entry_get_reg(entry, reg);

    }

    /* Fixups for the data returned by KVM, below */

    if (function == 1 && reg == R_EDX) {

        /* KVM before 2.6.30 misreports the following features */

        ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;

    } else if (function == 1 && reg == R_ECX) {

        /* We can set the hypervisor flag, even if KVM does not return it on

         * GET_SUPPORTED_CPUID

         */

        ret |= CPUID_EXT_HYPERVISOR;

        /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it

         * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,

         * and the irqchip is in the kernel.

         */

        if (kvm_irqchip_in_kernel() &&

                kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) {

            ret |= CPUID_EXT_TSC_DEADLINE_TIMER;

        }

        /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled

         * without the in-kernel irqchip

         */

        if (!kvm_irqchip_in_kernel()) {

            ret &= ~CPUID_EXT_X2APIC;

        }

    } else if (function == 0x80000001 && reg == R_EDX) {

        /* On Intel, kvm returns cpuid according to the Intel spec,

         * so add missing bits according to the AMD spec:

         */

        cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX);

        ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES;

    }

    g_free(cpuid);

    /* fallback for older kernels */

    if ((function == KVM_CPUID_FEATURES) && !found) {

        ret = get_para_features(s);

    }

    return ret;

}

typedef struct HWPoisonPage {

    ram_addr_t ram_addr;

    QLIST_ENTRY(HWPoisonPage) list;

} HWPoisonPage;

static QLIST_HEAD(, HWPoisonPage) hwpoison_page_list =

    QLIST_HEAD_INITIALIZER(hwpoison_page_list);

static void kvm_unpoison_all(void *param)

{

    HWPoisonPage *page, *next_page;

    QLIST_FOREACH_SAFE(page, &hwpoison_page_list, list, next_page) {

        QLIST_REMOVE(page, list);

        qemu_ram_remap(page->ram_addr, TARGET_PAGE_SIZE);

        g_free(page);

    }

}

static void kvm_hwpoison_page_add(ram_addr_t ram_addr)

{

    HWPoisonPage *page;

    QLIST_FOREACH(page, &hwpoison_page_list, list) {

        if (page->ram_addr == ram_addr) {

            return;

        }

    }

    page = g_malloc(sizeof(HWPoisonPage));

    page->ram_addr = ram_addr;

    QLIST_INSERT_HEAD(&hwpoison_page_list, page, list);

}

static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap,

                                     int *max_banks)

{

    int r;

    r = kvm_check_extension(s, KVM_CAP_MCE);

    if (r > 0) {

        *max_banks = r;

        return kvm_ioctl(s, KVM_X86_GET_MCE_CAP_SUPPORTED, mce_cap);

    }

    return -ENOSYS;

}

static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code)

{

    CPUX86State *env = &cpu->env;

    uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |

                      MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S;

    uint64_t mcg_status = MCG_STATUS_MCIP;

    if (code == BUS_MCEERR_AR) {

        status |= MCI_STATUS_AR | 0x134;

        mcg_status |= MCG_STATUS_EIPV;

    } else {

        status |= 0xc0;

        mcg_status |= MCG_STATUS_RIPV;

    }

    cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr,

                       (MCM_ADDR_PHYS << 6) | 0xc,

                       cpu_x86_support_mca_broadcast(env) ?

                       MCE_INJECT_BROADCAST : 0);

}

static void hardware_memory_error(void)

{

    fprintf(stderr, "Hardware memory error!\n");

    exit(1);

}

int kvm_arch_on_sigbus_vcpu(CPUState *c, int code, void *addr)

{

    X86CPU *cpu = X86_CPU(c);

    CPUX86State *env = &cpu->env;

    ram_addr_t ram_addr;

    hwaddr paddr;

    if ((env->mcg_cap & MCG_SER_P) && addr

        && (code == BUS_MCEERR_AR || code == BUS_MCEERR_AO)) {

        if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||

            !kvm_physical_memory_addr_from_host(c->kvm_state, addr, &paddr)) {

            fprintf(stderr, "Hardware memory error for memory used by "

                    "QEMU itself instead of guest system!\n");

            /* Hope we are lucky for AO MCE */

            if (code == BUS_MCEERR_AO) {

                return 0;

            } else {

                hardware_memory_error();

            }

        }

        kvm_hwpoison_page_add(ram_addr);

        kvm_mce_inject(cpu, paddr, code);

    } else {

        if (code == BUS_MCEERR_AO) {

            return 0;

        } else if (code == BUS_MCEERR_AR) {

            hardware_memory_error();

        } else {

            return 1;

        }

    }

    return 0;

}

int kvm_arch_on_sigbus(int code, void *addr)

{

    X86CPU *cpu = X86_CPU(first_cpu);

    if ((cpu->env.mcg_cap & MCG_SER_P) && addr && code == BUS_MCEERR_AO) {

        ram_addr_t ram_addr;

        hwaddr paddr;

        /* Hope we are lucky for AO MCE */

        if (qemu_ram_addr_from_host(addr, &ram_addr) == NULL ||

            !kvm_physical_memory_addr_from_host(first_cpu->kvm_state,

                                                addr, &paddr)) {

            fprintf(stderr, "Hardware memory error for memory used by "

                    "QEMU itself instead of guest system!: %p\n", addr);

            return 0;

        }

        kvm_hwpoison_page_add(ram_addr);

        kvm_mce_inject(X86_CPU(first_cpu), paddr, code);

    } else {

        if (code == BUS_MCEERR_AO) {

            return 0;

        } else if (code == BUS_MCEERR_AR) {

            hardware_memory_error();

        } else {

            return 1;

        }

    }

    return 0;

}

static int kvm_inject_mce_oldstyle(X86CPU *cpu)

{

    CPUX86State *env = &cpu->env;

    if (!kvm_has_vcpu_events() && env->exception_injected == EXCP12_MCHK) {

        unsigned int bank, bank_num = env->mcg_cap & 0xff;

        struct kvm_x86_mce mce;

        env->exception_injected = -1;

        /*

         * There must be at least one bank in use if an MCE is pending.

         * Find it and use its values for the event injection.

         */

        for (bank = 0; bank < bank_num; bank++) {

            if (env->mce_banks[bank * 4 + 1] & MCI_STATUS_VAL) {

                break;

            }

        }

        assert(bank < bank_num);

        mce.bank = bank;

        mce.status = env->mce_banks[bank * 4 + 1];

        mce.mcg_status = env->mcg_status;

        mce.addr = env->mce_banks[bank * 4 + 2];

        mce.misc = env->mce_banks[bank * 4 + 3];

        return kvm_vcpu_ioctl(CPU(cpu), KVM_X86_SET_MCE, &mce);

    }

    return 0;

}

static void cpu_update_state(void *opaque, int running, RunState state)

{

    CPUX86State *env = opaque;

    if (running) {

        env->tsc_valid = false;

    }

}

unsigned long kvm_arch_vcpu_id(CPUState *cs)

{

    X86CPU *cpu = X86_CPU(cs);

    return cpu->env.cpuid_apic_id;

}

#ifndef KVM_CPUID_SIGNATURE_NEXT

#define KVM_CPUID_SIGNATURE_NEXT                0x40000100

#endif

static bool hyperv_hypercall_available(X86CPU *cpu)

{

    return cpu->hyperv_vapic ||

           (cpu->hyperv_spinlock_attempts != HYPERV_SPINLOCK_NEVER_RETRY);

}

static bool hyperv_enabled(X86CPU *cpu)

{

    return hyperv_hypercall_available(cpu) ||

           cpu->hyperv_relaxed_timing;

}

#define KVM_MAX_CPUID_ENTRIES  100

int kvm_arch_init_vcpu(CPUState *cs)

{

    struct {

        struct kvm_cpuid2 cpuid;

        struct kvm_cpuid_entry2 entries[KVM_MAX_CPUID_ENTRIES];

    } QEMU_PACKED cpuid_data;

    X86CPU *cpu = X86_CPU(cs);

    CPUX86State *env = &cpu->env;

    uint32_t limit, i, j, cpuid_i;

    uint32_t unused;

    struct kvm_cpuid_entry2 *c;

    uint32_t signature[3];

    int r;

    cpuid_i = 0;

    /* Paravirtualization CPUIDs */

    c = &cpuid_data.entries[cpuid_i++];

    memset(c, 0, sizeof(*c));

    c->function = KVM_CPUID_SIGNATURE;

    if (!hyperv_enabled(cpu)) {

        memcpy(signature, "KVMKVMKVM\0\0\0", 12);

        c->eax = 0;

    } else {

        memcpy(signature, "Microsoft Hv", 12);

        c->eax = HYPERV_CPUID_MIN;

    }

    c->ebx = signature[0];

    c->ecx = signature[1];

    c->edx = signature[2];

    c = &cpuid_data.entries[cpuid_i++];

    memset(c, 0, sizeof(*c));

    c->function = KVM_CPUID_FEATURES;

    c->eax = env->features[FEAT_KVM];

    if (hyperv_enabled(cpu)) {

        memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12);

        c->eax = signature[0];

        c = &cpuid_data.entries[cpuid_i++];

        memset(c, 0, sizeof(*c));

        c->function = HYPERV_CPUID_VERSION;

        c->eax = 0x00001bbc;

        c->ebx = 0x00060001;

        c = &cpuid_data.entries[cpuid_i++];

        memset(c, 0, sizeof(*c));

        c->function = HYPERV_CPUID_FEATURES;

        if (cpu->hyperv_relaxed_timing) {

            c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;

        }

        if (cpu->hyperv_vapic) {

            c->eax |= HV_X64_MSR_HYPERCALL_AVAILABLE;

            c->eax |= HV_X64_MSR_APIC_ACCESS_AVAILABLE;

        }

        c = &cpuid_data.entries[cpuid_i++];

        memset(c, 0, sizeof(*c));

        c->function = HYPERV_CPUID_ENLIGHTMENT_INFO;

        if (cpu->hyperv_relaxed_timing) {

            c->eax |= HV_X64_RELAXED_TIMING_RECOMMENDED;

        }

        if (cpu->hyperv_vapic) {

            c->eax |= HV_X64_APIC_ACCESS_RECOMMENDED;

        }

        c->ebx = cpu->hyperv_spinlock_attempts;

        c = &cpuid_data.entries[cpuid_i++];

        memset(c, 0, sizeof(*c));

        c->function = HYPERV_CPUID_IMPLEMENT_LIMITS;

        c->eax = 0x40;

        c->ebx = 0x40;

        c = &cpuid_data.entries[cpuid_i++];

        memset(c, 0, sizeof(*c));

        c->function = KVM_CPUID_SIGNATURE_NEXT;

        memcpy(signature, "KVMKVMKVM\0\0\0", 12);

        c->eax = 0;

        c->ebx = signature[0];

        c->ecx = signature[1];

        c->edx = signature[2];

    }

    has_msr_async_pf_en = c->eax & (1 << KVM_FEATURE_ASYNC_PF);

    has_msr_pv_eoi_en = c->eax & (1 << KVM_FEATURE_PV_EOI);

    has_msr_kvm_steal_time = c->eax & (1 << KVM_FEATURE_STEAL_TIME);

    cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);

    for (i = 0; i <= limit; i++) {

        if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {

            fprintf(stderr, "unsupported level value: 0x%x\n", limit);

            abort();

        }

        c = &cpuid_data.entries[cpuid_i++];

        switch (i) {

        case 2: {

            /* Keep reading function 2 till all the input is received */

            int times;

            c->function = i;

            c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |

                       KVM_CPUID_FLAG_STATE_READ_NEXT;

            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);

            times = c->eax & 0xff;

            for (j = 1; j < times; ++j) {

                if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {

                    fprintf(stderr, "cpuid_data is full, no space for "

                            "cpuid(eax:2):eax & 0xf = 0x%x\n", times);

                    abort();

                }

                c = &cpuid_data.entries[cpuid_i++];

                c->function = i;

                c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;

                cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);

            }

            break;

        }

        case 4:

        case 0xb:

        case 0xd:

            for (j = 0; ; j++) {

                if (i == 0xd && j == 64) {

                    break;

                }

                c->function = i;

                c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;

                c->index = j;

                cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);

                if (i == 4 && c->eax == 0) {

                    break;

                }

                if (i == 0xb && !(c->ecx & 0xff00)) {

                    break;

                }

                if (i == 0xd && c->eax == 0) {

                    continue;

                }

                if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {

                    fprintf(stderr, "cpuid_data is full, no space for "

                            "cpuid(eax:0x%x,ecx:0x%x)\n", i, j);

                    abort();

                }

                c = &cpuid_data.entries[cpuid_i++];

            }

            break;

        default:

            c->function = i;

            c->flags = 0;

            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);

            break;

        }

    }

    if (limit >= 0x0a) {

        uint32_t ver;

        cpu_x86_cpuid(env, 0x0a, 0, &ver, &unused, &unused, &unused);

        if ((ver & 0xff) > 0) {

            has_msr_architectural_pmu = true;

            num_architectural_pmu_counters = (ver & 0xff00) >> 8;

            /* Shouldn't be more than 32, since that's the number of bits

             * available in EBX to tell us _which_ counters are available.

             * Play it safe.

             */

            if (num_architectural_pmu_counters > MAX_GP_COUNTERS) {

                num_architectural_pmu_counters = MAX_GP_COUNTERS;

            }

        }

    }

    cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);

    for (i = 0x80000000; i <= limit; i++) {

        if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {

            fprintf(stderr, "unsupported xlevel value: 0x%x\n", limit);

            abort();

        }

        c = &cpuid_data.entries[cpuid_i++];

        c->function = i;

        c->flags = 0;

        cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);

    }

    /* Call Centaur's CPUID instructions they are supported. */

    if (env->cpuid_xlevel2 > 0) {

        cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused);

        for (i = 0xC0000000; i <= limit; i++) {

            if (cpuid_i == KVM_MAX_CPUID_ENTRIES) {

                fprintf(stderr, "unsupported xlevel2 value: 0x%x\n", limit);

                abort();

            }

            c = &cpuid_data.entries[cpuid_i++];

            c->function = i;

            c->flags = 0;

            cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);

        }

    }

    cpuid_data.cpuid.nent = cpuid_i;

    if (((env->cpuid_version >> 8)&0xF) >= 6

        && (env->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==

           (CPUID_MCE | CPUID_MCA)

        && kvm_check_extension(cs->kvm_state, KVM_CAP_MCE) > 0) {

        uint64_t mcg_cap;

        int banks;

        int ret;

        ret = kvm_get_mce_cap_supported(cs->kvm_state, &mcg_cap, &banks);

        if (ret < 0) {

            fprintf(stderr, "kvm_get_mce_cap_supported: %s", strerror(-ret));

            return ret;

        }

        if (banks > MCE_BANKS_DEF) {

            banks = MCE_BANKS_DEF;

        }

        mcg_cap &= MCE_CAP_DEF;

        mcg_cap |= banks;

        ret = kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap);

        if (ret < 0) {

            fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret));

            return ret;

        }

        env->mcg_cap = mcg_cap;

    }

    qemu_add_vm_change_state_handler(cpu_update_state, env);

    c = cpuid_find_entry(&cpuid_data.cpuid, 1, 0);

    if (c) {

        has_msr_feature_control = !!(c->ecx & CPUID_EXT_VMX) ||

                                  !!(c->ecx & CPUID_EXT_SMX);

    }

    cpuid_data.cpuid.padding = 0;

    r = kvm_vcpu_ioctl(cs, KVM_SET_CPUID2, &cpuid_data);

    if (r) {

        return r;

    }

    r = kvm_check_extension(cs->kvm_state, KVM_CAP_TSC_CONTROL);

    if (r && env->tsc_khz) {

        r = kvm_vcpu_ioctl(cs, KVM_SET_TSC_KHZ, env->tsc_khz);

        if (r < 0) {

            fprintf(stderr, "KVM_SET_TSC_KHZ failed\n");

            return r;

        }

    }

    if (kvm_has_xsave()) {

        env->kvm_xsave_buf = qemu_memalign(4096, sizeof(struct kvm_xsave));

    }

    return 0;

}

void kvm_arch_reset_vcpu(CPUState *cs)

{

    X86CPU *cpu = X86_CPU(cs);

    CPUX86State *env = &cpu->env;

    env->exception_injected = -1;

    env->interrupt_injected = -1;

    env->xcr0 = 1;

    if (kvm_irqchip_in_kernel()) {

        env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE :

                                          KVM_MP_STATE_UNINITIALIZED;

    } else {

        env->mp_state = KVM_MP_STATE_RUNNABLE;

    }

}

static int kvm_get_supported_msrs(KVMState *s)

{

    static int kvm_supported_msrs;

    int ret = 0;

    /* first time */

    if (kvm_supported_msrs == 0) {

        struct kvm_msr_list msr_list, *kvm_msr_list;

        kvm_supported_msrs = -1;

        /* Obtain MSR list from KVM.  These are the MSRs that we must

         * save/restore */

        msr_list.nmsrs = 0;

        ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, &msr_list);

        if (ret < 0 && ret != -E2BIG) {

            return ret;

        }

        /* Old kernel modules had a bug and could write beyond the provided

           memory. Allocate at least a safe amount of 1K. */

        kvm_msr_list = g_malloc0(MAX(1024, sizeof(msr_list) +

                                              msr_list.nmsrs *

                                              sizeof(msr_list.indices[0])));

        kvm_msr_list->nmsrs = msr_list.nmsrs;

        ret = kvm_ioctl(s, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);

        if (ret >= 0) {

            int i;

            for (i = 0; i < kvm_msr_list->nmsrs; i++) {

                if (kvm_msr_list->indices[i] == MSR_STAR) {

                    has_msr_star = true;

                    continue;

                }

                if (kvm_msr_list->indices[i] == MSR_VM_HSAVE_PA) {

                    has_msr_hsave_pa = true;

                    continue;

                }

                if (kvm_msr_list->indices[i] == MSR_TSC_ADJUST) {

                    has_msr_tsc_adjust = true;

                    continue;

                }

                if (kvm_msr_list->indices[i] == MSR_IA32_TSCDEADLINE) {

                    has_msr_tsc_deadline = true;

                    continue;

                }

                if (kvm_msr_list->indices[i] == MSR_IA32_MISC_ENABLE) {

                    has_msr_misc_enable = true;

                    continue;

                }

            }

        }

        g_free(kvm_msr_list);

    }

    return ret;

}

int kvm_arch_init(KVMState *s)

{

    uint64_t identity_base = 0xfffbc000;

    uint64_t shadow_mem;

    int ret;

    struct utsname utsname;

    ret = kvm_get_supported_msrs(s);

    if (ret < 0) {

        return ret;

    }

    uname(&utsname);

    lm_capable_kernel = strcmp(utsname.machine, "x86_64") == 0;

    /*

     * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.

     * In order to use vm86 mode, an EPT identity map and a TSS  are needed.

     * Since these must be part of guest physical memory, we need to allocate

     * them, both by setting their start addresses in the kernel and by

     * creating a corresponding e820 entry. We need 4 pages before the BIOS.

     *

     * Older KVM versions may not support setting the identity map base. In

     * that case we need to stick with the default, i.e. a 256K maximum BIOS

     * size.

     */

    if (kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {

        /* Allows up to 16M BIOSes. */

        identity_base = 0xfeffc000;

        ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &identity_base);

        if (ret < 0) {

            return ret;

        }

    }

    /* Set TSS base one page after EPT identity map. */

    ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, identity_base + 0x1000);

    if (ret < 0) {

        return ret;

    }

    /* Tell fw_cfg to notify the BIOS to reserve the range. */

    ret = e820_add_entry(identity_base, 0x4000, E820_RESERVED);

    if (ret < 0) {

        fprintf(stderr, "e820_add_entry() table is full\n");

        return ret;

    }

    qemu_register_reset(kvm_unpoison_all, NULL);

    shadow_mem = qemu_opt_get_size(qemu_get_machine_opts(),

                                   "kvm_shadow_mem", -1);

    if (shadow_mem != -1) {

        shadow_mem /= 4096;

        ret = kvm_vm_ioctl(s, KVM_SET_NR_MMU_PAGES, shadow_mem);

        if (ret < 0) {

            return ret;

        }

    }

    return 0;

}

static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)

{

    lhs->selector = rhs->selector;

    lhs->base = rhs->base;

    lhs->limit = rhs->limit;

    lhs->type = 3;

    lhs->present = 1;

    lhs->dpl = 3;

    lhs->db = 0;

    lhs->s = 1;

    lhs->l = 0;

    lhs->g = 0;

    lhs->avl = 0;

    lhs->unusable = 0;

}

static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)

{

    unsigned flags = rhs->flags;

    lhs->selector = rhs->selector;

    lhs->base = rhs->base;

    lhs->limit = rhs->limit;

    lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;

    lhs->present = (flags & DESC_P_MASK) != 0;

    lhs->dpl = (flags >> DESC_DPL_SHIFT) & 3;

    lhs->db = (flags >> DESC_B_SHIFT) & 1;

    lhs->s = (flags & DESC_S_MASK) != 0;

    lhs->l = (flags >> DESC_L_SHIFT) & 1;

    lhs->g = (flags & DESC_G_MASK) != 0;

    lhs->avl = (flags & DESC_AVL_MASK) != 0;

    lhs->unusable = 0;

    lhs->padding = 0;

}

static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)

{

    lhs->selector = rhs->selector;

    lhs->base = rhs->base;

    lhs->limit = rhs->limit;

    lhs->flags = (rhs->type << DESC_TYPE_SHIFT) |

                 (rhs->present * DESC_P_MASK) |

                 (rhs->dpl << DESC_DPL_SHIFT) |

                 (rhs->db << DESC_B_SHIFT) |

                 (rhs->s * DESC_S_MASK) |

                 (rhs->l << DESC_L_SHIFT) |

                 (rhs->g * DESC_G_MASK) |

                 (rhs->avl * DESC_AVL_MASK);

}