hw/arm/exynos4210.c: convert chipid_and_omr to an mmio region
Exynos SoC was misusing memory_region_init_ram_ptr(): this interface can safelybe used only for memory regions which size is a multiple of target page size.Change chipid_and_omr memory to an mmio region to fix this....
sd/sdhci.c: Fix bdata_read DPRINT message
This message was printing out the data in decimal only, which is notvery friendly to the debugging developer. Add hex variant inparenthesis to make it consistent with other similar messages in thismodule.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>...
sd/sdhci:ADMA: fix interrupt
The end of transfer check was occurring and potentially returning beforethe interrupt flag was checked. This means the interrupt will be missedif it occurs on the last packet. Fix by checking for the interruptbefore checking for the end of transfer....
sd/sd.c: Fix "inquiry" ACMD41
QEMU models two (of the three) ACMD41 has two modes, "inquiry" and"first". The selection logic for which of the two is incorrect - itcompares != 0 for the entire argument value rather than only bits 23:0as per the spec. Fix....
i.MX: split GPT and EPIT timer implementation
There is no common code between these 2 timer implementation.So it is better to split them.
Signed-off-by: Jean-Christophe DUBOIS <jcd@tribudubois.net>Message-id: 1368990197-19694-1-git-send-email-jcd@tribudubois.net...
xilinx_spips: lqspi: Push more data to tx-fifo
Do 16 words per fifo flush. Increases performance and decreasesdebug verbosity. This data depth has no real hardware analogue,so just go with something that has reasonable performance.
xilinx_spips: lqspi: Fix byte/misaligned access
The LQSPI bus attachment supports byte/halfword and misalignedaccesses. Fixed. Refactored the LQSPI cache to be byte-wiseinstead of word wise accordingly.
sd/sdhci.c: Only reset data_count on new commands
The data_count variable was being reset on every transfer, includingDMA transfer resumptions. This is incorrect, it should only be seton a new command.
Manifests as a bug when using ADMA and there is a timer delay between...
sd/sdhci: Fix Buffer Write Ready interrupt
This interrupt is not risen after the last block is written to sd. Itis mutually exclusive with the end of transfer conditions. Fix.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Igor Mitsyanko <i.mitsyanko@gmail.com>...
xilinx_spips: Multiple debug verbosity levels
The debug printfs on every SPI operation is extremely verbose. Adda second level of debug for this.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
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