target-arm: Handle UNDEF cases for Neon invalid modified-immediates
For Neon "one register and a modified immediate value" forms, thecombination op=1 cmode=1111 is unallocated and should UNDEF.All instructions of this form also UNDEF if Q 1 and Vd<0> 1....
target-arm: Handle UNDEF cases for Neon 3-regs-different-widths
Add missing UNDEF checks for instructions in the Neon "3 registers ofdifferent widths" data processing space.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms
Add missing checks for cases which must UNDEF in the Neon "2 registers anda scalar" data processing instruction space.
target-arm: Handle UNDEF cases for VEXT
VEXT must UNDEF if Q 1 && (Vd<0> 1 || Vr<0> 1 || Vm<0> 1)
target-arm: Simplify checking of size field in Neon 2reg-misc forms
Many of the Neon "2 register misc" instruction forms require invalidsize fields to cause the instruction to UNDEF. Pull this informationout into an array; this simplifies the code and also means we can do...
target-arm: Handle UNDEF cases for Neon 2 register misc forms
Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF if Q==1 && (Vd<0> 1 || Vm<0> 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q 1 || Vm<0> 1...
target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF
Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF itrather than allowing the helper function to index off the endof the register file.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-arm: Handle UNDEF cases for VDUP (scalar)
Handle the UNDEF cases for VDUP: imm4 x000 Q 1 && Vd<0> == 1
Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-arm: Collapse VSRI case into VSHL, VSLI
Collapse some switch cases for VSRI into those for VSHL, VSLI,since the bodies are the same. (This is not completely obviousfor the size < 3 case, but since for VSRI we know U=1 theGEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded...
target-arm: Handle UNDEF cases for Neon "2 regs and shift" insns
Correctly handle all the UNDEF cases for Neon instructions of the"2 registers and shift" form, and make sure that we check for thesecases early enough not to leak TCG temporaries.
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