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TCG/PPC: use stack for TCG temps
Use stack instead of temp_buf array in CPUState for TCG temps.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc: Remove tcg_out_addi
The only user (within tcg.c) was removed
Signed-off-by: malc <av1474@comtv.ru>
Delegate setup of TCG temporaries to targets
Delegate TCG temp_buf setup to targets, so that they can use a stackframe later instead.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
cpu-exec.c: avoid AREG0 use
Make functions take a parameter for CPUState instead of relyingon global env. Pass CPUState pointer to TCG prologue, which movesit to AREG0.
Thanks to Peter Maydell and Laurent Desnogues for the ARM prologuechange.
Revert the hacks to avoid AREG0 use on Sparc hosts....
tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.
We need not reserve the register unless we're going to use it.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: malc <av1474@comtv.ru>
tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologueare unused outside of tcg.c.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64to perform the move at the proper width, which may elide a REX prefix.
Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data"...
tcg/ppc: Remove redundant comparison from brcond2
tcg/ppc: Fix signed versions of brcond2
Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.
tcg/ppc: Fix typo
tcg/ppc: Implment bswap16/32
tcg/ppc: Implement eqv, nand and nor
Split TLB addend and target_phys_addr_t
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,so needed to be able to hold both host addresses (unsigned long) and guestphysical addresses (target_phys_addr_t). However since the introduction of...
tcg/ppc: Fix not_i32
Thanks to Alexander Graf for bug report and a good reproducible testcase.
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Use TCGCond where appropriate.
Use the TCGCond enumeration type in the brcond and setcondrelated prototypes in tcg-op.h and each code generator.
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
tcg/ppc64: Only define addend load helpers in softmmu case
tcg/ppc: Fix right rotation
tcg/ppc: Implement some of the optional ops
tcg: fix build on 32-bit hppa, ppc and sparc hosts
The qemu_ld32s op is only defined if TCG_TARGET_REG_BITS == 64.
Signed-off-by: Jay Foad <jay.foad@gmail.com>Signed-off-by: malc <av1474@comtv.ru>
tcg/ppc: Consistently use calling convention selection macros
tcg/ppc32: proper setcond implementation
tcg/ppc32: implement setcond2
tcg/ppc: always use tcg_out_call
When targeting PPU use rlwinm instead of andi. if possible
andi. is microcoded and slow there.
Fix rbase initialization
PPC 32/64 GUEST_BASE support
Fix LHZX opcode value
Whack [LS]MW
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7081 c046a42c-6fe2-441c-8c8c-71466251a162
Remove reserved registers from tcg_target_reg_alloc_order
Noticed by Andreas Faerber
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7080 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing r24..r26 to calle save registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6612 c046a42c-6fe2-441c-8c8c-71466251a162
R13 is reserved for small data area pointer by SVR4 PPC ABI
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6450 c046a42c-6fe2-441c-8c8c-71466251a162
Use the ARRAY_SIZE() macro where appropriate.
Change from v1: Avoid changing the existing coding style in certain files.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6120 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary AIX support
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5732 c046a42c-6fe2-441c-8c8c-71466251a162
Rename misnamed BACK_CHAIN_OFFSET to LR_OFFSET
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5711 c046a42c-6fe2-441c-8c8c-71466251a162
Add some missing static and const qualifiers, reg_names only used if NDEBUG set
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
Avoid clobbering input register in qemu_ld64+bswap+useronly case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5287 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
Relax qemu_ld/st constraints for !SOFTMMU case
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5038 c046a42c-6fe2-441c-8c8c-71466251a162
Account for MacOS X ABI reserved space in linkage area (Andreas Faerber)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4985 c046a42c-6fe2-441c-8c8c-71466251a162
Preliminary MacOS X on PPC32 support
Big thanks to BlueSwirl for Sparc failure analysis.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4984 c046a42c-6fe2-441c-8c8c-71466251a162
On ppc32 make tb_set_jmp_target1 behave like it does on a ppc64
Avoids nasty warnings about flush_icache_range from gcc4 and inabilityto compile [cpu-]exec.c with gcc3 and -O, also the function is muchtoo large to be candidate for inlining anyway.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4974 c046a42c-6fe2-441c-8c8c-71466251a162
Do not try handle "special" arguments of and/or/xor/shl/shr, upper level does it
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4961 c046a42c-6fe2-441c-8c8c-71466251a162
Provide extNs_M instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4934 c046a42c-6fe2-441c-8c8c-71466251a162
Fuse EQ and NE handling in tcg_out_brcond2
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4845 c046a42c-6fe2-441c-8c8c-71466251a162
Mask LL portion of B to 24 bits in tcg_out_b (Thanks to Thiemo Seufer)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4841 c046a42c-6fe2-441c-8c8c-71466251a162
According to gcc-4.3.0/gcc/config/rs6000/crtsavres.asm R13 is volatile
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4779 c046a42c-6fe2-441c-8c8c-71466251a162
Shuffle contents of tcg_target_reg_alloc_order
Move reserved/volatile registers down. Currently qemu_ld/stXX aremarked with TCG_OPF_CALL_CLOBBER and since memory accesses arefrequent and R3 through R12 are volatile moving this down results inless spills and tighter generated code....
Save LR into proper place on callers stack frame
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4745 c046a42c-6fe2-441c-8c8c-71466251a162
Reimplement brcond2 and refactor brcond
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4738 c046a42c-6fe2-441c-8c8c-71466251a162
Remove stray variable
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4725 c046a42c-6fe2-441c-8c8c-71466251a162
Use rem/div[u]_i32 drop div[u]2_i32
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4722 c046a42c-6fe2-441c-8c8c-71466251a162
Emit trampolines manually in prologue
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4715 c046a42c-6fe2-441c-8c8c-71466251a162
Fix test for signed div fast path
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4714 c046a42c-6fe2-441c-8c8c-71466251a162
Fix div[u]2.
Previous code assummed 32 by 32 bit divmod operation, and survivedx86_64 test only by sheer luck. MIPS wasn't so forgiving.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4705 c046a42c-6fe2-441c-8c8c-71466251a162
PPC TCG Fixes
support of long calls for PPC (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4629 c046a42c-6fe2-441c-8c8c-71466251a162
Fix signed/unsigned issues of immediate version of brcond (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4588 c046a42c-6fe2-441c-8c8c-71466251a162
ppc TCG target (malc)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4584 c046a42c-6fe2-441c-8c8c-71466251a162