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1 | 267002cd | bellard | /*
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2 | 3cbee15b | j_mayer | * QEMU PowerMac CUDA device support
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3 | 5fafdf24 | ths | *
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4 | 3cbee15b | j_mayer | * Copyright (c) 2004-2007 Fabrice Bellard
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5 | 3cbee15b | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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6 | 5fafdf24 | ths | *
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7 | 267002cd | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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8 | 267002cd | bellard | * of this software and associated documentation files (the "Software"), to deal
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9 | 267002cd | bellard | * in the Software without restriction, including without limitation the rights
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10 | 267002cd | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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11 | 267002cd | bellard | * copies of the Software, and to permit persons to whom the Software is
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12 | 267002cd | bellard | * furnished to do so, subject to the following conditions:
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13 | 267002cd | bellard | *
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14 | 267002cd | bellard | * The above copyright notice and this permission notice shall be included in
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15 | 267002cd | bellard | * all copies or substantial portions of the Software.
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16 | 267002cd | bellard | *
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17 | 267002cd | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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18 | 267002cd | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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19 | 267002cd | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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20 | 267002cd | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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21 | 267002cd | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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22 | 267002cd | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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23 | 267002cd | bellard | * THE SOFTWARE.
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24 | 267002cd | bellard | */
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25 | 87ecb68b | pbrook | #include "hw.h" |
26 | 3cbee15b | j_mayer | #include "ppc_mac.h" |
27 | 7a880d93 | Laurent Vivier | #include "adb.h" |
28 | 87ecb68b | pbrook | #include "qemu-timer.h" |
29 | 87ecb68b | pbrook | #include "sysemu.h" |
30 | 267002cd | bellard | |
31 | 61271e5c | bellard | /* XXX: implement all timer modes */
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32 | 61271e5c | bellard | |
33 | ea026b2f | blueswir1 | /* debug CUDA */
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34 | 819e712b | bellard | //#define DEBUG_CUDA
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35 | ea026b2f | blueswir1 | |
36 | ea026b2f | blueswir1 | /* debug CUDA packets */
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37 | 819e712b | bellard | //#define DEBUG_CUDA_PACKET
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38 | 819e712b | bellard | |
39 | ea026b2f | blueswir1 | #ifdef DEBUG_CUDA
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40 | 001faf32 | Blue Swirl | #define CUDA_DPRINTF(fmt, ...) \
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41 | 001faf32 | Blue Swirl | do { printf("CUDA: " fmt , ## __VA_ARGS__); } while (0) |
42 | ea026b2f | blueswir1 | #else
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43 | 001faf32 | Blue Swirl | #define CUDA_DPRINTF(fmt, ...)
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44 | ea026b2f | blueswir1 | #endif
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45 | ea026b2f | blueswir1 | |
46 | 267002cd | bellard | /* Bits in B data register: all active low */
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47 | 267002cd | bellard | #define TREQ 0x08 /* Transfer request (input) */ |
48 | 267002cd | bellard | #define TACK 0x10 /* Transfer acknowledge (output) */ |
49 | 267002cd | bellard | #define TIP 0x20 /* Transfer in progress (output) */ |
50 | 267002cd | bellard | |
51 | 267002cd | bellard | /* Bits in ACR */
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52 | 267002cd | bellard | #define SR_CTRL 0x1c /* Shift register control bits */ |
53 | 267002cd | bellard | #define SR_EXT 0x0c /* Shift on external clock */ |
54 | 267002cd | bellard | #define SR_OUT 0x10 /* Shift out if 1 */ |
55 | 267002cd | bellard | |
56 | 267002cd | bellard | /* Bits in IFR and IER */
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57 | 267002cd | bellard | #define IER_SET 0x80 /* set bits in IER */ |
58 | 267002cd | bellard | #define IER_CLR 0 /* clear bits in IER */ |
59 | 267002cd | bellard | #define SR_INT 0x04 /* Shift register full/empty */ |
60 | 267002cd | bellard | #define T1_INT 0x40 /* Timer 1 interrupt */ |
61 | 61271e5c | bellard | #define T2_INT 0x20 /* Timer 2 interrupt */ |
62 | 267002cd | bellard | |
63 | 267002cd | bellard | /* Bits in ACR */
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64 | 267002cd | bellard | #define T1MODE 0xc0 /* Timer 1 mode */ |
65 | 267002cd | bellard | #define T1MODE_CONT 0x40 /* continuous interrupts */ |
66 | 267002cd | bellard | |
67 | 267002cd | bellard | /* commands (1st byte) */
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68 | 267002cd | bellard | #define ADB_PACKET 0 |
69 | 267002cd | bellard | #define CUDA_PACKET 1 |
70 | 267002cd | bellard | #define ERROR_PACKET 2 |
71 | 267002cd | bellard | #define TIMER_PACKET 3 |
72 | 267002cd | bellard | #define POWER_PACKET 4 |
73 | 267002cd | bellard | #define MACIIC_PACKET 5 |
74 | 267002cd | bellard | #define PMU_PACKET 6 |
75 | 267002cd | bellard | |
76 | 267002cd | bellard | |
77 | 267002cd | bellard | /* CUDA commands (2nd byte) */
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78 | 267002cd | bellard | #define CUDA_WARM_START 0x0 |
79 | 267002cd | bellard | #define CUDA_AUTOPOLL 0x1 |
80 | 267002cd | bellard | #define CUDA_GET_6805_ADDR 0x2 |
81 | 267002cd | bellard | #define CUDA_GET_TIME 0x3 |
82 | 267002cd | bellard | #define CUDA_GET_PRAM 0x7 |
83 | 267002cd | bellard | #define CUDA_SET_6805_ADDR 0x8 |
84 | 267002cd | bellard | #define CUDA_SET_TIME 0x9 |
85 | 267002cd | bellard | #define CUDA_POWERDOWN 0xa |
86 | 267002cd | bellard | #define CUDA_POWERUP_TIME 0xb |
87 | 267002cd | bellard | #define CUDA_SET_PRAM 0xc |
88 | 267002cd | bellard | #define CUDA_MS_RESET 0xd |
89 | 267002cd | bellard | #define CUDA_SEND_DFAC 0xe |
90 | 267002cd | bellard | #define CUDA_BATTERY_SWAP_SENSE 0x10 |
91 | 267002cd | bellard | #define CUDA_RESET_SYSTEM 0x11 |
92 | 267002cd | bellard | #define CUDA_SET_IPL 0x12 |
93 | 267002cd | bellard | #define CUDA_FILE_SERVER_FLAG 0x13 |
94 | 267002cd | bellard | #define CUDA_SET_AUTO_RATE 0x14 |
95 | 267002cd | bellard | #define CUDA_GET_AUTO_RATE 0x16 |
96 | 267002cd | bellard | #define CUDA_SET_DEVICE_LIST 0x19 |
97 | 267002cd | bellard | #define CUDA_GET_DEVICE_LIST 0x1a |
98 | 267002cd | bellard | #define CUDA_SET_ONE_SECOND_MODE 0x1b |
99 | 267002cd | bellard | #define CUDA_SET_POWER_MESSAGES 0x21 |
100 | 267002cd | bellard | #define CUDA_GET_SET_IIC 0x22 |
101 | 267002cd | bellard | #define CUDA_WAKEUP 0x23 |
102 | 267002cd | bellard | #define CUDA_TIMER_TICKLE 0x24 |
103 | 267002cd | bellard | #define CUDA_COMBINED_FORMAT_IIC 0x25 |
104 | 267002cd | bellard | |
105 | 267002cd | bellard | #define CUDA_TIMER_FREQ (4700000 / 6) |
106 | e2733d20 | bellard | #define CUDA_ADB_POLL_FREQ 50 |
107 | 267002cd | bellard | |
108 | d7ce296f | bellard | /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
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109 | d7ce296f | bellard | #define RTC_OFFSET 2082844800 |
110 | d7ce296f | bellard | |
111 | 267002cd | bellard | typedef struct CUDATimer { |
112 | 5fafdf24 | ths | int index;
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113 | 61271e5c | bellard | uint16_t latch; |
114 | 267002cd | bellard | uint16_t counter_value; /* counter value at load time */
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115 | 267002cd | bellard | int64_t load_time; |
116 | 267002cd | bellard | int64_t next_irq_time; |
117 | 267002cd | bellard | QEMUTimer *timer; |
118 | 267002cd | bellard | } CUDATimer; |
119 | 267002cd | bellard | |
120 | 267002cd | bellard | typedef struct CUDAState { |
121 | 23c5e4ca | Avi Kivity | MemoryRegion mem; |
122 | 267002cd | bellard | /* cuda registers */
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123 | 267002cd | bellard | uint8_t b; /* B-side data */
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124 | 267002cd | bellard | uint8_t a; /* A-side data */
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125 | 267002cd | bellard | uint8_t dirb; /* B-side direction (1=output) */
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126 | 267002cd | bellard | uint8_t dira; /* A-side direction (1=output) */
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127 | 267002cd | bellard | uint8_t sr; /* Shift register */
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128 | 267002cd | bellard | uint8_t acr; /* Auxiliary control register */
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129 | 267002cd | bellard | uint8_t pcr; /* Peripheral control register */
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130 | 267002cd | bellard | uint8_t ifr; /* Interrupt flag register */
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131 | 267002cd | bellard | uint8_t ier; /* Interrupt enable register */
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132 | 267002cd | bellard | uint8_t anh; /* A-side data, no handshake */
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133 | 267002cd | bellard | |
134 | 267002cd | bellard | CUDATimer timers[2];
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135 | 3b46e624 | ths | |
136 | 5703c174 | aurel32 | uint32_t tick_offset; |
137 | 5703c174 | aurel32 | |
138 | 267002cd | bellard | uint8_t last_b; /* last value of B register */
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139 | 267002cd | bellard | uint8_t last_acr; /* last value of B register */
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140 | 3b46e624 | ths | |
141 | 267002cd | bellard | int data_in_size;
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142 | 267002cd | bellard | int data_in_index;
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143 | 267002cd | bellard | int data_out_index;
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144 | 267002cd | bellard | |
145 | d537cf6c | pbrook | qemu_irq irq; |
146 | 267002cd | bellard | uint8_t autopoll; |
147 | 267002cd | bellard | uint8_t data_in[128];
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148 | 267002cd | bellard | uint8_t data_out[16];
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149 | e2733d20 | bellard | QEMUTimer *adb_poll_timer; |
150 | 267002cd | bellard | } CUDAState; |
151 | 267002cd | bellard | |
152 | 267002cd | bellard | static CUDAState cuda_state;
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153 | 267002cd | bellard | ADBBusState adb_bus; |
154 | 267002cd | bellard | |
155 | 267002cd | bellard | static void cuda_update(CUDAState *s); |
156 | 5fafdf24 | ths | static void cuda_receive_packet_from_host(CUDAState *s, |
157 | 267002cd | bellard | const uint8_t *data, int len); |
158 | 5fafdf24 | ths | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
159 | 819e712b | bellard | int64_t current_time); |
160 | 267002cd | bellard | |
161 | 267002cd | bellard | static void cuda_update_irq(CUDAState *s) |
162 | 267002cd | bellard | { |
163 | 819e712b | bellard | if (s->ifr & s->ier & (SR_INT | T1_INT)) {
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164 | d537cf6c | pbrook | qemu_irq_raise(s->irq); |
165 | 267002cd | bellard | } else {
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166 | d537cf6c | pbrook | qemu_irq_lower(s->irq); |
167 | 267002cd | bellard | } |
168 | 267002cd | bellard | } |
169 | 267002cd | bellard | |
170 | 267002cd | bellard | static unsigned int get_counter(CUDATimer *s) |
171 | 267002cd | bellard | { |
172 | 267002cd | bellard | int64_t d; |
173 | 267002cd | bellard | unsigned int counter; |
174 | 267002cd | bellard | |
175 | 74475455 | Paolo Bonzini | d = muldiv64(qemu_get_clock_ns(vm_clock) - s->load_time, |
176 | 6ee093c9 | Juan Quintela | CUDA_TIMER_FREQ, get_ticks_per_sec()); |
177 | 61271e5c | bellard | if (s->index == 0) { |
178 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
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179 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
180 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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181 | 61271e5c | bellard | } else {
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182 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
183 | 5fafdf24 | ths | counter = (s->latch - counter) & 0xffff;
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184 | 61271e5c | bellard | } |
185 | 267002cd | bellard | } else {
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186 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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187 | 267002cd | bellard | } |
188 | 267002cd | bellard | return counter;
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189 | 267002cd | bellard | } |
190 | 267002cd | bellard | |
191 | 819e712b | bellard | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
192 | 267002cd | bellard | { |
193 | ea026b2f | blueswir1 | CUDA_DPRINTF("T%d.counter=%d\n", 1 + (ti->timer == NULL), val); |
194 | 74475455 | Paolo Bonzini | ti->load_time = qemu_get_clock_ns(vm_clock); |
195 | 819e712b | bellard | ti->counter_value = val; |
196 | 819e712b | bellard | cuda_timer_update(s, ti, ti->load_time); |
197 | 267002cd | bellard | } |
198 | 267002cd | bellard | |
199 | 267002cd | bellard | static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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200 | 267002cd | bellard | { |
201 | 61271e5c | bellard | int64_t d, next_time; |
202 | 61271e5c | bellard | unsigned int counter; |
203 | 61271e5c | bellard | |
204 | 267002cd | bellard | /* current counter value */
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205 | 5fafdf24 | ths | d = muldiv64(current_time - s->load_time, |
206 | 6ee093c9 | Juan Quintela | CUDA_TIMER_FREQ, get_ticks_per_sec()); |
207 | 61271e5c | bellard | /* the timer goes down from latch to -1 (period of latch + 2) */
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208 | 61271e5c | bellard | if (d <= (s->counter_value + 1)) { |
209 | 61271e5c | bellard | counter = (s->counter_value - d) & 0xffff;
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210 | 61271e5c | bellard | } else {
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211 | 61271e5c | bellard | counter = (d - (s->counter_value + 1)) % (s->latch + 2); |
212 | 5fafdf24 | ths | counter = (s->latch - counter) & 0xffff;
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213 | 61271e5c | bellard | } |
214 | 3b46e624 | ths | |
215 | 61271e5c | bellard | /* Note: we consider the irq is raised on 0 */
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216 | 61271e5c | bellard | if (counter == 0xffff) { |
217 | 61271e5c | bellard | next_time = d + s->latch + 1;
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218 | 61271e5c | bellard | } else if (counter == 0) { |
219 | 61271e5c | bellard | next_time = d + s->latch + 2;
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220 | 61271e5c | bellard | } else {
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221 | 61271e5c | bellard | next_time = d + counter; |
222 | 267002cd | bellard | } |
223 | ea026b2f | blueswir1 | CUDA_DPRINTF("latch=%d counter=%" PRId64 " delta_next=%" PRId64 "\n", |
224 | ea026b2f | blueswir1 | s->latch, d, next_time - d); |
225 | 6ee093c9 | Juan Quintela | next_time = muldiv64(next_time, get_ticks_per_sec(), CUDA_TIMER_FREQ) + |
226 | 267002cd | bellard | s->load_time; |
227 | 267002cd | bellard | if (next_time <= current_time)
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228 | 267002cd | bellard | next_time = current_time + 1;
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229 | 267002cd | bellard | return next_time;
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230 | 267002cd | bellard | } |
231 | 267002cd | bellard | |
232 | 5fafdf24 | ths | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
233 | 819e712b | bellard | int64_t current_time) |
234 | 819e712b | bellard | { |
235 | 819e712b | bellard | if (!ti->timer)
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236 | 819e712b | bellard | return;
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237 | 819e712b | bellard | if ((s->acr & T1MODE) != T1MODE_CONT) {
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238 | 819e712b | bellard | qemu_del_timer(ti->timer); |
239 | 819e712b | bellard | } else {
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240 | 819e712b | bellard | ti->next_irq_time = get_next_irq_time(ti, current_time); |
241 | 819e712b | bellard | qemu_mod_timer(ti->timer, ti->next_irq_time); |
242 | 819e712b | bellard | } |
243 | 819e712b | bellard | } |
244 | 819e712b | bellard | |
245 | 267002cd | bellard | static void cuda_timer1(void *opaque) |
246 | 267002cd | bellard | { |
247 | 267002cd | bellard | CUDAState *s = opaque; |
248 | 267002cd | bellard | CUDATimer *ti = &s->timers[0];
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249 | 267002cd | bellard | |
250 | 819e712b | bellard | cuda_timer_update(s, ti, ti->next_irq_time); |
251 | 267002cd | bellard | s->ifr |= T1_INT; |
252 | 267002cd | bellard | cuda_update_irq(s); |
253 | 267002cd | bellard | } |
254 | 267002cd | bellard | |
255 | c227f099 | Anthony Liguori | static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
256 | 267002cd | bellard | { |
257 | 267002cd | bellard | CUDAState *s = opaque; |
258 | 267002cd | bellard | uint32_t val; |
259 | 267002cd | bellard | |
260 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
261 | 267002cd | bellard | switch(addr) {
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262 | 267002cd | bellard | case 0: |
263 | 267002cd | bellard | val = s->b; |
264 | 267002cd | bellard | break;
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265 | 267002cd | bellard | case 1: |
266 | 267002cd | bellard | val = s->a; |
267 | 267002cd | bellard | break;
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268 | 267002cd | bellard | case 2: |
269 | 267002cd | bellard | val = s->dirb; |
270 | 267002cd | bellard | break;
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271 | 267002cd | bellard | case 3: |
272 | 267002cd | bellard | val = s->dira; |
273 | 267002cd | bellard | break;
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274 | 267002cd | bellard | case 4: |
275 | 267002cd | bellard | val = get_counter(&s->timers[0]) & 0xff; |
276 | 267002cd | bellard | s->ifr &= ~T1_INT; |
277 | 267002cd | bellard | cuda_update_irq(s); |
278 | 267002cd | bellard | break;
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279 | 267002cd | bellard | case 5: |
280 | 267002cd | bellard | val = get_counter(&s->timers[0]) >> 8; |
281 | 267002cd | bellard | cuda_update_irq(s); |
282 | 267002cd | bellard | break;
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283 | 267002cd | bellard | case 6: |
284 | 267002cd | bellard | val = s->timers[0].latch & 0xff; |
285 | 267002cd | bellard | break;
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286 | 267002cd | bellard | case 7: |
287 | 61271e5c | bellard | /* XXX: check this */
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288 | 267002cd | bellard | val = (s->timers[0].latch >> 8) & 0xff; |
289 | 267002cd | bellard | break;
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290 | 267002cd | bellard | case 8: |
291 | 267002cd | bellard | val = get_counter(&s->timers[1]) & 0xff; |
292 | 61271e5c | bellard | s->ifr &= ~T2_INT; |
293 | 267002cd | bellard | break;
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294 | 267002cd | bellard | case 9: |
295 | 267002cd | bellard | val = get_counter(&s->timers[1]) >> 8; |
296 | 267002cd | bellard | break;
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297 | 267002cd | bellard | case 10: |
298 | 819e712b | bellard | val = s->sr; |
299 | 819e712b | bellard | s->ifr &= ~SR_INT; |
300 | 819e712b | bellard | cuda_update_irq(s); |
301 | 267002cd | bellard | break;
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302 | 267002cd | bellard | case 11: |
303 | 267002cd | bellard | val = s->acr; |
304 | 267002cd | bellard | break;
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305 | 267002cd | bellard | case 12: |
306 | 267002cd | bellard | val = s->pcr; |
307 | 267002cd | bellard | break;
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308 | 267002cd | bellard | case 13: |
309 | 267002cd | bellard | val = s->ifr; |
310 | 5fafdf24 | ths | if (s->ifr & s->ier)
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311 | b7c7b181 | bellard | val |= 0x80;
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312 | 267002cd | bellard | break;
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313 | 267002cd | bellard | case 14: |
314 | b7c7b181 | bellard | val = s->ier | 0x80;
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315 | 267002cd | bellard | break;
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316 | 267002cd | bellard | default:
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317 | 267002cd | bellard | case 15: |
318 | 267002cd | bellard | val = s->anh; |
319 | 267002cd | bellard | break;
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320 | 267002cd | bellard | } |
321 | 3c83eb4f | Blue Swirl | if (addr != 13 || val != 0) { |
322 | ea026b2f | blueswir1 | CUDA_DPRINTF("read: reg=0x%x val=%02x\n", (int)addr, val); |
323 | 3c83eb4f | Blue Swirl | } |
324 | 3c83eb4f | Blue Swirl | |
325 | 267002cd | bellard | return val;
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326 | 267002cd | bellard | } |
327 | 267002cd | bellard | |
328 | c227f099 | Anthony Liguori | static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
329 | 267002cd | bellard | { |
330 | 267002cd | bellard | CUDAState *s = opaque; |
331 | 3b46e624 | ths | |
332 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
333 | ea026b2f | blueswir1 | CUDA_DPRINTF("write: reg=0x%x val=%02x\n", (int)addr, val); |
334 | 267002cd | bellard | |
335 | 267002cd | bellard | switch(addr) {
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336 | 267002cd | bellard | case 0: |
337 | 267002cd | bellard | s->b = val; |
338 | 267002cd | bellard | cuda_update(s); |
339 | 267002cd | bellard | break;
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340 | 267002cd | bellard | case 1: |
341 | 267002cd | bellard | s->a = val; |
342 | 267002cd | bellard | break;
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343 | 267002cd | bellard | case 2: |
344 | 267002cd | bellard | s->dirb = val; |
345 | 267002cd | bellard | break;
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346 | 267002cd | bellard | case 3: |
347 | 267002cd | bellard | s->dira = val; |
348 | 267002cd | bellard | break;
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349 | 267002cd | bellard | case 4: |
350 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
351 | 74475455 | Paolo Bonzini | cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
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352 | 267002cd | bellard | break;
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353 | 267002cd | bellard | case 5: |
354 | 61271e5c | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
355 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
356 | 61271e5c | bellard | set_counter(s, &s->timers[0], s->timers[0].latch); |
357 | 267002cd | bellard | break;
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358 | 267002cd | bellard | case 6: |
359 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
360 | 74475455 | Paolo Bonzini | cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
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361 | 267002cd | bellard | break;
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362 | 267002cd | bellard | case 7: |
363 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
364 | 61271e5c | bellard | s->ifr &= ~T1_INT; |
365 | 74475455 | Paolo Bonzini | cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
|
366 | 267002cd | bellard | break;
|
367 | 267002cd | bellard | case 8: |
368 | 61271e5c | bellard | s->timers[1].latch = val;
|
369 | 819e712b | bellard | set_counter(s, &s->timers[1], val);
|
370 | 267002cd | bellard | break;
|
371 | 267002cd | bellard | case 9: |
372 | 61271e5c | bellard | set_counter(s, &s->timers[1], (val << 8) | s->timers[1].latch); |
373 | 267002cd | bellard | break;
|
374 | 267002cd | bellard | case 10: |
375 | 267002cd | bellard | s->sr = val; |
376 | 267002cd | bellard | break;
|
377 | 267002cd | bellard | case 11: |
378 | 267002cd | bellard | s->acr = val; |
379 | 74475455 | Paolo Bonzini | cuda_timer_update(s, &s->timers[0], qemu_get_clock_ns(vm_clock));
|
380 | 267002cd | bellard | cuda_update(s); |
381 | 267002cd | bellard | break;
|
382 | 267002cd | bellard | case 12: |
383 | 267002cd | bellard | s->pcr = val; |
384 | 267002cd | bellard | break;
|
385 | 267002cd | bellard | case 13: |
386 | 267002cd | bellard | /* reset bits */
|
387 | 267002cd | bellard | s->ifr &= ~val; |
388 | 267002cd | bellard | cuda_update_irq(s); |
389 | 267002cd | bellard | break;
|
390 | 267002cd | bellard | case 14: |
391 | 267002cd | bellard | if (val & IER_SET) {
|
392 | 267002cd | bellard | /* set bits */
|
393 | 267002cd | bellard | s->ier |= val & 0x7f;
|
394 | 267002cd | bellard | } else {
|
395 | 267002cd | bellard | /* reset bits */
|
396 | 267002cd | bellard | s->ier &= ~val; |
397 | 267002cd | bellard | } |
398 | 267002cd | bellard | cuda_update_irq(s); |
399 | 267002cd | bellard | break;
|
400 | 267002cd | bellard | default:
|
401 | 267002cd | bellard | case 15: |
402 | 267002cd | bellard | s->anh = val; |
403 | 267002cd | bellard | break;
|
404 | 267002cd | bellard | } |
405 | 267002cd | bellard | } |
406 | 267002cd | bellard | |
407 | 267002cd | bellard | /* NOTE: TIP and TREQ are negated */
|
408 | 267002cd | bellard | static void cuda_update(CUDAState *s) |
409 | 267002cd | bellard | { |
410 | 819e712b | bellard | int packet_received, len;
|
411 | 819e712b | bellard | |
412 | 819e712b | bellard | packet_received = 0;
|
413 | 819e712b | bellard | if (!(s->b & TIP)) {
|
414 | 819e712b | bellard | /* transfer requested from host */
|
415 | 267002cd | bellard | |
416 | 819e712b | bellard | if (s->acr & SR_OUT) {
|
417 | 819e712b | bellard | /* data output */
|
418 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
419 | 819e712b | bellard | if (s->data_out_index < sizeof(s->data_out)) { |
420 | ea026b2f | blueswir1 | CUDA_DPRINTF("send: %02x\n", s->sr);
|
421 | 819e712b | bellard | s->data_out[s->data_out_index++] = s->sr; |
422 | 819e712b | bellard | s->ifr |= SR_INT; |
423 | 819e712b | bellard | cuda_update_irq(s); |
424 | 819e712b | bellard | } |
425 | 819e712b | bellard | } |
426 | 819e712b | bellard | } else {
|
427 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
428 | 819e712b | bellard | /* data input */
|
429 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
430 | 819e712b | bellard | s->sr = s->data_in[s->data_in_index++]; |
431 | ea026b2f | blueswir1 | CUDA_DPRINTF("recv: %02x\n", s->sr);
|
432 | 819e712b | bellard | /* indicate end of transfer */
|
433 | 819e712b | bellard | if (s->data_in_index >= s->data_in_size) {
|
434 | 819e712b | bellard | s->b = (s->b | TREQ); |
435 | 819e712b | bellard | } |
436 | 819e712b | bellard | s->ifr |= SR_INT; |
437 | 819e712b | bellard | cuda_update_irq(s); |
438 | 819e712b | bellard | } |
439 | 267002cd | bellard | } |
440 | 819e712b | bellard | } |
441 | 819e712b | bellard | } else {
|
442 | 819e712b | bellard | /* no transfer requested: handle sync case */
|
443 | 819e712b | bellard | if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
444 | 819e712b | bellard | /* update TREQ state each time TACK change state */
|
445 | 819e712b | bellard | if (s->b & TACK)
|
446 | 819e712b | bellard | s->b = (s->b | TREQ); |
447 | 819e712b | bellard | else
|
448 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
449 | 267002cd | bellard | s->ifr |= SR_INT; |
450 | 267002cd | bellard | cuda_update_irq(s); |
451 | 819e712b | bellard | } else {
|
452 | 819e712b | bellard | if (!(s->last_b & TIP)) {
|
453 | e91c8a77 | ths | /* handle end of host to cuda transfer */
|
454 | 819e712b | bellard | packet_received = (s->data_out_index > 0);
|
455 | e91c8a77 | ths | /* always an IRQ at the end of transfer */
|
456 | 819e712b | bellard | s->ifr |= SR_INT; |
457 | 819e712b | bellard | cuda_update_irq(s); |
458 | 819e712b | bellard | } |
459 | 819e712b | bellard | /* signal if there is data to read */
|
460 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
461 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
462 | 819e712b | bellard | } |
463 | 267002cd | bellard | } |
464 | 267002cd | bellard | } |
465 | 267002cd | bellard | |
466 | 267002cd | bellard | s->last_acr = s->acr; |
467 | 267002cd | bellard | s->last_b = s->b; |
468 | 819e712b | bellard | |
469 | 819e712b | bellard | /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
470 | 819e712b | bellard | recursively */
|
471 | 819e712b | bellard | if (packet_received) {
|
472 | 819e712b | bellard | len = s->data_out_index; |
473 | 819e712b | bellard | s->data_out_index = 0;
|
474 | 819e712b | bellard | cuda_receive_packet_from_host(s, s->data_out, len); |
475 | 819e712b | bellard | } |
476 | 267002cd | bellard | } |
477 | 267002cd | bellard | |
478 | 5fafdf24 | ths | static void cuda_send_packet_to_host(CUDAState *s, |
479 | 267002cd | bellard | const uint8_t *data, int len) |
480 | 267002cd | bellard | { |
481 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
482 | 819e712b | bellard | { |
483 | 819e712b | bellard | int i;
|
484 | 819e712b | bellard | printf("cuda_send_packet_to_host:\n");
|
485 | 819e712b | bellard | for(i = 0; i < len; i++) |
486 | 819e712b | bellard | printf(" %02x", data[i]);
|
487 | 819e712b | bellard | printf("\n");
|
488 | 819e712b | bellard | } |
489 | 819e712b | bellard | #endif
|
490 | 267002cd | bellard | memcpy(s->data_in, data, len); |
491 | 267002cd | bellard | s->data_in_size = len; |
492 | 267002cd | bellard | s->data_in_index = 0;
|
493 | 267002cd | bellard | cuda_update(s); |
494 | 267002cd | bellard | s->ifr |= SR_INT; |
495 | 267002cd | bellard | cuda_update_irq(s); |
496 | 267002cd | bellard | } |
497 | 267002cd | bellard | |
498 | 7db4eea6 | bellard | static void cuda_adb_poll(void *opaque) |
499 | e2733d20 | bellard | { |
500 | e2733d20 | bellard | CUDAState *s = opaque; |
501 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
502 | e2733d20 | bellard | int olen;
|
503 | e2733d20 | bellard | |
504 | e2733d20 | bellard | olen = adb_poll(&adb_bus, obuf + 2);
|
505 | e2733d20 | bellard | if (olen > 0) { |
506 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
507 | e2733d20 | bellard | obuf[1] = 0x40; /* polled data */ |
508 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
509 | e2733d20 | bellard | } |
510 | 5fafdf24 | ths | qemu_mod_timer(s->adb_poll_timer, |
511 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) + |
512 | 6ee093c9 | Juan Quintela | (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); |
513 | e2733d20 | bellard | } |
514 | e2733d20 | bellard | |
515 | 5fafdf24 | ths | static void cuda_receive_packet(CUDAState *s, |
516 | 267002cd | bellard | const uint8_t *data, int len) |
517 | 267002cd | bellard | { |
518 | 267002cd | bellard | uint8_t obuf[16];
|
519 | 5703c174 | aurel32 | int autopoll;
|
520 | 5703c174 | aurel32 | uint32_t ti; |
521 | 267002cd | bellard | |
522 | 267002cd | bellard | switch(data[0]) { |
523 | 267002cd | bellard | case CUDA_AUTOPOLL:
|
524 | e2733d20 | bellard | autopoll = (data[1] != 0); |
525 | e2733d20 | bellard | if (autopoll != s->autopoll) {
|
526 | e2733d20 | bellard | s->autopoll = autopoll; |
527 | e2733d20 | bellard | if (autopoll) {
|
528 | 5fafdf24 | ths | qemu_mod_timer(s->adb_poll_timer, |
529 | 74475455 | Paolo Bonzini | qemu_get_clock_ns(vm_clock) + |
530 | 6ee093c9 | Juan Quintela | (get_ticks_per_sec() / CUDA_ADB_POLL_FREQ)); |
531 | e2733d20 | bellard | } else {
|
532 | e2733d20 | bellard | qemu_del_timer(s->adb_poll_timer); |
533 | e2733d20 | bellard | } |
534 | e2733d20 | bellard | } |
535 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
536 | 267002cd | bellard | obuf[1] = data[1]; |
537 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
538 | 267002cd | bellard | break;
|
539 | dccfafc4 | bellard | case CUDA_SET_TIME:
|
540 | 5703c174 | aurel32 | ti = (((uint32_t)data[1]) << 24) + (((uint32_t)data[2]) << 16) + (((uint32_t)data[3]) << 8) + data[4]; |
541 | 74475455 | Paolo Bonzini | s->tick_offset = ti - (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec()); |
542 | 5703c174 | aurel32 | obuf[0] = CUDA_PACKET;
|
543 | 5703c174 | aurel32 | obuf[1] = 0; |
544 | 5703c174 | aurel32 | obuf[2] = 0; |
545 | 5703c174 | aurel32 | cuda_send_packet_to_host(s, obuf, 3);
|
546 | 5703c174 | aurel32 | break;
|
547 | 5703c174 | aurel32 | case CUDA_GET_TIME:
|
548 | 74475455 | Paolo Bonzini | ti = s->tick_offset + (qemu_get_clock_ns(vm_clock) / get_ticks_per_sec()); |
549 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
550 | 267002cd | bellard | obuf[1] = 0; |
551 | 267002cd | bellard | obuf[2] = 0; |
552 | 267002cd | bellard | obuf[3] = ti >> 24; |
553 | 267002cd | bellard | obuf[4] = ti >> 16; |
554 | 267002cd | bellard | obuf[5] = ti >> 8; |
555 | 267002cd | bellard | obuf[6] = ti;
|
556 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 7);
|
557 | 267002cd | bellard | break;
|
558 | 267002cd | bellard | case CUDA_FILE_SERVER_FLAG:
|
559 | 267002cd | bellard | case CUDA_SET_DEVICE_LIST:
|
560 | 267002cd | bellard | case CUDA_SET_AUTO_RATE:
|
561 | 267002cd | bellard | case CUDA_SET_POWER_MESSAGES:
|
562 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
563 | 267002cd | bellard | obuf[1] = 0; |
564 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
565 | 267002cd | bellard | break;
|
566 | d7ce296f | bellard | case CUDA_POWERDOWN:
|
567 | d7ce296f | bellard | obuf[0] = CUDA_PACKET;
|
568 | d7ce296f | bellard | obuf[1] = 0; |
569 | d7ce296f | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
570 | c76ee25d | aurel32 | qemu_system_shutdown_request(); |
571 | c76ee25d | aurel32 | break;
|
572 | 0686970f | j_mayer | case CUDA_RESET_SYSTEM:
|
573 | 0686970f | j_mayer | obuf[0] = CUDA_PACKET;
|
574 | 0686970f | j_mayer | obuf[1] = 0; |
575 | 0686970f | j_mayer | cuda_send_packet_to_host(s, obuf, 2);
|
576 | 0686970f | j_mayer | qemu_system_reset_request(); |
577 | 0686970f | j_mayer | break;
|
578 | 267002cd | bellard | default:
|
579 | 267002cd | bellard | break;
|
580 | 267002cd | bellard | } |
581 | 267002cd | bellard | } |
582 | 267002cd | bellard | |
583 | 5fafdf24 | ths | static void cuda_receive_packet_from_host(CUDAState *s, |
584 | 267002cd | bellard | const uint8_t *data, int len) |
585 | 267002cd | bellard | { |
586 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
587 | 819e712b | bellard | { |
588 | 819e712b | bellard | int i;
|
589 | cadae95f | bellard | printf("cuda_receive_packet_from_host:\n");
|
590 | 819e712b | bellard | for(i = 0; i < len; i++) |
591 | 819e712b | bellard | printf(" %02x", data[i]);
|
592 | 819e712b | bellard | printf("\n");
|
593 | 819e712b | bellard | } |
594 | 819e712b | bellard | #endif
|
595 | 267002cd | bellard | switch(data[0]) { |
596 | 267002cd | bellard | case ADB_PACKET:
|
597 | e2733d20 | bellard | { |
598 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
599 | e2733d20 | bellard | int olen;
|
600 | e2733d20 | bellard | olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
601 | 38f0b147 | bellard | if (olen > 0) { |
602 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
603 | e2733d20 | bellard | obuf[1] = 0x00; |
604 | e2733d20 | bellard | } else {
|
605 | 38f0b147 | bellard | /* error */
|
606 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
607 | 38f0b147 | bellard | obuf[1] = -olen;
|
608 | 38f0b147 | bellard | olen = 0;
|
609 | e2733d20 | bellard | } |
610 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
611 | e2733d20 | bellard | } |
612 | 267002cd | bellard | break;
|
613 | 267002cd | bellard | case CUDA_PACKET:
|
614 | 267002cd | bellard | cuda_receive_packet(s, data + 1, len - 1); |
615 | 267002cd | bellard | break;
|
616 | 267002cd | bellard | } |
617 | 267002cd | bellard | } |
618 | 267002cd | bellard | |
619 | c227f099 | Anthony Liguori | static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
620 | 267002cd | bellard | { |
621 | 267002cd | bellard | } |
622 | 267002cd | bellard | |
623 | c227f099 | Anthony Liguori | static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
624 | 267002cd | bellard | { |
625 | 267002cd | bellard | } |
626 | 267002cd | bellard | |
627 | c227f099 | Anthony Liguori | static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
628 | 267002cd | bellard | { |
629 | 267002cd | bellard | return 0; |
630 | 267002cd | bellard | } |
631 | 267002cd | bellard | |
632 | c227f099 | Anthony Liguori | static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
633 | 267002cd | bellard | { |
634 | 267002cd | bellard | return 0; |
635 | 267002cd | bellard | } |
636 | 267002cd | bellard | |
637 | a348f108 | Stefan Weil | static const MemoryRegionOps cuda_ops = { |
638 | ea0a7eb4 | Alexander Graf | .old_mmio = { |
639 | ea0a7eb4 | Alexander Graf | .write = { |
640 | ea0a7eb4 | Alexander Graf | cuda_writeb, |
641 | ea0a7eb4 | Alexander Graf | cuda_writew, |
642 | ea0a7eb4 | Alexander Graf | cuda_writel, |
643 | ea0a7eb4 | Alexander Graf | }, |
644 | ea0a7eb4 | Alexander Graf | .read = { |
645 | ea0a7eb4 | Alexander Graf | cuda_readb, |
646 | ea0a7eb4 | Alexander Graf | cuda_readw, |
647 | ea0a7eb4 | Alexander Graf | cuda_readl, |
648 | ea0a7eb4 | Alexander Graf | }, |
649 | ea0a7eb4 | Alexander Graf | }, |
650 | ea0a7eb4 | Alexander Graf | .endianness = DEVICE_NATIVE_ENDIAN, |
651 | 267002cd | bellard | }; |
652 | 267002cd | bellard | |
653 | c0a93a9e | Juan Quintela | static bool cuda_timer_exist(void *opaque, int version_id) |
654 | 9b64997f | blueswir1 | { |
655 | c0a93a9e | Juan Quintela | CUDATimer *s = opaque; |
656 | 9b64997f | blueswir1 | |
657 | c0a93a9e | Juan Quintela | return s->timer != NULL; |
658 | 9b64997f | blueswir1 | } |
659 | 9b64997f | blueswir1 | |
660 | c0a93a9e | Juan Quintela | static const VMStateDescription vmstate_cuda_timer = { |
661 | c0a93a9e | Juan Quintela | .name = "cuda_timer",
|
662 | c0a93a9e | Juan Quintela | .version_id = 0,
|
663 | c0a93a9e | Juan Quintela | .minimum_version_id = 0,
|
664 | c0a93a9e | Juan Quintela | .minimum_version_id_old = 0,
|
665 | c0a93a9e | Juan Quintela | .fields = (VMStateField[]) { |
666 | c0a93a9e | Juan Quintela | VMSTATE_UINT16(latch, CUDATimer), |
667 | c0a93a9e | Juan Quintela | VMSTATE_UINT16(counter_value, CUDATimer), |
668 | c0a93a9e | Juan Quintela | VMSTATE_INT64(load_time, CUDATimer), |
669 | c0a93a9e | Juan Quintela | VMSTATE_INT64(next_irq_time, CUDATimer), |
670 | c0a93a9e | Juan Quintela | VMSTATE_TIMER_TEST(timer, CUDATimer, cuda_timer_exist), |
671 | c0a93a9e | Juan Quintela | VMSTATE_END_OF_LIST() |
672 | c0a93a9e | Juan Quintela | } |
673 | c0a93a9e | Juan Quintela | }; |
674 | 9b64997f | blueswir1 | |
675 | c0a93a9e | Juan Quintela | static const VMStateDescription vmstate_cuda = { |
676 | c0a93a9e | Juan Quintela | .name = "cuda",
|
677 | c0a93a9e | Juan Quintela | .version_id = 1,
|
678 | c0a93a9e | Juan Quintela | .minimum_version_id = 1,
|
679 | c0a93a9e | Juan Quintela | .minimum_version_id_old = 1,
|
680 | c0a93a9e | Juan Quintela | .fields = (VMStateField[]) { |
681 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(a, CUDAState), |
682 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(b, CUDAState), |
683 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(dira, CUDAState), |
684 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(dirb, CUDAState), |
685 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(sr, CUDAState), |
686 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(acr, CUDAState), |
687 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(pcr, CUDAState), |
688 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(ifr, CUDAState), |
689 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(ier, CUDAState), |
690 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(anh, CUDAState), |
691 | c0a93a9e | Juan Quintela | VMSTATE_INT32(data_in_size, CUDAState), |
692 | c0a93a9e | Juan Quintela | VMSTATE_INT32(data_in_index, CUDAState), |
693 | c0a93a9e | Juan Quintela | VMSTATE_INT32(data_out_index, CUDAState), |
694 | c0a93a9e | Juan Quintela | VMSTATE_UINT8(autopoll, CUDAState), |
695 | c0a93a9e | Juan Quintela | VMSTATE_BUFFER(data_in, CUDAState), |
696 | c0a93a9e | Juan Quintela | VMSTATE_BUFFER(data_out, CUDAState), |
697 | c0a93a9e | Juan Quintela | VMSTATE_UINT32(tick_offset, CUDAState), |
698 | c0a93a9e | Juan Quintela | VMSTATE_STRUCT_ARRAY(timers, CUDAState, 2, 1, |
699 | c0a93a9e | Juan Quintela | vmstate_cuda_timer, CUDATimer), |
700 | c0a93a9e | Juan Quintela | VMSTATE_END_OF_LIST() |
701 | c0a93a9e | Juan Quintela | } |
702 | c0a93a9e | Juan Quintela | }; |
703 | 9b64997f | blueswir1 | |
704 | 6e6b7363 | blueswir1 | static void cuda_reset(void *opaque) |
705 | 6e6b7363 | blueswir1 | { |
706 | 6e6b7363 | blueswir1 | CUDAState *s = opaque; |
707 | 6e6b7363 | blueswir1 | |
708 | 6e6b7363 | blueswir1 | s->b = 0;
|
709 | 6e6b7363 | blueswir1 | s->a = 0;
|
710 | 6e6b7363 | blueswir1 | s->dirb = 0;
|
711 | 6e6b7363 | blueswir1 | s->dira = 0;
|
712 | 6e6b7363 | blueswir1 | s->sr = 0;
|
713 | 6e6b7363 | blueswir1 | s->acr = 0;
|
714 | 6e6b7363 | blueswir1 | s->pcr = 0;
|
715 | 6e6b7363 | blueswir1 | s->ifr = 0;
|
716 | 6e6b7363 | blueswir1 | s->ier = 0;
|
717 | 6e6b7363 | blueswir1 | // s->ier = T1_INT | SR_INT;
|
718 | 6e6b7363 | blueswir1 | s->anh = 0;
|
719 | 6e6b7363 | blueswir1 | s->data_in_size = 0;
|
720 | 6e6b7363 | blueswir1 | s->data_in_index = 0;
|
721 | 6e6b7363 | blueswir1 | s->data_out_index = 0;
|
722 | 6e6b7363 | blueswir1 | s->autopoll = 0;
|
723 | 6e6b7363 | blueswir1 | |
724 | 6e6b7363 | blueswir1 | s->timers[0].latch = 0xffff; |
725 | 6e6b7363 | blueswir1 | set_counter(s, &s->timers[0], 0xffff); |
726 | 6e6b7363 | blueswir1 | |
727 | 6e6b7363 | blueswir1 | s->timers[1].latch = 0; |
728 | 6e6b7363 | blueswir1 | set_counter(s, &s->timers[1], 0xffff); |
729 | 6e6b7363 | blueswir1 | } |
730 | 6e6b7363 | blueswir1 | |
731 | 23c5e4ca | Avi Kivity | void cuda_init (MemoryRegion **cuda_mem, qemu_irq irq)
|
732 | 267002cd | bellard | { |
733 | 5703c174 | aurel32 | struct tm tm;
|
734 | 267002cd | bellard | CUDAState *s = &cuda_state; |
735 | 267002cd | bellard | |
736 | 819e712b | bellard | s->irq = irq; |
737 | 819e712b | bellard | |
738 | 61271e5c | bellard | s->timers[0].index = 0; |
739 | 74475455 | Paolo Bonzini | s->timers[0].timer = qemu_new_timer_ns(vm_clock, cuda_timer1, s);
|
740 | 61271e5c | bellard | |
741 | 61271e5c | bellard | s->timers[1].index = 1; |
742 | e2733d20 | bellard | |
743 | 9c554c1c | aurel32 | qemu_get_timedate(&tm, 0);
|
744 | 9c554c1c | aurel32 | s->tick_offset = (uint32_t)mktimegm(&tm) + RTC_OFFSET; |
745 | 5703c174 | aurel32 | |
746 | 74475455 | Paolo Bonzini | s->adb_poll_timer = qemu_new_timer_ns(vm_clock, cuda_adb_poll, s); |
747 | ea0a7eb4 | Alexander Graf | memory_region_init_io(&s->mem, &cuda_ops, s, "cuda", 0x2000); |
748 | ea0a7eb4 | Alexander Graf | |
749 | 23c5e4ca | Avi Kivity | *cuda_mem = &s->mem; |
750 | c0a93a9e | Juan Quintela | vmstate_register(NULL, -1, &vmstate_cuda, s); |
751 | a08d4367 | Jan Kiszka | qemu_register_reset(cuda_reset, s); |
752 | 267002cd | bellard | } |