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tcg/arm: Replace qemu_ld32u (left over from previous commit)
Commit 86feb1c860dc38e9c89e787c5210e8191800385edid not change all occurrences of INDEX_op_qemu_ld32ufor tcg/arm.
Please note that I could not test this patch(I have currently no arm system available)....
tcg: Disambiguate qemu_ld32u with 32-bit and 64-bit outputs.
Some targets (e.g. Alpha and MIPS64) need to keep 32-bit operandssign-extended in 64-bit registers (regardless of the "real" signof the operand). For that, we need to be able to distinguishbetween a 32-bit load with a 32-bit result and a 32-bit load with...
tcg: Name the opcode enumeration.
Give the enumeration formed from tcg-opc.h a name: TCGOpcode.Use that enumeration type instead of "int" whereever appropriate.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: don't save/restore r7 in prologue/epilogue
There is no need to save r7, it is used to store the addressof the env structure and is not modified by GCC.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg/arm: fix load/store definitions for 32-bit targets
tcg/arm: use helpers for divu/remu
tcg/arm: implement andc op
tcg/arm: correctly save/restore registers in prologue/epilogue
Since commit 6113d6d3169393c323ac4c82d756a850145a5e7a QEMU crasheson ARM hosts. This is not a bug of this commit, but a latent bugrevealed by this commit.
The TCG code is called through a procedure call using the prologue...
Remove TLB from userspace
Remove TLB from userspace CPU structure.
Signed-off-by: Paul Brook <paul@codesourcery.com>
tcg/arm: accept immediate arguments for brcond/setcond
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Add a missing break
tcg/arm: implement setcond2
tcg/arm: implement setcond
tcg/arm: fix div2/divu2
When restoring register values, increase the stack register for skippedvalues.
ARM back-end: Use sxt[bh] instructions for ext{8, 6}s
This patch uses sxtb for ext8s_i32 and sxth for ext16s_i32 in ARM back-end.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Suppress some variants of English in comments
Replace surpress, supress by suppress.
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
ARM back-end: Fix encode_imm
the encode_imm function in tcg/arm/tcg-target.c lacks shift declaration.
Laurent
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
ARM back-end: Handle all possible immediates for ALU ops
this patch handles all possible constants for immediate operand of ALU ops.I'm not very satisfied by the implementation.
ARM back-end: Add TCG not
this patch:
- implements TCG not.
rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN
Signed-off-by: Juan Quintela <quintela@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
this patch improves the ARM back-end in the following way:
- use movw/movt to load immediate values for ARMv7-A- implement add/sub/and/or/xor with immediate (only 8-bit)
Userspace guest address offsetting
Re-implement GUEST_BASE support.Offset guest ddress space by default if the guest binary containsregions below the host mmap_min_addr.Implement support for i386, x86-64 and arm hosts.
Signed-off-by: Riku Voipio <riku.voipio@iki.fi>...
ARM host fixes
Minor TCG cleanups and warning fixes for ARM hosts.
tcg-arm: fix qemu_ld64
Emulating fldl on arm doesn't seem to work too well. It's the wayqemu_ld64 is translated to arm instructions.
tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0); tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);...
Fix 64-bit targets compilation on ARM host.
Only fix compilation, probably doesn't run.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5947 c046a42c-6fe2-441c-8c8c-71466251a162
arm: Don't potentially overwrite input registers in add2, sub2.
According to malc TCG will often genereate an add2/sub2/mul2 with lowhalf of the output in the same register as high half of one of theinputs, so account for that.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5847 c046a42c-6fe2-441c-8c8c-71466251a162
Don't rely on ARM tcg_out_goto() generating just a single insn.
Otherwise when tb_exit generates a jump beyond the pc-relative range,tcg_out_goto() spans two/three instructions and we load the tb returnvalue from a wrong address. This is #ifdefed out currently because...
Add some missing static and const qualifiers, reg_names only used if NDEBUG set
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5421 c046a42c-6fe2-441c-8c8c-71466251a162
Fix some warnings that would be generated by gcc -Wredundant-decls
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
Fix off-by-one unwinding error.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
Relax a constraint for qemu_ld64 on ARM host.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4567 c046a42c-6fe2-441c-8c8c-71466251a162
Fix a deadly typo, correct comments.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4566 c046a42c-6fe2-441c-8c8c-71466251a162
Fix ARM host TLB.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4564 c046a42c-6fe2-441c-8c8c-71466251a162
Comment non-obvious calculation. Don't clobber r3 in qemu_st64.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4548 c046a42c-6fe2-441c-8c8c-71466251a162
A branch insn must not overwrite the branch target before relocation.
When a branch to label is translated it generates a reloc that is filled inwhen the label is translated. However, when handling an exception andsearching for the pc we abort the translation early and we sometimes...
Fix qemu_ld/st for mem_index > 0 on arm host.
offsetof(CPUState, tlb_table[mem_index][0].addr_read) with mem_index > 0was larger than max immediate offset for ldr and str (12-bit) so insert anadditional insn to add the mem_index offset.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4542 c046a42c-6fe2-441c-8c8c-71466251a162
Fix 8-bit signed load/store and a typo.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4504 c046a42c-6fe2-441c-8c8c-71466251a162
Implement neg_i32, clean-up.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4503 c046a42c-6fe2-441c-8c8c-71466251a162
ARM host support for TCG targets.
Updated from previous version to use the tcg prologue/epilogue mechanism, may be slower than direct call.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4500 c046a42c-6fe2-441c-8c8c-71466251a162