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root / target-arm @ 168aa23b

Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.6 kB
cpu.h 42.1 kB
cpu64.c 3.6 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 7.5 kB
helper-a64.h 2 kB
helper.c 148.8 kB
helper.h 19 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 4.4 kB
kvm-stub.c 437 Bytes
kvm.c 10.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 4.2 kB
machine.c 7.9 kB
neon_helper.c 53.2 kB
op_addsub.h 1.8 kB
op_helper.c 9 kB
translate-a64.c 283.6 kB
translate.c 378.5 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
168aa23b 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 TLB invalidate ops

Implement the AArch64 TLB invalidate operations. This is
the full set of TLBI ops defined for a CPU which doesn't
implement EL2 or EL3.

Signed-off-by: Peter Maydell <>
0eef9d98 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 CurrentEL sysreg

Implement the CurrentEL sysreg.

Signed-off-by: Peter Maydell <>
Reviewed-by: Peter Crosthwaite <>
cd4da631 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 MIDR_EL1

Implement the AArch64 view of the MIDR system register
(for AArch64 it is a simple constant, unlike the complicated
mess that TI925 imposes on the 32-bit view).

Signed-off-by: Peter Maydell <>...
8af35c37 02/26/2014 07:20 pm Peter Maydell

target-arm: Implement AArch64 cache invalidate/clean ops

Implement all the AArch64 cache invalidate and clean ops
(which are all NOPs since QEMU doesn't emulate the cache).
The only remaining unimplemented cache op is DC ZVA.

Signed-off-by: Peter Maydell <>...
67ed771d 02/26/2014 07:20 pm Peter Maydell

target-arm: Fix raw read and write functions on AArch64 registers

The raw read and write functions were using the ARM_CP_64BIT flag in
ri->type to determine whether to treat the register's state field as
uint32_t or uint64_t; however AArch64 register info structs don't use...
7da845b0 02/26/2014 07:20 pm Peter Maydell

target-arm: A64: Make cache ID registers visible to AArch64

Make the cache ID system registers (CLIDR, CSSELR, CCSIDR, CTR)
visible to AArch64. These are mostly simple 64-bit extensions of the
existing 32 bit system registers and so can share reginfo definitions....
1da41cc1 02/26/2014 07:20 pm Christoffer Dall

arm: vgic device control api support

Support creating the ARM vgic device through the device control API and
setting the base address for the distributor and cpu interfaces in KVM
VMs using this API.

Because the older KVM_CREATE_IRQCHIP interface needs the irq chip to be...
c10f7fc3 02/26/2014 07:19 pm Peter Maydell

target-arm: Load correct access bits from ARMv5 level 2 page table descriptors

In ARMv5 level 2 page table descriptors, each 4K or 64K page is split into
four subpages, each of which can have different access permission settings,
which are specified by four two-bit fields in the l2 descriptor. A...
775fda92 02/26/2014 07:19 pm Peter Maydell

target-arm: Fix incorrect arithmetic constructing short-form PAR for ATS ops

Correct some obviously nonsensical bit manipulation spotted by Coverity
when constructing the short-form PAR value for ATS operations.

Signed-off-by: Peter Maydell <>...
60510aed 02/20/2014 12:35 pm Peter Maydell

target-arm: A64: Implement unprivileged load/store

Implement the unprivileged load and store instructions.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>

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