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1 | a541f297 | bellard | /*
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2 | e9df014c | j_mayer | * QEMU generic PowerPC hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 76a66253 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | a541f297 | bellard | */
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24 | 87ecb68b | pbrook | #include "hw.h" |
25 | 87ecb68b | pbrook | #include "ppc.h" |
26 | 87ecb68b | pbrook | #include "qemu-timer.h" |
27 | 87ecb68b | pbrook | #include "sysemu.h" |
28 | 87ecb68b | pbrook | #include "nvram.h" |
29 | 3b3fb322 | blueswir1 | #include "qemu-log.h" |
30 | ca20cf32 | Blue Swirl | #include "loader.h" |
31 | fc87e185 | Alexander Graf | #include "kvm.h" |
32 | fc87e185 | Alexander Graf | #include "kvm_ppc.h" |
33 | a541f297 | bellard | |
34 | e9df014c | j_mayer | //#define PPC_DEBUG_IRQ
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35 | 4b6d0a4c | j_mayer | //#define PPC_DEBUG_TB
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36 | e9df014c | j_mayer | |
37 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_IRQ
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38 | 93fcfe39 | aliguori | # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) |
39 | d12d51d5 | aliguori | #else
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40 | d12d51d5 | aliguori | # define LOG_IRQ(...) do { } while (0) |
41 | d12d51d5 | aliguori | #endif
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42 | d12d51d5 | aliguori | |
43 | d12d51d5 | aliguori | |
44 | d12d51d5 | aliguori | #ifdef PPC_DEBUG_TB
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45 | 93fcfe39 | aliguori | # define LOG_TB(...) qemu_log(__VA_ARGS__)
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46 | d12d51d5 | aliguori | #else
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47 | d12d51d5 | aliguori | # define LOG_TB(...) do { } while (0) |
48 | d12d51d5 | aliguori | #endif
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49 | d12d51d5 | aliguori | |
50 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env); |
51 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env); |
52 | dbdd2506 | j_mayer | |
53 | 00af685f | j_mayer | static void ppc_set_irq (CPUState *env, int n_IRQ, int level) |
54 | 47103572 | j_mayer | { |
55 | fc87e185 | Alexander Graf | unsigned int old_pending = env->pending_interrupts; |
56 | fc87e185 | Alexander Graf | |
57 | 47103572 | j_mayer | if (level) {
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58 | 47103572 | j_mayer | env->pending_interrupts |= 1 << n_IRQ;
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59 | 47103572 | j_mayer | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
60 | 47103572 | j_mayer | } else {
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61 | 47103572 | j_mayer | env->pending_interrupts &= ~(1 << n_IRQ);
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62 | 47103572 | j_mayer | if (env->pending_interrupts == 0) |
63 | 47103572 | j_mayer | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
64 | 47103572 | j_mayer | } |
65 | fc87e185 | Alexander Graf | |
66 | fc87e185 | Alexander Graf | if (old_pending != env->pending_interrupts) {
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67 | fc87e185 | Alexander Graf | #ifdef CONFIG_KVM
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68 | fc87e185 | Alexander Graf | kvmppc_set_interrupt(env, n_IRQ, level); |
69 | fc87e185 | Alexander Graf | #endif
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70 | fc87e185 | Alexander Graf | } |
71 | fc87e185 | Alexander Graf | |
72 | d12d51d5 | aliguori | LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32
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73 | aae9366a | j_mayer | "req %08x\n", __func__, env, n_IRQ, level,
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74 | a496775f | j_mayer | env->pending_interrupts, env->interrupt_request); |
75 | 47103572 | j_mayer | } |
76 | 47103572 | j_mayer | |
77 | e9df014c | j_mayer | /* PowerPC 6xx / 7xx internal IRQ controller */
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78 | e9df014c | j_mayer | static void ppc6xx_set_irq (void *opaque, int pin, int level) |
79 | d537cf6c | pbrook | { |
80 | e9df014c | j_mayer | CPUState *env = opaque; |
81 | e9df014c | j_mayer | int cur_level;
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82 | d537cf6c | pbrook | |
83 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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84 | a496775f | j_mayer | env, pin, level); |
85 | e9df014c | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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86 | e9df014c | j_mayer | /* Don't generate spurious events */
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87 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
88 | e9df014c | j_mayer | switch (pin) {
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89 | dbdd2506 | j_mayer | case PPC6xx_INPUT_TBEN:
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90 | dbdd2506 | j_mayer | /* Level sensitive - active high */
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91 | d12d51d5 | aliguori | LOG_IRQ("%s: %s the time base\n",
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92 | dbdd2506 | j_mayer | __func__, level ? "start" : "stop"); |
93 | dbdd2506 | j_mayer | if (level) {
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94 | dbdd2506 | j_mayer | cpu_ppc_tb_start(env); |
95 | dbdd2506 | j_mayer | } else {
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96 | dbdd2506 | j_mayer | cpu_ppc_tb_stop(env); |
97 | dbdd2506 | j_mayer | } |
98 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_INT:
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99 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
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100 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
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101 | a496775f | j_mayer | __func__, level); |
102 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
103 | e9df014c | j_mayer | break;
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104 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SMI:
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105 | e9df014c | j_mayer | /* Level sensitive - active high */
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106 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n",
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107 | a496775f | j_mayer | __func__, level); |
108 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_SMI, level); |
109 | e9df014c | j_mayer | break;
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110 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_MCP:
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111 | e9df014c | j_mayer | /* Negative edge sensitive */
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112 | e9df014c | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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113 | e9df014c | j_mayer | * 603/604/740/750: check HID0[EMCP]
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114 | e9df014c | j_mayer | */
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115 | e9df014c | j_mayer | if (cur_level == 1 && level == 0) { |
116 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
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117 | a496775f | j_mayer | __func__); |
118 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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119 | e9df014c | j_mayer | } |
120 | e9df014c | j_mayer | break;
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121 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_CKSTP_IN:
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122 | e9df014c | j_mayer | /* Level sensitive - active low */
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123 | e9df014c | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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124 | e63ecc6f | j_mayer | /* XXX: Note that the only way to restart the CPU is to reset it */
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125 | e9df014c | j_mayer | if (level) {
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126 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
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127 | e9df014c | j_mayer | env->halted = 1;
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128 | e9df014c | j_mayer | } |
129 | e9df014c | j_mayer | break;
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130 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_HRESET:
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131 | e9df014c | j_mayer | /* Level sensitive - active low */
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132 | e9df014c | j_mayer | if (level) {
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133 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
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134 | ef397e88 | j_mayer | env->interrupt_request |= CPU_INTERRUPT_EXITTB; |
135 | ef397e88 | j_mayer | /* XXX: TOFIX */
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136 | ef397e88 | j_mayer | #if 0
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137 | d84bda46 | Blue Swirl | cpu_reset(env);
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138 | ef397e88 | j_mayer | #else
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139 | ef397e88 | j_mayer | qemu_system_reset_request(); |
140 | e9df014c | j_mayer | #endif
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141 | e9df014c | j_mayer | } |
142 | e9df014c | j_mayer | break;
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143 | 24be5ae3 | j_mayer | case PPC6xx_INPUT_SRESET:
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144 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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145 | a496775f | j_mayer | __func__, level); |
146 | e9df014c | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
147 | e9df014c | j_mayer | break;
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148 | e9df014c | j_mayer | default:
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149 | e9df014c | j_mayer | /* Unknown pin - do nothing */
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150 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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151 | e9df014c | j_mayer | return;
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152 | e9df014c | j_mayer | } |
153 | e9df014c | j_mayer | if (level)
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154 | e9df014c | j_mayer | env->irq_input_state |= 1 << pin;
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155 | e9df014c | j_mayer | else
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156 | e9df014c | j_mayer | env->irq_input_state &= ~(1 << pin);
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157 | d537cf6c | pbrook | } |
158 | d537cf6c | pbrook | } |
159 | d537cf6c | pbrook | |
160 | e9df014c | j_mayer | void ppc6xx_irq_init (CPUState *env)
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161 | 47103572 | j_mayer | { |
162 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env,
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163 | 7b62a955 | j_mayer | PPC6xx_INPUT_NB); |
164 | 47103572 | j_mayer | } |
165 | 47103572 | j_mayer | |
166 | 00af685f | j_mayer | #if defined(TARGET_PPC64)
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167 | d0dfae6e | j_mayer | /* PowerPC 970 internal IRQ controller */
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168 | d0dfae6e | j_mayer | static void ppc970_set_irq (void *opaque, int pin, int level) |
169 | d0dfae6e | j_mayer | { |
170 | d0dfae6e | j_mayer | CPUState *env = opaque; |
171 | d0dfae6e | j_mayer | int cur_level;
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172 | d0dfae6e | j_mayer | |
173 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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174 | d0dfae6e | j_mayer | env, pin, level); |
175 | d0dfae6e | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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176 | d0dfae6e | j_mayer | /* Don't generate spurious events */
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177 | d0dfae6e | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
178 | d0dfae6e | j_mayer | switch (pin) {
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179 | d0dfae6e | j_mayer | case PPC970_INPUT_INT:
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180 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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181 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
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182 | d0dfae6e | j_mayer | __func__, level); |
183 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
184 | d0dfae6e | j_mayer | break;
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185 | d0dfae6e | j_mayer | case PPC970_INPUT_THINT:
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186 | d0dfae6e | j_mayer | /* Level sensitive - active high */
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187 | d12d51d5 | aliguori | LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__,
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188 | d0dfae6e | j_mayer | level); |
189 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_THERM, level); |
190 | d0dfae6e | j_mayer | break;
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191 | d0dfae6e | j_mayer | case PPC970_INPUT_MCP:
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192 | d0dfae6e | j_mayer | /* Negative edge sensitive */
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193 | d0dfae6e | j_mayer | /* XXX: TODO: actual reaction may depends on HID0 status
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194 | d0dfae6e | j_mayer | * 603/604/740/750: check HID0[EMCP]
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195 | d0dfae6e | j_mayer | */
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196 | d0dfae6e | j_mayer | if (cur_level == 1 && level == 0) { |
197 | d12d51d5 | aliguori | LOG_IRQ("%s: raise machine check state\n",
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198 | d0dfae6e | j_mayer | __func__); |
199 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_MCK, 1);
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200 | d0dfae6e | j_mayer | } |
201 | d0dfae6e | j_mayer | break;
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202 | d0dfae6e | j_mayer | case PPC970_INPUT_CKSTP:
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203 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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204 | d0dfae6e | j_mayer | /* XXX: TODO: relay the signal to CKSTP_OUT pin */
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205 | d0dfae6e | j_mayer | if (level) {
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206 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
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207 | d0dfae6e | j_mayer | env->halted = 1;
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208 | d0dfae6e | j_mayer | } else {
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209 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
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210 | d0dfae6e | j_mayer | env->halted = 0;
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211 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
212 | d0dfae6e | j_mayer | } |
213 | d0dfae6e | j_mayer | break;
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214 | d0dfae6e | j_mayer | case PPC970_INPUT_HRESET:
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215 | d0dfae6e | j_mayer | /* Level sensitive - active low */
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216 | d0dfae6e | j_mayer | if (level) {
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217 | d0dfae6e | j_mayer | #if 0 // XXX: TOFIX
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218 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the CPU\n", __func__);
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219 | d0dfae6e | j_mayer | cpu_reset(env);
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220 | d0dfae6e | j_mayer | #endif
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221 | d0dfae6e | j_mayer | } |
222 | d0dfae6e | j_mayer | break;
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223 | d0dfae6e | j_mayer | case PPC970_INPUT_SRESET:
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224 | d12d51d5 | aliguori | LOG_IRQ("%s: set the RESET IRQ state to %d\n",
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225 | d0dfae6e | j_mayer | __func__, level); |
226 | d0dfae6e | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_RESET, level); |
227 | d0dfae6e | j_mayer | break;
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228 | d0dfae6e | j_mayer | case PPC970_INPUT_TBEN:
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229 | d12d51d5 | aliguori | LOG_IRQ("%s: set the TBEN state to %d\n", __func__,
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230 | d0dfae6e | j_mayer | level); |
231 | d0dfae6e | j_mayer | /* XXX: TODO */
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232 | d0dfae6e | j_mayer | break;
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233 | d0dfae6e | j_mayer | default:
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234 | d0dfae6e | j_mayer | /* Unknown pin - do nothing */
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235 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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236 | d0dfae6e | j_mayer | return;
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237 | d0dfae6e | j_mayer | } |
238 | d0dfae6e | j_mayer | if (level)
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239 | d0dfae6e | j_mayer | env->irq_input_state |= 1 << pin;
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240 | d0dfae6e | j_mayer | else
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241 | d0dfae6e | j_mayer | env->irq_input_state &= ~(1 << pin);
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242 | d0dfae6e | j_mayer | } |
243 | d0dfae6e | j_mayer | } |
244 | d0dfae6e | j_mayer | |
245 | d0dfae6e | j_mayer | void ppc970_irq_init (CPUState *env)
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246 | d0dfae6e | j_mayer | { |
247 | 7b62a955 | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env,
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248 | 7b62a955 | j_mayer | PPC970_INPUT_NB); |
249 | d0dfae6e | j_mayer | } |
250 | 9d52e907 | David Gibson | |
251 | 9d52e907 | David Gibson | /* POWER7 internal IRQ controller */
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252 | 9d52e907 | David Gibson | static void power7_set_irq (void *opaque, int pin, int level) |
253 | 9d52e907 | David Gibson | { |
254 | 9d52e907 | David Gibson | CPUState *env = opaque; |
255 | 9d52e907 | David Gibson | |
256 | 9d52e907 | David Gibson | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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257 | 9d52e907 | David Gibson | env, pin, level); |
258 | 9d52e907 | David Gibson | |
259 | 9d52e907 | David Gibson | switch (pin) {
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260 | 9d52e907 | David Gibson | case POWER7_INPUT_INT:
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261 | 9d52e907 | David Gibson | /* Level sensitive - active high */
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262 | 9d52e907 | David Gibson | LOG_IRQ("%s: set the external IRQ state to %d\n",
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263 | 9d52e907 | David Gibson | __func__, level); |
264 | 9d52e907 | David Gibson | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
265 | 9d52e907 | David Gibson | break;
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266 | 9d52e907 | David Gibson | default:
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267 | 9d52e907 | David Gibson | /* Unknown pin - do nothing */
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268 | 9d52e907 | David Gibson | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
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269 | 9d52e907 | David Gibson | return;
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270 | 9d52e907 | David Gibson | } |
271 | 9d52e907 | David Gibson | if (level) {
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272 | 9d52e907 | David Gibson | env->irq_input_state |= 1 << pin;
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273 | 9d52e907 | David Gibson | } else {
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274 | 9d52e907 | David Gibson | env->irq_input_state &= ~(1 << pin);
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275 | 9d52e907 | David Gibson | } |
276 | 9d52e907 | David Gibson | } |
277 | 9d52e907 | David Gibson | |
278 | 9d52e907 | David Gibson | void ppcPOWER7_irq_init (CPUState *env)
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279 | 9d52e907 | David Gibson | { |
280 | 9d52e907 | David Gibson | env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env,
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281 | 9d52e907 | David Gibson | POWER7_INPUT_NB); |
282 | 9d52e907 | David Gibson | } |
283 | 00af685f | j_mayer | #endif /* defined(TARGET_PPC64) */ |
284 | d0dfae6e | j_mayer | |
285 | 4e290a0b | j_mayer | /* PowerPC 40x internal IRQ controller */
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286 | 4e290a0b | j_mayer | static void ppc40x_set_irq (void *opaque, int pin, int level) |
287 | 24be5ae3 | j_mayer | { |
288 | 24be5ae3 | j_mayer | CPUState *env = opaque; |
289 | 24be5ae3 | j_mayer | int cur_level;
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290 | 24be5ae3 | j_mayer | |
291 | d12d51d5 | aliguori | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
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292 | 8ecc7913 | j_mayer | env, pin, level); |
293 | 24be5ae3 | j_mayer | cur_level = (env->irq_input_state >> pin) & 1;
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294 | 24be5ae3 | j_mayer | /* Don't generate spurious events */
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295 | 24be5ae3 | j_mayer | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
296 | 24be5ae3 | j_mayer | switch (pin) {
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297 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_SYS:
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298 | 8ecc7913 | j_mayer | if (level) {
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299 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC system\n",
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300 | 8ecc7913 | j_mayer | __func__); |
301 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
302 | 8ecc7913 | j_mayer | } |
303 | 8ecc7913 | j_mayer | break;
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304 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CHIP:
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305 | 8ecc7913 | j_mayer | if (level) {
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306 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC chip\n", __func__);
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307 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
308 | 8ecc7913 | j_mayer | } |
309 | 8ecc7913 | j_mayer | break;
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310 | 4e290a0b | j_mayer | case PPC40x_INPUT_RESET_CORE:
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311 | 24be5ae3 | j_mayer | /* XXX: TODO: update DBSR[MRR] */
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312 | 24be5ae3 | j_mayer | if (level) {
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313 | d12d51d5 | aliguori | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
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314 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
315 | 24be5ae3 | j_mayer | } |
316 | 24be5ae3 | j_mayer | break;
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317 | 4e290a0b | j_mayer | case PPC40x_INPUT_CINT:
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318 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
319 | d12d51d5 | aliguori | LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
320 | 8ecc7913 | j_mayer | __func__, level); |
321 | 4e290a0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
322 | 24be5ae3 | j_mayer | break;
|
323 | 4e290a0b | j_mayer | case PPC40x_INPUT_INT:
|
324 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
325 | d12d51d5 | aliguori | LOG_IRQ("%s: set the external IRQ state to %d\n",
|
326 | a496775f | j_mayer | __func__, level); |
327 | 24be5ae3 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
328 | 24be5ae3 | j_mayer | break;
|
329 | 4e290a0b | j_mayer | case PPC40x_INPUT_HALT:
|
330 | 24be5ae3 | j_mayer | /* Level sensitive - active low */
|
331 | 24be5ae3 | j_mayer | if (level) {
|
332 | d12d51d5 | aliguori | LOG_IRQ("%s: stop the CPU\n", __func__);
|
333 | 24be5ae3 | j_mayer | env->halted = 1;
|
334 | 24be5ae3 | j_mayer | } else {
|
335 | d12d51d5 | aliguori | LOG_IRQ("%s: restart the CPU\n", __func__);
|
336 | 24be5ae3 | j_mayer | env->halted = 0;
|
337 | 94ad5b00 | Paolo Bonzini | qemu_cpu_kick(env); |
338 | 24be5ae3 | j_mayer | } |
339 | 24be5ae3 | j_mayer | break;
|
340 | 4e290a0b | j_mayer | case PPC40x_INPUT_DEBUG:
|
341 | 24be5ae3 | j_mayer | /* Level sensitive - active high */
|
342 | d12d51d5 | aliguori | LOG_IRQ("%s: set the debug pin state to %d\n",
|
343 | a496775f | j_mayer | __func__, level); |
344 | a750fc0b | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
345 | 24be5ae3 | j_mayer | break;
|
346 | 24be5ae3 | j_mayer | default:
|
347 | 24be5ae3 | j_mayer | /* Unknown pin - do nothing */
|
348 | d12d51d5 | aliguori | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
349 | 24be5ae3 | j_mayer | return;
|
350 | 24be5ae3 | j_mayer | } |
351 | 24be5ae3 | j_mayer | if (level)
|
352 | 24be5ae3 | j_mayer | env->irq_input_state |= 1 << pin;
|
353 | 24be5ae3 | j_mayer | else
|
354 | 24be5ae3 | j_mayer | env->irq_input_state &= ~(1 << pin);
|
355 | 24be5ae3 | j_mayer | } |
356 | 24be5ae3 | j_mayer | } |
357 | 24be5ae3 | j_mayer | |
358 | 4e290a0b | j_mayer | void ppc40x_irq_init (CPUState *env)
|
359 | 24be5ae3 | j_mayer | { |
360 | 4e290a0b | j_mayer | env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq,
|
361 | 4e290a0b | j_mayer | env, PPC40x_INPUT_NB); |
362 | 24be5ae3 | j_mayer | } |
363 | 24be5ae3 | j_mayer | |
364 | 9fdc60bf | aurel32 | /* PowerPC E500 internal IRQ controller */
|
365 | 9fdc60bf | aurel32 | static void ppce500_set_irq (void *opaque, int pin, int level) |
366 | 9fdc60bf | aurel32 | { |
367 | 9fdc60bf | aurel32 | CPUState *env = opaque; |
368 | 9fdc60bf | aurel32 | int cur_level;
|
369 | 9fdc60bf | aurel32 | |
370 | 9fdc60bf | aurel32 | LOG_IRQ("%s: env %p pin %d level %d\n", __func__,
|
371 | 9fdc60bf | aurel32 | env, pin, level); |
372 | 9fdc60bf | aurel32 | cur_level = (env->irq_input_state >> pin) & 1;
|
373 | 9fdc60bf | aurel32 | /* Don't generate spurious events */
|
374 | 9fdc60bf | aurel32 | if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { |
375 | 9fdc60bf | aurel32 | switch (pin) {
|
376 | 9fdc60bf | aurel32 | case PPCE500_INPUT_MCK:
|
377 | 9fdc60bf | aurel32 | if (level) {
|
378 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC system\n",
|
379 | 9fdc60bf | aurel32 | __func__); |
380 | 9fdc60bf | aurel32 | qemu_system_reset_request(); |
381 | 9fdc60bf | aurel32 | } |
382 | 9fdc60bf | aurel32 | break;
|
383 | 9fdc60bf | aurel32 | case PPCE500_INPUT_RESET_CORE:
|
384 | 9fdc60bf | aurel32 | if (level) {
|
385 | 9fdc60bf | aurel32 | LOG_IRQ("%s: reset the PowerPC core\n", __func__);
|
386 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_MCK, level); |
387 | 9fdc60bf | aurel32 | } |
388 | 9fdc60bf | aurel32 | break;
|
389 | 9fdc60bf | aurel32 | case PPCE500_INPUT_CINT:
|
390 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
391 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the critical IRQ state to %d\n",
|
392 | 9fdc60bf | aurel32 | __func__, level); |
393 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_CEXT, level); |
394 | 9fdc60bf | aurel32 | break;
|
395 | 9fdc60bf | aurel32 | case PPCE500_INPUT_INT:
|
396 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
397 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the core IRQ state to %d\n",
|
398 | 9fdc60bf | aurel32 | __func__, level); |
399 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_EXT, level); |
400 | 9fdc60bf | aurel32 | break;
|
401 | 9fdc60bf | aurel32 | case PPCE500_INPUT_DEBUG:
|
402 | 9fdc60bf | aurel32 | /* Level sensitive - active high */
|
403 | 9fdc60bf | aurel32 | LOG_IRQ("%s: set the debug pin state to %d\n",
|
404 | 9fdc60bf | aurel32 | __func__, level); |
405 | 9fdc60bf | aurel32 | ppc_set_irq(env, PPC_INTERRUPT_DEBUG, level); |
406 | 9fdc60bf | aurel32 | break;
|
407 | 9fdc60bf | aurel32 | default:
|
408 | 9fdc60bf | aurel32 | /* Unknown pin - do nothing */
|
409 | 9fdc60bf | aurel32 | LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin);
|
410 | 9fdc60bf | aurel32 | return;
|
411 | 9fdc60bf | aurel32 | } |
412 | 9fdc60bf | aurel32 | if (level)
|
413 | 9fdc60bf | aurel32 | env->irq_input_state |= 1 << pin;
|
414 | 9fdc60bf | aurel32 | else
|
415 | 9fdc60bf | aurel32 | env->irq_input_state &= ~(1 << pin);
|
416 | 9fdc60bf | aurel32 | } |
417 | 9fdc60bf | aurel32 | } |
418 | 9fdc60bf | aurel32 | |
419 | 9fdc60bf | aurel32 | void ppce500_irq_init (CPUState *env)
|
420 | 9fdc60bf | aurel32 | { |
421 | 9fdc60bf | aurel32 | env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq,
|
422 | 9fdc60bf | aurel32 | env, PPCE500_INPUT_NB); |
423 | 9fdc60bf | aurel32 | } |
424 | 9fddaa0c | bellard | /*****************************************************************************/
|
425 | e9df014c | j_mayer | /* PowerPC time base and decrementer emulation */
|
426 | c227f099 | Anthony Liguori | struct ppc_tb_t {
|
427 | 9fddaa0c | bellard | /* Time base management */
|
428 | dbdd2506 | j_mayer | int64_t tb_offset; /* Compensation */
|
429 | dbdd2506 | j_mayer | int64_t atb_offset; /* Compensation */
|
430 | dbdd2506 | j_mayer | uint32_t tb_freq; /* TB frequency */
|
431 | 9fddaa0c | bellard | /* Decrementer management */
|
432 | dbdd2506 | j_mayer | uint64_t decr_next; /* Tick for next decr interrupt */
|
433 | dbdd2506 | j_mayer | uint32_t decr_freq; /* decrementer frequency */
|
434 | 9fddaa0c | bellard | struct QEMUTimer *decr_timer;
|
435 | 58a7d328 | j_mayer | /* Hypervisor decrementer management */
|
436 | 58a7d328 | j_mayer | uint64_t hdecr_next; /* Tick for next hdecr interrupt */
|
437 | 58a7d328 | j_mayer | struct QEMUTimer *hdecr_timer;
|
438 | 58a7d328 | j_mayer | uint64_t purr_load; |
439 | 58a7d328 | j_mayer | uint64_t purr_start; |
440 | 47103572 | j_mayer | void *opaque;
|
441 | 9fddaa0c | bellard | }; |
442 | 9fddaa0c | bellard | |
443 | c227f099 | Anthony Liguori | static inline uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
444 | 636aa200 | Blue Swirl | int64_t tb_offset) |
445 | 9fddaa0c | bellard | { |
446 | 9fddaa0c | bellard | /* TB time in tb periods */
|
447 | 6ee093c9 | Juan Quintela | return muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()) + tb_offset;
|
448 | 9fddaa0c | bellard | } |
449 | 9fddaa0c | bellard | |
450 | e3ea6529 | Alexander Graf | uint64_t cpu_ppc_load_tbl (CPUState *env) |
451 | 9fddaa0c | bellard | { |
452 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
453 | 9fddaa0c | bellard | uint64_t tb; |
454 | 9fddaa0c | bellard | |
455 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
456 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
457 | 9fddaa0c | bellard | |
458 | e3ea6529 | Alexander Graf | return tb;
|
459 | 9fddaa0c | bellard | } |
460 | 9fddaa0c | bellard | |
461 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_tbu(CPUState *env) |
462 | 9fddaa0c | bellard | { |
463 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
464 | 9fddaa0c | bellard | uint64_t tb; |
465 | 9fddaa0c | bellard | |
466 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
467 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
468 | 76a66253 | j_mayer | |
469 | 9fddaa0c | bellard | return tb >> 32; |
470 | 9fddaa0c | bellard | } |
471 | 9fddaa0c | bellard | |
472 | 8a84de23 | j_mayer | uint32_t cpu_ppc_load_tbu (CPUState *env) |
473 | 8a84de23 | j_mayer | { |
474 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
475 | 8a84de23 | j_mayer | } |
476 | 8a84de23 | j_mayer | |
477 | c227f099 | Anthony Liguori | static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, |
478 | 636aa200 | Blue Swirl | int64_t *tb_offsetp, uint64_t value) |
479 | 9fddaa0c | bellard | { |
480 | 6ee093c9 | Juan Quintela | *tb_offsetp = value - muldiv64(vmclk, tb_env->tb_freq, get_ticks_per_sec()); |
481 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", |
482 | aae9366a | j_mayer | __func__, value, *tb_offsetp); |
483 | 9fddaa0c | bellard | } |
484 | 9fddaa0c | bellard | |
485 | a062e36c | j_mayer | void cpu_ppc_store_tbl (CPUState *env, uint32_t value)
|
486 | a062e36c | j_mayer | { |
487 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
488 | a062e36c | j_mayer | uint64_t tb; |
489 | a062e36c | j_mayer | |
490 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
491 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
492 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
493 | dbdd2506 | j_mayer | &tb_env->tb_offset, tb | (uint64_t)value); |
494 | a062e36c | j_mayer | } |
495 | a062e36c | j_mayer | |
496 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_tbu(CPUState *env, uint32_t value) |
497 | 9fddaa0c | bellard | { |
498 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
499 | a062e36c | j_mayer | uint64_t tb; |
500 | 9fddaa0c | bellard | |
501 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->tb_offset); |
502 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
503 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
504 | dbdd2506 | j_mayer | &tb_env->tb_offset, ((uint64_t)value << 32) | tb);
|
505 | 9fddaa0c | bellard | } |
506 | 9fddaa0c | bellard | |
507 | 8a84de23 | j_mayer | void cpu_ppc_store_tbu (CPUState *env, uint32_t value)
|
508 | 8a84de23 | j_mayer | { |
509 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
510 | 8a84de23 | j_mayer | } |
511 | 8a84de23 | j_mayer | |
512 | b711de95 | Aurelien Jarno | uint64_t cpu_ppc_load_atbl (CPUState *env) |
513 | a062e36c | j_mayer | { |
514 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
515 | a062e36c | j_mayer | uint64_t tb; |
516 | a062e36c | j_mayer | |
517 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
518 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
519 | a062e36c | j_mayer | |
520 | b711de95 | Aurelien Jarno | return tb;
|
521 | a062e36c | j_mayer | } |
522 | a062e36c | j_mayer | |
523 | a062e36c | j_mayer | uint32_t cpu_ppc_load_atbu (CPUState *env) |
524 | a062e36c | j_mayer | { |
525 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
526 | a062e36c | j_mayer | uint64_t tb; |
527 | a062e36c | j_mayer | |
528 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
529 | d12d51d5 | aliguori | LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); |
530 | a062e36c | j_mayer | |
531 | a062e36c | j_mayer | return tb >> 32; |
532 | a062e36c | j_mayer | } |
533 | a062e36c | j_mayer | |
534 | a062e36c | j_mayer | void cpu_ppc_store_atbl (CPUState *env, uint32_t value)
|
535 | a062e36c | j_mayer | { |
536 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
537 | a062e36c | j_mayer | uint64_t tb; |
538 | a062e36c | j_mayer | |
539 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
540 | a062e36c | j_mayer | tb &= 0xFFFFFFFF00000000ULL;
|
541 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
542 | dbdd2506 | j_mayer | &tb_env->atb_offset, tb | (uint64_t)value); |
543 | a062e36c | j_mayer | } |
544 | a062e36c | j_mayer | |
545 | a062e36c | j_mayer | void cpu_ppc_store_atbu (CPUState *env, uint32_t value)
|
546 | 9fddaa0c | bellard | { |
547 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
548 | a062e36c | j_mayer | uint64_t tb; |
549 | 9fddaa0c | bellard | |
550 | 74475455 | Paolo Bonzini | tb = cpu_ppc_get_tb(tb_env, qemu_get_clock_ns(vm_clock), tb_env->atb_offset); |
551 | a062e36c | j_mayer | tb &= 0x00000000FFFFFFFFULL;
|
552 | 74475455 | Paolo Bonzini | cpu_ppc_store_tb(tb_env, qemu_get_clock_ns(vm_clock), |
553 | dbdd2506 | j_mayer | &tb_env->atb_offset, ((uint64_t)value << 32) | tb);
|
554 | dbdd2506 | j_mayer | } |
555 | dbdd2506 | j_mayer | |
556 | dbdd2506 | j_mayer | static void cpu_ppc_tb_stop (CPUState *env) |
557 | dbdd2506 | j_mayer | { |
558 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
559 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
560 | dbdd2506 | j_mayer | |
561 | dbdd2506 | j_mayer | /* If the time base is already frozen, do nothing */
|
562 | dbdd2506 | j_mayer | if (tb_env->tb_freq != 0) { |
563 | 74475455 | Paolo Bonzini | vmclk = qemu_get_clock_ns(vm_clock); |
564 | dbdd2506 | j_mayer | /* Get the time base */
|
565 | dbdd2506 | j_mayer | tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); |
566 | dbdd2506 | j_mayer | /* Get the alternate time base */
|
567 | dbdd2506 | j_mayer | atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); |
568 | dbdd2506 | j_mayer | /* Store the time base value (ie compute the current offset) */
|
569 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
570 | dbdd2506 | j_mayer | /* Store the alternate time base value (compute the current offset) */
|
571 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
572 | dbdd2506 | j_mayer | /* Set the time base frequency to zero */
|
573 | dbdd2506 | j_mayer | tb_env->tb_freq = 0;
|
574 | dbdd2506 | j_mayer | /* Now, the time bases are frozen to tb_offset / atb_offset value */
|
575 | dbdd2506 | j_mayer | } |
576 | dbdd2506 | j_mayer | } |
577 | dbdd2506 | j_mayer | |
578 | dbdd2506 | j_mayer | static void cpu_ppc_tb_start (CPUState *env) |
579 | dbdd2506 | j_mayer | { |
580 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
581 | dbdd2506 | j_mayer | uint64_t tb, atb, vmclk; |
582 | aae9366a | j_mayer | |
583 | dbdd2506 | j_mayer | /* If the time base is not frozen, do nothing */
|
584 | dbdd2506 | j_mayer | if (tb_env->tb_freq == 0) { |
585 | 74475455 | Paolo Bonzini | vmclk = qemu_get_clock_ns(vm_clock); |
586 | dbdd2506 | j_mayer | /* Get the time base from tb_offset */
|
587 | dbdd2506 | j_mayer | tb = tb_env->tb_offset; |
588 | dbdd2506 | j_mayer | /* Get the alternate time base from atb_offset */
|
589 | dbdd2506 | j_mayer | atb = tb_env->atb_offset; |
590 | dbdd2506 | j_mayer | /* Restore the tb frequency from the decrementer frequency */
|
591 | dbdd2506 | j_mayer | tb_env->tb_freq = tb_env->decr_freq; |
592 | dbdd2506 | j_mayer | /* Store the time base value */
|
593 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); |
594 | dbdd2506 | j_mayer | /* Store the alternate time base value */
|
595 | dbdd2506 | j_mayer | cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); |
596 | dbdd2506 | j_mayer | } |
597 | 9fddaa0c | bellard | } |
598 | 9fddaa0c | bellard | |
599 | 636aa200 | Blue Swirl | static inline uint32_t _cpu_ppc_load_decr(CPUState *env, uint64_t next) |
600 | 9fddaa0c | bellard | { |
601 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
602 | 9fddaa0c | bellard | uint32_t decr; |
603 | 4e588a4d | bellard | int64_t diff; |
604 | 9fddaa0c | bellard | |
605 | 74475455 | Paolo Bonzini | diff = next - qemu_get_clock_ns(vm_clock); |
606 | 4e588a4d | bellard | if (diff >= 0) |
607 | 6ee093c9 | Juan Quintela | decr = muldiv64(diff, tb_env->decr_freq, get_ticks_per_sec()); |
608 | 4e588a4d | bellard | else
|
609 | 6ee093c9 | Juan Quintela | decr = -muldiv64(-diff, tb_env->decr_freq, get_ticks_per_sec()); |
610 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 "\n", __func__, decr); |
611 | 76a66253 | j_mayer | |
612 | 9fddaa0c | bellard | return decr;
|
613 | 9fddaa0c | bellard | } |
614 | 9fddaa0c | bellard | |
615 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_decr (CPUState *env) |
616 | 58a7d328 | j_mayer | { |
617 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
618 | 58a7d328 | j_mayer | |
619 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->decr_next);
|
620 | 58a7d328 | j_mayer | } |
621 | 58a7d328 | j_mayer | |
622 | 58a7d328 | j_mayer | uint32_t cpu_ppc_load_hdecr (CPUState *env) |
623 | 58a7d328 | j_mayer | { |
624 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
625 | 58a7d328 | j_mayer | |
626 | f55e9d9a | Tristan Gingold | return _cpu_ppc_load_decr(env, tb_env->hdecr_next);
|
627 | 58a7d328 | j_mayer | } |
628 | 58a7d328 | j_mayer | |
629 | 58a7d328 | j_mayer | uint64_t cpu_ppc_load_purr (CPUState *env) |
630 | 58a7d328 | j_mayer | { |
631 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
632 | 58a7d328 | j_mayer | uint64_t diff; |
633 | 58a7d328 | j_mayer | |
634 | 74475455 | Paolo Bonzini | diff = qemu_get_clock_ns(vm_clock) - tb_env->purr_start; |
635 | b33c17e1 | j_mayer | |
636 | 6ee093c9 | Juan Quintela | return tb_env->purr_load + muldiv64(diff, tb_env->tb_freq, get_ticks_per_sec());
|
637 | 58a7d328 | j_mayer | } |
638 | 58a7d328 | j_mayer | |
639 | 9fddaa0c | bellard | /* When decrementer expires,
|
640 | 9fddaa0c | bellard | * all we need to do is generate or queue a CPU exception
|
641 | 9fddaa0c | bellard | */
|
642 | 636aa200 | Blue Swirl | static inline void cpu_ppc_decr_excp(CPUState *env) |
643 | 9fddaa0c | bellard | { |
644 | 9fddaa0c | bellard | /* Raise it */
|
645 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
646 | 47103572 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_DECR, 1);
|
647 | 9fddaa0c | bellard | } |
648 | 9fddaa0c | bellard | |
649 | 636aa200 | Blue Swirl | static inline void cpu_ppc_hdecr_excp(CPUState *env) |
650 | 58a7d328 | j_mayer | { |
651 | 58a7d328 | j_mayer | /* Raise it */
|
652 | d12d51d5 | aliguori | LOG_TB("raise decrementer exception\n");
|
653 | 58a7d328 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_HDECR, 1);
|
654 | 58a7d328 | j_mayer | } |
655 | 58a7d328 | j_mayer | |
656 | 58a7d328 | j_mayer | static void __cpu_ppc_store_decr (CPUState *env, uint64_t *nextp, |
657 | b33c17e1 | j_mayer | struct QEMUTimer *timer,
|
658 | b33c17e1 | j_mayer | void (*raise_excp)(CPUState *),
|
659 | b33c17e1 | j_mayer | uint32_t decr, uint32_t value, |
660 | b33c17e1 | j_mayer | int is_excp)
|
661 | 9fddaa0c | bellard | { |
662 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
663 | 9fddaa0c | bellard | uint64_t now, next; |
664 | 9fddaa0c | bellard | |
665 | d12d51d5 | aliguori | LOG_TB("%s: %08" PRIx32 " => %08" PRIx32 "\n", __func__, |
666 | aae9366a | j_mayer | decr, value); |
667 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
668 | 6ee093c9 | Juan Quintela | next = now + muldiv64(value, get_ticks_per_sec(), tb_env->decr_freq); |
669 | 9fddaa0c | bellard | if (is_excp)
|
670 | 58a7d328 | j_mayer | next += *nextp - now; |
671 | 9fddaa0c | bellard | if (next == now)
|
672 | 76a66253 | j_mayer | next++; |
673 | 58a7d328 | j_mayer | *nextp = next; |
674 | 9fddaa0c | bellard | /* Adjust timer */
|
675 | 58a7d328 | j_mayer | qemu_mod_timer(timer, next); |
676 | 9fddaa0c | bellard | /* If we set a negative value and the decrementer was positive,
|
677 | 9fddaa0c | bellard | * raise an exception.
|
678 | 9fddaa0c | bellard | */
|
679 | 9fddaa0c | bellard | if ((value & 0x80000000) && !(decr & 0x80000000)) |
680 | 58a7d328 | j_mayer | (*raise_excp)(env); |
681 | 58a7d328 | j_mayer | } |
682 | 58a7d328 | j_mayer | |
683 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_decr(CPUState *env, uint32_t decr, |
684 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
685 | 58a7d328 | j_mayer | { |
686 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
687 | 58a7d328 | j_mayer | |
688 | 58a7d328 | j_mayer | __cpu_ppc_store_decr(env, &tb_env->decr_next, tb_env->decr_timer, |
689 | 58a7d328 | j_mayer | &cpu_ppc_decr_excp, decr, value, is_excp); |
690 | 9fddaa0c | bellard | } |
691 | 9fddaa0c | bellard | |
692 | 9fddaa0c | bellard | void cpu_ppc_store_decr (CPUState *env, uint32_t value)
|
693 | 9fddaa0c | bellard | { |
694 | 9fddaa0c | bellard | _cpu_ppc_store_decr(env, cpu_ppc_load_decr(env), value, 0);
|
695 | 9fddaa0c | bellard | } |
696 | 9fddaa0c | bellard | |
697 | 9fddaa0c | bellard | static void cpu_ppc_decr_cb (void *opaque) |
698 | 9fddaa0c | bellard | { |
699 | 9fddaa0c | bellard | _cpu_ppc_store_decr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
700 | 9fddaa0c | bellard | } |
701 | 9fddaa0c | bellard | |
702 | 636aa200 | Blue Swirl | static inline void _cpu_ppc_store_hdecr(CPUState *env, uint32_t hdecr, |
703 | 636aa200 | Blue Swirl | uint32_t value, int is_excp)
|
704 | 58a7d328 | j_mayer | { |
705 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
706 | 58a7d328 | j_mayer | |
707 | b172c56a | j_mayer | if (tb_env->hdecr_timer != NULL) { |
708 | b172c56a | j_mayer | __cpu_ppc_store_decr(env, &tb_env->hdecr_next, tb_env->hdecr_timer, |
709 | b172c56a | j_mayer | &cpu_ppc_hdecr_excp, hdecr, value, is_excp); |
710 | b172c56a | j_mayer | } |
711 | 58a7d328 | j_mayer | } |
712 | 58a7d328 | j_mayer | |
713 | 58a7d328 | j_mayer | void cpu_ppc_store_hdecr (CPUState *env, uint32_t value)
|
714 | 58a7d328 | j_mayer | { |
715 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, cpu_ppc_load_hdecr(env), value, 0);
|
716 | 58a7d328 | j_mayer | } |
717 | 58a7d328 | j_mayer | |
718 | 58a7d328 | j_mayer | static void cpu_ppc_hdecr_cb (void *opaque) |
719 | 58a7d328 | j_mayer | { |
720 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); |
721 | 58a7d328 | j_mayer | } |
722 | 58a7d328 | j_mayer | |
723 | 58a7d328 | j_mayer | void cpu_ppc_store_purr (CPUState *env, uint64_t value)
|
724 | 58a7d328 | j_mayer | { |
725 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
726 | 58a7d328 | j_mayer | |
727 | 58a7d328 | j_mayer | tb_env->purr_load = value; |
728 | 74475455 | Paolo Bonzini | tb_env->purr_start = qemu_get_clock_ns(vm_clock); |
729 | 58a7d328 | j_mayer | } |
730 | 58a7d328 | j_mayer | |
731 | 8ecc7913 | j_mayer | static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) |
732 | 8ecc7913 | j_mayer | { |
733 | 8ecc7913 | j_mayer | CPUState *env = opaque; |
734 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
735 | 8ecc7913 | j_mayer | |
736 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
737 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
738 | 8ecc7913 | j_mayer | /* There is a bug in Linux 2.4 kernels:
|
739 | 8ecc7913 | j_mayer | * if a decrementer exception is pending when it enables msr_ee at startup,
|
740 | 8ecc7913 | j_mayer | * it's not ready to handle it...
|
741 | 8ecc7913 | j_mayer | */
|
742 | 8ecc7913 | j_mayer | _cpu_ppc_store_decr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
743 | 58a7d328 | j_mayer | _cpu_ppc_store_hdecr(env, 0xFFFFFFFF, 0xFFFFFFFF, 0); |
744 | 58a7d328 | j_mayer | cpu_ppc_store_purr(env, 0x0000000000000000ULL);
|
745 | 8ecc7913 | j_mayer | } |
746 | 8ecc7913 | j_mayer | |
747 | 9fddaa0c | bellard | /* Set up (once) timebase frequency (in Hz) */
|
748 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq) |
749 | 9fddaa0c | bellard | { |
750 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
751 | 9fddaa0c | bellard | |
752 | c227f099 | Anthony Liguori | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
753 | 9fddaa0c | bellard | env->tb_env = tb_env; |
754 | 8ecc7913 | j_mayer | /* Create new timer */
|
755 | 74475455 | Paolo Bonzini | tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_decr_cb, env); |
756 | b172c56a | j_mayer | if (0) { |
757 | b172c56a | j_mayer | /* XXX: find a suitable condition to enable the hypervisor decrementer
|
758 | b172c56a | j_mayer | */
|
759 | 74475455 | Paolo Bonzini | tb_env->hdecr_timer = qemu_new_timer_ns(vm_clock, &cpu_ppc_hdecr_cb, env); |
760 | b172c56a | j_mayer | } else {
|
761 | b172c56a | j_mayer | tb_env->hdecr_timer = NULL;
|
762 | b172c56a | j_mayer | } |
763 | 8ecc7913 | j_mayer | cpu_ppc_set_tb_clk(env, freq); |
764 | 9fddaa0c | bellard | |
765 | 8ecc7913 | j_mayer | return &cpu_ppc_set_tb_clk;
|
766 | 9fddaa0c | bellard | } |
767 | 9fddaa0c | bellard | |
768 | 76a66253 | j_mayer | /* Specific helpers for POWER & PowerPC 601 RTC */
|
769 | b1d8e52e | blueswir1 | #if 0
|
770 | b1d8e52e | blueswir1 | static clk_setup_cb cpu_ppc601_rtc_init (CPUState *env)
|
771 | 76a66253 | j_mayer | {
|
772 | 76a66253 | j_mayer | return cpu_ppc_tb_init(env, 7812500);
|
773 | 76a66253 | j_mayer | }
|
774 | b1d8e52e | blueswir1 | #endif
|
775 | 76a66253 | j_mayer | |
776 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcu (CPUState *env, uint32_t value)
|
777 | 8a84de23 | j_mayer | { |
778 | 8a84de23 | j_mayer | _cpu_ppc_store_tbu(env, value); |
779 | 8a84de23 | j_mayer | } |
780 | 76a66253 | j_mayer | |
781 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcu (CPUState *env) |
782 | 8a84de23 | j_mayer | { |
783 | 8a84de23 | j_mayer | return _cpu_ppc_load_tbu(env);
|
784 | 8a84de23 | j_mayer | } |
785 | 76a66253 | j_mayer | |
786 | 76a66253 | j_mayer | void cpu_ppc601_store_rtcl (CPUState *env, uint32_t value)
|
787 | 76a66253 | j_mayer | { |
788 | 76a66253 | j_mayer | cpu_ppc_store_tbl(env, value & 0x3FFFFF80);
|
789 | 76a66253 | j_mayer | } |
790 | 76a66253 | j_mayer | |
791 | 76a66253 | j_mayer | uint32_t cpu_ppc601_load_rtcl (CPUState *env) |
792 | 76a66253 | j_mayer | { |
793 | 76a66253 | j_mayer | return cpu_ppc_load_tbl(env) & 0x3FFFFF80; |
794 | 76a66253 | j_mayer | } |
795 | 76a66253 | j_mayer | |
796 | 636aaad7 | j_mayer | /*****************************************************************************/
|
797 | 76a66253 | j_mayer | /* Embedded PowerPC timers */
|
798 | 636aaad7 | j_mayer | |
799 | 636aaad7 | j_mayer | /* PIT, FIT & WDT */
|
800 | c227f099 | Anthony Liguori | typedef struct ppcemb_timer_t ppcemb_timer_t; |
801 | c227f099 | Anthony Liguori | struct ppcemb_timer_t {
|
802 | 636aaad7 | j_mayer | uint64_t pit_reload; /* PIT auto-reload value */
|
803 | 636aaad7 | j_mayer | uint64_t fit_next; /* Tick for next FIT interrupt */
|
804 | 636aaad7 | j_mayer | struct QEMUTimer *fit_timer;
|
805 | 636aaad7 | j_mayer | uint64_t wdt_next; /* Tick for next WDT interrupt */
|
806 | 636aaad7 | j_mayer | struct QEMUTimer *wdt_timer;
|
807 | d63cb48d | Edgar E. Iglesias | |
808 | d63cb48d | Edgar E. Iglesias | /* 405 have the PIT, 440 have a DECR. */
|
809 | d63cb48d | Edgar E. Iglesias | unsigned int decr_excp; |
810 | 636aaad7 | j_mayer | }; |
811 | 3b46e624 | ths | |
812 | 636aaad7 | j_mayer | /* Fixed interval timer */
|
813 | 636aaad7 | j_mayer | static void cpu_4xx_fit_cb (void *opaque) |
814 | 636aaad7 | j_mayer | { |
815 | 636aaad7 | j_mayer | CPUState *env; |
816 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
817 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
818 | 636aaad7 | j_mayer | uint64_t now, next; |
819 | 636aaad7 | j_mayer | |
820 | 636aaad7 | j_mayer | env = opaque; |
821 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
822 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
823 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
824 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { |
825 | 636aaad7 | j_mayer | case 0: |
826 | 636aaad7 | j_mayer | next = 1 << 9; |
827 | 636aaad7 | j_mayer | break;
|
828 | 636aaad7 | j_mayer | case 1: |
829 | 636aaad7 | j_mayer | next = 1 << 13; |
830 | 636aaad7 | j_mayer | break;
|
831 | 636aaad7 | j_mayer | case 2: |
832 | 636aaad7 | j_mayer | next = 1 << 17; |
833 | 636aaad7 | j_mayer | break;
|
834 | 636aaad7 | j_mayer | case 3: |
835 | 636aaad7 | j_mayer | next = 1 << 21; |
836 | 636aaad7 | j_mayer | break;
|
837 | 636aaad7 | j_mayer | default:
|
838 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
839 | 636aaad7 | j_mayer | return;
|
840 | 636aaad7 | j_mayer | } |
841 | 6ee093c9 | Juan Quintela | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->tb_freq); |
842 | 636aaad7 | j_mayer | if (next == now)
|
843 | 636aaad7 | j_mayer | next++; |
844 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->fit_timer, next); |
845 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 26; |
846 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) |
847 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_FIT, 1);
|
848 | 90e189ec | Blue Swirl | LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
849 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), |
850 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
851 | 636aaad7 | j_mayer | } |
852 | 636aaad7 | j_mayer | |
853 | 636aaad7 | j_mayer | /* Programmable interval timer */
|
854 | c227f099 | Anthony Liguori | static void start_stop_pit (CPUState *env, ppc_tb_t *tb_env, int is_excp) |
855 | 76a66253 | j_mayer | { |
856 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
857 | 636aaad7 | j_mayer | uint64_t now, next; |
858 | 636aaad7 | j_mayer | |
859 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
860 | 4b6d0a4c | j_mayer | if (ppcemb_timer->pit_reload <= 1 || |
861 | 4b6d0a4c | j_mayer | !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || |
862 | 4b6d0a4c | j_mayer | (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { |
863 | 4b6d0a4c | j_mayer | /* Stop PIT */
|
864 | d12d51d5 | aliguori | LOG_TB("%s: stop PIT\n", __func__);
|
865 | 4b6d0a4c | j_mayer | qemu_del_timer(tb_env->decr_timer); |
866 | 4b6d0a4c | j_mayer | } else {
|
867 | d12d51d5 | aliguori | LOG_TB("%s: start PIT %016" PRIx64 "\n", |
868 | 4b6d0a4c | j_mayer | __func__, ppcemb_timer->pit_reload); |
869 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
870 | 636aaad7 | j_mayer | next = now + muldiv64(ppcemb_timer->pit_reload, |
871 | 6ee093c9 | Juan Quintela | get_ticks_per_sec(), tb_env->decr_freq); |
872 | 4b6d0a4c | j_mayer | if (is_excp)
|
873 | 4b6d0a4c | j_mayer | next += tb_env->decr_next - now; |
874 | 636aaad7 | j_mayer | if (next == now)
|
875 | 636aaad7 | j_mayer | next++; |
876 | 636aaad7 | j_mayer | qemu_mod_timer(tb_env->decr_timer, next); |
877 | 636aaad7 | j_mayer | tb_env->decr_next = next; |
878 | 636aaad7 | j_mayer | } |
879 | 4b6d0a4c | j_mayer | } |
880 | 4b6d0a4c | j_mayer | |
881 | 4b6d0a4c | j_mayer | static void cpu_4xx_pit_cb (void *opaque) |
882 | 4b6d0a4c | j_mayer | { |
883 | 4b6d0a4c | j_mayer | CPUState *env; |
884 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
885 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
886 | 4b6d0a4c | j_mayer | |
887 | 4b6d0a4c | j_mayer | env = opaque; |
888 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
889 | 4b6d0a4c | j_mayer | ppcemb_timer = tb_env->opaque; |
890 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 27; |
891 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) |
892 | d63cb48d | Edgar E. Iglesias | ppc_set_irq(env, ppcemb_timer->decr_excp, 1);
|
893 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
894 | 90e189ec | Blue Swirl | LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " |
895 | 90e189ec | Blue Swirl | "%016" PRIx64 "\n", __func__, |
896 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), |
897 | 90e189ec | Blue Swirl | (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), |
898 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], |
899 | 90e189ec | Blue Swirl | ppcemb_timer->pit_reload); |
900 | 636aaad7 | j_mayer | } |
901 | 636aaad7 | j_mayer | |
902 | 636aaad7 | j_mayer | /* Watchdog timer */
|
903 | 636aaad7 | j_mayer | static void cpu_4xx_wdt_cb (void *opaque) |
904 | 636aaad7 | j_mayer | { |
905 | 636aaad7 | j_mayer | CPUState *env; |
906 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
907 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
908 | 636aaad7 | j_mayer | uint64_t now, next; |
909 | 636aaad7 | j_mayer | |
910 | 636aaad7 | j_mayer | env = opaque; |
911 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
912 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
913 | 74475455 | Paolo Bonzini | now = qemu_get_clock_ns(vm_clock); |
914 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { |
915 | 636aaad7 | j_mayer | case 0: |
916 | 636aaad7 | j_mayer | next = 1 << 17; |
917 | 636aaad7 | j_mayer | break;
|
918 | 636aaad7 | j_mayer | case 1: |
919 | 636aaad7 | j_mayer | next = 1 << 21; |
920 | 636aaad7 | j_mayer | break;
|
921 | 636aaad7 | j_mayer | case 2: |
922 | 636aaad7 | j_mayer | next = 1 << 25; |
923 | 636aaad7 | j_mayer | break;
|
924 | 636aaad7 | j_mayer | case 3: |
925 | 636aaad7 | j_mayer | next = 1 << 29; |
926 | 636aaad7 | j_mayer | break;
|
927 | 636aaad7 | j_mayer | default:
|
928 | 636aaad7 | j_mayer | /* Cannot occur, but makes gcc happy */
|
929 | 636aaad7 | j_mayer | return;
|
930 | 636aaad7 | j_mayer | } |
931 | 6ee093c9 | Juan Quintela | next = now + muldiv64(next, get_ticks_per_sec(), tb_env->decr_freq); |
932 | 636aaad7 | j_mayer | if (next == now)
|
933 | 636aaad7 | j_mayer | next++; |
934 | 90e189ec | Blue Swirl | LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, |
935 | 90e189ec | Blue Swirl | env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); |
936 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { |
937 | 636aaad7 | j_mayer | case 0x0: |
938 | 636aaad7 | j_mayer | case 0x1: |
939 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
940 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
941 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 31; |
942 | 636aaad7 | j_mayer | break;
|
943 | 636aaad7 | j_mayer | case 0x2: |
944 | 636aaad7 | j_mayer | qemu_mod_timer(ppcemb_timer->wdt_timer, next); |
945 | 636aaad7 | j_mayer | ppcemb_timer->wdt_next = next; |
946 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= 1 << 30; |
947 | 636aaad7 | j_mayer | if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) |
948 | 636aaad7 | j_mayer | ppc_set_irq(env, PPC_INTERRUPT_WDT, 1);
|
949 | 636aaad7 | j_mayer | break;
|
950 | 636aaad7 | j_mayer | case 0x3: |
951 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] &= ~0x30000000;
|
952 | 636aaad7 | j_mayer | env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000;
|
953 | 636aaad7 | j_mayer | switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { |
954 | 636aaad7 | j_mayer | case 0x0: |
955 | 636aaad7 | j_mayer | /* No reset */
|
956 | 636aaad7 | j_mayer | break;
|
957 | 636aaad7 | j_mayer | case 0x1: /* Core reset */ |
958 | 8ecc7913 | j_mayer | ppc40x_core_reset(env); |
959 | 8ecc7913 | j_mayer | break;
|
960 | 636aaad7 | j_mayer | case 0x2: /* Chip reset */ |
961 | 8ecc7913 | j_mayer | ppc40x_chip_reset(env); |
962 | 8ecc7913 | j_mayer | break;
|
963 | 636aaad7 | j_mayer | case 0x3: /* System reset */ |
964 | 8ecc7913 | j_mayer | ppc40x_system_reset(env); |
965 | 8ecc7913 | j_mayer | break;
|
966 | 636aaad7 | j_mayer | } |
967 | 636aaad7 | j_mayer | } |
968 | 76a66253 | j_mayer | } |
969 | 76a66253 | j_mayer | |
970 | 76a66253 | j_mayer | void store_40x_pit (CPUState *env, target_ulong val)
|
971 | 76a66253 | j_mayer | { |
972 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
973 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
974 | 636aaad7 | j_mayer | |
975 | 636aaad7 | j_mayer | tb_env = env->tb_env; |
976 | 636aaad7 | j_mayer | ppcemb_timer = tb_env->opaque; |
977 | 90e189ec | Blue Swirl | LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); |
978 | 636aaad7 | j_mayer | ppcemb_timer->pit_reload = val; |
979 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 0);
|
980 | 76a66253 | j_mayer | } |
981 | 76a66253 | j_mayer | |
982 | 636aaad7 | j_mayer | target_ulong load_40x_pit (CPUState *env) |
983 | 76a66253 | j_mayer | { |
984 | 636aaad7 | j_mayer | return cpu_ppc_load_decr(env);
|
985 | 76a66253 | j_mayer | } |
986 | 76a66253 | j_mayer | |
987 | 76a66253 | j_mayer | void store_booke_tsr (CPUState *env, target_ulong val)
|
988 | 76a66253 | j_mayer | { |
989 | d63cb48d | Edgar E. Iglesias | ppc_tb_t *tb_env = env->tb_env; |
990 | d63cb48d | Edgar E. Iglesias | ppcemb_timer_t *ppcemb_timer; |
991 | d63cb48d | Edgar E. Iglesias | |
992 | d63cb48d | Edgar E. Iglesias | ppcemb_timer = tb_env->opaque; |
993 | d63cb48d | Edgar E. Iglesias | |
994 | 90e189ec | Blue Swirl | LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val); |
995 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TSR] &= ~(val & 0xFC000000);
|
996 | 4b6d0a4c | j_mayer | if (val & 0x80000000) |
997 | d63cb48d | Edgar E. Iglesias | ppc_set_irq(env, ppcemb_timer->decr_excp, 0);
|
998 | 636aaad7 | j_mayer | } |
999 | 636aaad7 | j_mayer | |
1000 | 636aaad7 | j_mayer | void store_booke_tcr (CPUState *env, target_ulong val)
|
1001 | 636aaad7 | j_mayer | { |
1002 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
1003 | 4b6d0a4c | j_mayer | |
1004 | 4b6d0a4c | j_mayer | tb_env = env->tb_env; |
1005 | 90e189ec | Blue Swirl | LOG_TB("%s: val " TARGET_FMT_lx "\n", __func__, val); |
1006 | 4b6d0a4c | j_mayer | env->spr[SPR_40x_TCR] = val & 0xFFC00000;
|
1007 | 4b6d0a4c | j_mayer | start_stop_pit(env, tb_env, 1);
|
1008 | 8ecc7913 | j_mayer | cpu_4xx_wdt_cb(env); |
1009 | 636aaad7 | j_mayer | } |
1010 | 636aaad7 | j_mayer | |
1011 | 4b6d0a4c | j_mayer | static void ppc_emb_set_tb_clk (void *opaque, uint32_t freq) |
1012 | 4b6d0a4c | j_mayer | { |
1013 | 4b6d0a4c | j_mayer | CPUState *env = opaque; |
1014 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env = env->tb_env; |
1015 | 4b6d0a4c | j_mayer | |
1016 | d12d51d5 | aliguori | LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, |
1017 | aae9366a | j_mayer | freq); |
1018 | 4b6d0a4c | j_mayer | tb_env->tb_freq = freq; |
1019 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
1020 | 4b6d0a4c | j_mayer | /* XXX: we should also update all timers */
|
1021 | 4b6d0a4c | j_mayer | } |
1022 | 4b6d0a4c | j_mayer | |
1023 | d63cb48d | Edgar E. Iglesias | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq, |
1024 | d63cb48d | Edgar E. Iglesias | unsigned int decr_excp) |
1025 | 636aaad7 | j_mayer | { |
1026 | c227f099 | Anthony Liguori | ppc_tb_t *tb_env; |
1027 | c227f099 | Anthony Liguori | ppcemb_timer_t *ppcemb_timer; |
1028 | 636aaad7 | j_mayer | |
1029 | c227f099 | Anthony Liguori | tb_env = qemu_mallocz(sizeof(ppc_tb_t));
|
1030 | 8ecc7913 | j_mayer | env->tb_env = tb_env; |
1031 | c227f099 | Anthony Liguori | ppcemb_timer = qemu_mallocz(sizeof(ppcemb_timer_t));
|
1032 | 8ecc7913 | j_mayer | tb_env->tb_freq = freq; |
1033 | dbdd2506 | j_mayer | tb_env->decr_freq = freq; |
1034 | 636aaad7 | j_mayer | tb_env->opaque = ppcemb_timer; |
1035 | d12d51d5 | aliguori | LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); |
1036 | 636aaad7 | j_mayer | if (ppcemb_timer != NULL) { |
1037 | 636aaad7 | j_mayer | /* We use decr timer for PIT */
|
1038 | 74475455 | Paolo Bonzini | tb_env->decr_timer = qemu_new_timer_ns(vm_clock, &cpu_4xx_pit_cb, env); |
1039 | 636aaad7 | j_mayer | ppcemb_timer->fit_timer = |
1040 | 74475455 | Paolo Bonzini | qemu_new_timer_ns(vm_clock, &cpu_4xx_fit_cb, env); |
1041 | 636aaad7 | j_mayer | ppcemb_timer->wdt_timer = |
1042 | 74475455 | Paolo Bonzini | qemu_new_timer_ns(vm_clock, &cpu_4xx_wdt_cb, env); |
1043 | d63cb48d | Edgar E. Iglesias | ppcemb_timer->decr_excp = decr_excp; |
1044 | 636aaad7 | j_mayer | } |
1045 | 8ecc7913 | j_mayer | |
1046 | 4b6d0a4c | j_mayer | return &ppc_emb_set_tb_clk;
|
1047 | 76a66253 | j_mayer | } |
1048 | 76a66253 | j_mayer | |
1049 | 2e719ba3 | j_mayer | /*****************************************************************************/
|
1050 | 2e719ba3 | j_mayer | /* Embedded PowerPC Device Control Registers */
|
1051 | c227f099 | Anthony Liguori | typedef struct ppc_dcrn_t ppc_dcrn_t; |
1052 | c227f099 | Anthony Liguori | struct ppc_dcrn_t {
|
1053 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read; |
1054 | 2e719ba3 | j_mayer | dcr_write_cb dcr_write; |
1055 | 2e719ba3 | j_mayer | void *opaque;
|
1056 | 2e719ba3 | j_mayer | }; |
1057 | 2e719ba3 | j_mayer | |
1058 | a750fc0b | j_mayer | /* XXX: on 460, DCR addresses are 32 bits wide,
|
1059 | a750fc0b | j_mayer | * using DCRIPR to get the 22 upper bits of the DCR address
|
1060 | a750fc0b | j_mayer | */
|
1061 | 2e719ba3 | j_mayer | #define DCRN_NB 1024 |
1062 | c227f099 | Anthony Liguori | struct ppc_dcr_t {
|
1063 | c227f099 | Anthony Liguori | ppc_dcrn_t dcrn[DCRN_NB]; |
1064 | 2e719ba3 | j_mayer | int (*read_error)(int dcrn); |
1065 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn); |
1066 | 2e719ba3 | j_mayer | }; |
1067 | 2e719ba3 | j_mayer | |
1068 | 73b01960 | Alexander Graf | int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) |
1069 | 2e719ba3 | j_mayer | { |
1070 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1071 | 2e719ba3 | j_mayer | |
1072 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1073 | 2e719ba3 | j_mayer | goto error;
|
1074 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1075 | 2e719ba3 | j_mayer | if (dcr->dcr_read == NULL) |
1076 | 2e719ba3 | j_mayer | goto error;
|
1077 | 2e719ba3 | j_mayer | *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); |
1078 | 2e719ba3 | j_mayer | |
1079 | 2e719ba3 | j_mayer | return 0; |
1080 | 2e719ba3 | j_mayer | |
1081 | 2e719ba3 | j_mayer | error:
|
1082 | 2e719ba3 | j_mayer | if (dcr_env->read_error != NULL) |
1083 | 2e719ba3 | j_mayer | return (*dcr_env->read_error)(dcrn);
|
1084 | 2e719ba3 | j_mayer | |
1085 | 2e719ba3 | j_mayer | return -1; |
1086 | 2e719ba3 | j_mayer | } |
1087 | 2e719ba3 | j_mayer | |
1088 | 73b01960 | Alexander Graf | int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) |
1089 | 2e719ba3 | j_mayer | { |
1090 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1091 | 2e719ba3 | j_mayer | |
1092 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1093 | 2e719ba3 | j_mayer | goto error;
|
1094 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1095 | 2e719ba3 | j_mayer | if (dcr->dcr_write == NULL) |
1096 | 2e719ba3 | j_mayer | goto error;
|
1097 | 2e719ba3 | j_mayer | (*dcr->dcr_write)(dcr->opaque, dcrn, val); |
1098 | 2e719ba3 | j_mayer | |
1099 | 2e719ba3 | j_mayer | return 0; |
1100 | 2e719ba3 | j_mayer | |
1101 | 2e719ba3 | j_mayer | error:
|
1102 | 2e719ba3 | j_mayer | if (dcr_env->write_error != NULL) |
1103 | 2e719ba3 | j_mayer | return (*dcr_env->write_error)(dcrn);
|
1104 | 2e719ba3 | j_mayer | |
1105 | 2e719ba3 | j_mayer | return -1; |
1106 | 2e719ba3 | j_mayer | } |
1107 | 2e719ba3 | j_mayer | |
1108 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1109 | 2e719ba3 | j_mayer | dcr_read_cb dcr_read, dcr_write_cb dcr_write) |
1110 | 2e719ba3 | j_mayer | { |
1111 | c227f099 | Anthony Liguori | ppc_dcr_t *dcr_env; |
1112 | c227f099 | Anthony Liguori | ppc_dcrn_t *dcr; |
1113 | 2e719ba3 | j_mayer | |
1114 | 2e719ba3 | j_mayer | dcr_env = env->dcr_env; |
1115 | 2e719ba3 | j_mayer | if (dcr_env == NULL) |
1116 | 2e719ba3 | j_mayer | return -1; |
1117 | 2e719ba3 | j_mayer | if (dcrn < 0 || dcrn >= DCRN_NB) |
1118 | 2e719ba3 | j_mayer | return -1; |
1119 | 2e719ba3 | j_mayer | dcr = &dcr_env->dcrn[dcrn]; |
1120 | 2e719ba3 | j_mayer | if (dcr->opaque != NULL || |
1121 | 2e719ba3 | j_mayer | dcr->dcr_read != NULL ||
|
1122 | 2e719ba3 | j_mayer | dcr->dcr_write != NULL)
|
1123 | 2e719ba3 | j_mayer | return -1; |
1124 | 2e719ba3 | j_mayer | dcr->opaque = opaque; |
1125 | 2e719ba3 | j_mayer | dcr->dcr_read = dcr_read; |
1126 | 2e719ba3 | j_mayer | dcr->dcr_write = dcr_write; |
1127 | 2e719ba3 | j_mayer | |
1128 | 2e719ba3 | j_mayer | return 0; |
1129 | 2e719ba3 | j_mayer | } |
1130 | 2e719ba3 | j_mayer | |
1131 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*read_error)(int dcrn), |
1132 | 2e719ba3 | j_mayer | int (*write_error)(int dcrn)) |
1133 | 2e719ba3 | j_mayer | { |
1134 | c227f099 | Anthony Liguori | ppc_dcr_t *dcr_env; |
1135 | 2e719ba3 | j_mayer | |
1136 | c227f099 | Anthony Liguori | dcr_env = qemu_mallocz(sizeof(ppc_dcr_t));
|
1137 | 2e719ba3 | j_mayer | dcr_env->read_error = read_error; |
1138 | 2e719ba3 | j_mayer | dcr_env->write_error = write_error; |
1139 | 2e719ba3 | j_mayer | env->dcr_env = dcr_env; |
1140 | 2e719ba3 | j_mayer | |
1141 | 2e719ba3 | j_mayer | return 0; |
1142 | 2e719ba3 | j_mayer | } |
1143 | 2e719ba3 | j_mayer | |
1144 | 64201201 | bellard | /*****************************************************************************/
|
1145 | 64201201 | bellard | /* Debug port */
|
1146 | fd0bbb12 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) |
1147 | 64201201 | bellard | { |
1148 | 64201201 | bellard | addr &= 0xF;
|
1149 | 64201201 | bellard | switch (addr) {
|
1150 | 64201201 | bellard | case 0: |
1151 | 64201201 | bellard | printf("%c", val);
|
1152 | 64201201 | bellard | break;
|
1153 | 64201201 | bellard | case 1: |
1154 | 64201201 | bellard | printf("\n");
|
1155 | 64201201 | bellard | fflush(stdout); |
1156 | 64201201 | bellard | break;
|
1157 | 64201201 | bellard | case 2: |
1158 | aae9366a | j_mayer | printf("Set loglevel to %04" PRIx32 "\n", val); |
1159 | fd0bbb12 | bellard | cpu_set_log(val | 0x100);
|
1160 | 64201201 | bellard | break;
|
1161 | 64201201 | bellard | } |
1162 | 64201201 | bellard | } |
1163 | 64201201 | bellard | |
1164 | 64201201 | bellard | /*****************************************************************************/
|
1165 | 64201201 | bellard | /* NVRAM helpers */
|
1166 | c227f099 | Anthony Liguori | static inline uint32_t nvram_read (nvram_t *nvram, uint32_t addr) |
1167 | 64201201 | bellard | { |
1168 | 3cbee15b | j_mayer | return (*nvram->read_fn)(nvram->opaque, addr);;
|
1169 | 64201201 | bellard | } |
1170 | 64201201 | bellard | |
1171 | c227f099 | Anthony Liguori | static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) |
1172 | 64201201 | bellard | { |
1173 | 3cbee15b | j_mayer | (*nvram->write_fn)(nvram->opaque, addr, val); |
1174 | 64201201 | bellard | } |
1175 | 64201201 | bellard | |
1176 | c227f099 | Anthony Liguori | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value)
|
1177 | 64201201 | bellard | { |
1178 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value); |
1179 | 64201201 | bellard | } |
1180 | 64201201 | bellard | |
1181 | c227f099 | Anthony Liguori | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) |
1182 | 3cbee15b | j_mayer | { |
1183 | 3cbee15b | j_mayer | return nvram_read(nvram, addr);
|
1184 | 3cbee15b | j_mayer | } |
1185 | 3cbee15b | j_mayer | |
1186 | c227f099 | Anthony Liguori | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value)
|
1187 | 3cbee15b | j_mayer | { |
1188 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 8);
|
1189 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, value & 0xFF); |
1190 | 3cbee15b | j_mayer | } |
1191 | 3cbee15b | j_mayer | |
1192 | c227f099 | Anthony Liguori | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) |
1193 | 64201201 | bellard | { |
1194 | 64201201 | bellard | uint16_t tmp; |
1195 | 64201201 | bellard | |
1196 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 8;
|
1197 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1);
|
1198 | 3cbee15b | j_mayer | |
1199 | 64201201 | bellard | return tmp;
|
1200 | 64201201 | bellard | } |
1201 | 64201201 | bellard | |
1202 | c227f099 | Anthony Liguori | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value)
|
1203 | 64201201 | bellard | { |
1204 | 3cbee15b | j_mayer | nvram_write(nvram, addr, value >> 24);
|
1205 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); |
1206 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 2, (value >> 8) & 0xFF); |
1207 | 3cbee15b | j_mayer | nvram_write(nvram, addr + 3, value & 0xFF); |
1208 | 64201201 | bellard | } |
1209 | 64201201 | bellard | |
1210 | c227f099 | Anthony Liguori | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) |
1211 | 64201201 | bellard | { |
1212 | 64201201 | bellard | uint32_t tmp; |
1213 | 64201201 | bellard | |
1214 | 3cbee15b | j_mayer | tmp = nvram_read(nvram, addr) << 24;
|
1215 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 1) << 16; |
1216 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 2) << 8; |
1217 | 3cbee15b | j_mayer | tmp |= nvram_read(nvram, addr + 3);
|
1218 | 76a66253 | j_mayer | |
1219 | 64201201 | bellard | return tmp;
|
1220 | 64201201 | bellard | } |
1221 | 64201201 | bellard | |
1222 | c227f099 | Anthony Liguori | void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
|
1223 | b55266b5 | blueswir1 | const char *str, uint32_t max) |
1224 | 64201201 | bellard | { |
1225 | 64201201 | bellard | int i;
|
1226 | 64201201 | bellard | |
1227 | 64201201 | bellard | for (i = 0; i < max && str[i] != '\0'; i++) { |
1228 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1229 | 64201201 | bellard | } |
1230 | 3cbee15b | j_mayer | nvram_write(nvram, addr + i, str[i]); |
1231 | 3cbee15b | j_mayer | nvram_write(nvram, addr + max - 1, '\0'); |
1232 | 64201201 | bellard | } |
1233 | 64201201 | bellard | |
1234 | c227f099 | Anthony Liguori | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max) |
1235 | 64201201 | bellard | { |
1236 | 64201201 | bellard | int i;
|
1237 | 64201201 | bellard | |
1238 | 64201201 | bellard | memset(dst, 0, max);
|
1239 | 64201201 | bellard | for (i = 0; i < max; i++) { |
1240 | 64201201 | bellard | dst[i] = NVRAM_get_byte(nvram, addr + i); |
1241 | 64201201 | bellard | if (dst[i] == '\0') |
1242 | 64201201 | bellard | break;
|
1243 | 64201201 | bellard | } |
1244 | 64201201 | bellard | |
1245 | 64201201 | bellard | return i;
|
1246 | 64201201 | bellard | } |
1247 | 64201201 | bellard | |
1248 | 64201201 | bellard | static uint16_t NVRAM_crc_update (uint16_t prev, uint16_t value)
|
1249 | 64201201 | bellard | { |
1250 | 64201201 | bellard | uint16_t tmp; |
1251 | 64201201 | bellard | uint16_t pd, pd1, pd2; |
1252 | 64201201 | bellard | |
1253 | 64201201 | bellard | tmp = prev >> 8;
|
1254 | 64201201 | bellard | pd = prev ^ value; |
1255 | 64201201 | bellard | pd1 = pd & 0x000F;
|
1256 | 64201201 | bellard | pd2 = ((pd >> 4) & 0x000F) ^ pd1; |
1257 | 64201201 | bellard | tmp ^= (pd1 << 3) | (pd1 << 8); |
1258 | 64201201 | bellard | tmp ^= pd2 | (pd2 << 7) | (pd2 << 12); |
1259 | 64201201 | bellard | |
1260 | 64201201 | bellard | return tmp;
|
1261 | 64201201 | bellard | } |
1262 | 64201201 | bellard | |
1263 | c227f099 | Anthony Liguori | static uint16_t NVRAM_compute_crc (nvram_t *nvram, uint32_t start, uint32_t count)
|
1264 | 64201201 | bellard | { |
1265 | 64201201 | bellard | uint32_t i; |
1266 | 64201201 | bellard | uint16_t crc = 0xFFFF;
|
1267 | 64201201 | bellard | int odd;
|
1268 | 64201201 | bellard | |
1269 | 64201201 | bellard | odd = count & 1;
|
1270 | 64201201 | bellard | count &= ~1;
|
1271 | 64201201 | bellard | for (i = 0; i != count; i++) { |
1272 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_word(nvram, start + i)); |
1273 | 64201201 | bellard | } |
1274 | 64201201 | bellard | if (odd) {
|
1275 | 76a66253 | j_mayer | crc = NVRAM_crc_update(crc, NVRAM_get_byte(nvram, start + i) << 8);
|
1276 | 64201201 | bellard | } |
1277 | 64201201 | bellard | |
1278 | 64201201 | bellard | return crc;
|
1279 | 64201201 | bellard | } |
1280 | 64201201 | bellard | |
1281 | fd0bbb12 | bellard | #define CMDLINE_ADDR 0x017ff000 |
1282 | fd0bbb12 | bellard | |
1283 | c227f099 | Anthony Liguori | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
1284 | b55266b5 | blueswir1 | const char *arch, |
1285 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1286 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1287 | fd0bbb12 | bellard | const char *cmdline, |
1288 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1289 | fd0bbb12 | bellard | uint32_t NVRAM_image, |
1290 | fd0bbb12 | bellard | int width, int height, int depth) |
1291 | 64201201 | bellard | { |
1292 | 64201201 | bellard | uint16_t crc; |
1293 | 64201201 | bellard | |
1294 | 64201201 | bellard | /* Set parameters for Open Hack'Ware BIOS */
|
1295 | 64201201 | bellard | NVRAM_set_string(nvram, 0x00, "QEMU_BIOS", 16); |
1296 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x10, 0x00000002); /* structure v2 */ |
1297 | 64201201 | bellard | NVRAM_set_word(nvram, 0x14, NVRAM_size);
|
1298 | 64201201 | bellard | NVRAM_set_string(nvram, 0x20, arch, 16); |
1299 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x30, RAM_size);
|
1300 | 64201201 | bellard | NVRAM_set_byte(nvram, 0x34, boot_device);
|
1301 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x38, kernel_image);
|
1302 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x3C, kernel_size);
|
1303 | fd0bbb12 | bellard | if (cmdline) {
|
1304 | fd0bbb12 | bellard | /* XXX: put the cmdline in NVRAM too ? */
|
1305 | 3c178e72 | Gerd Hoffmann | pstrcpy_targphys("cmdline", CMDLINE_ADDR, RAM_size - CMDLINE_ADDR, cmdline);
|
1306 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, CMDLINE_ADDR);
|
1307 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, strlen(cmdline));
|
1308 | fd0bbb12 | bellard | } else {
|
1309 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x40, 0); |
1310 | fd0bbb12 | bellard | NVRAM_set_lword(nvram, 0x44, 0); |
1311 | fd0bbb12 | bellard | } |
1312 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x48, initrd_image);
|
1313 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x4C, initrd_size);
|
1314 | 64201201 | bellard | NVRAM_set_lword(nvram, 0x50, NVRAM_image);
|
1315 | fd0bbb12 | bellard | |
1316 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x54, width);
|
1317 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x56, height);
|
1318 | fd0bbb12 | bellard | NVRAM_set_word(nvram, 0x58, depth);
|
1319 | fd0bbb12 | bellard | crc = NVRAM_compute_crc(nvram, 0x00, 0xF8); |
1320 | 3cbee15b | j_mayer | NVRAM_set_word(nvram, 0xFC, crc);
|
1321 | 64201201 | bellard | |
1322 | 64201201 | bellard | return 0; |
1323 | a541f297 | bellard | } |