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1 | 267002cd | bellard | /*
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2 | 267002cd | bellard | * QEMU CUDA support
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3 | 267002cd | bellard | *
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4 | 267002cd | bellard | * Copyright (c) 2004 Fabrice Bellard
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5 | 267002cd | bellard | *
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6 | 267002cd | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | 267002cd | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | 267002cd | bellard | * in the Software without restriction, including without limitation the rights
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9 | 267002cd | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | 267002cd | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | 267002cd | bellard | * furnished to do so, subject to the following conditions:
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12 | 267002cd | bellard | *
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13 | 267002cd | bellard | * The above copyright notice and this permission notice shall be included in
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14 | 267002cd | bellard | * all copies or substantial portions of the Software.
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15 | 267002cd | bellard | *
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16 | 267002cd | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | 267002cd | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | 267002cd | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | 267002cd | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | 267002cd | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | 267002cd | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | 267002cd | bellard | * THE SOFTWARE.
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23 | 267002cd | bellard | */
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24 | 267002cd | bellard | #include "vl.h" |
25 | 267002cd | bellard | |
26 | 819e712b | bellard | //#define DEBUG_CUDA
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27 | 819e712b | bellard | //#define DEBUG_CUDA_PACKET
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28 | 819e712b | bellard | |
29 | 267002cd | bellard | /* Bits in B data register: all active low */
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30 | 267002cd | bellard | #define TREQ 0x08 /* Transfer request (input) */ |
31 | 267002cd | bellard | #define TACK 0x10 /* Transfer acknowledge (output) */ |
32 | 267002cd | bellard | #define TIP 0x20 /* Transfer in progress (output) */ |
33 | 267002cd | bellard | |
34 | 267002cd | bellard | /* Bits in ACR */
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35 | 267002cd | bellard | #define SR_CTRL 0x1c /* Shift register control bits */ |
36 | 267002cd | bellard | #define SR_EXT 0x0c /* Shift on external clock */ |
37 | 267002cd | bellard | #define SR_OUT 0x10 /* Shift out if 1 */ |
38 | 267002cd | bellard | |
39 | 267002cd | bellard | /* Bits in IFR and IER */
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40 | 267002cd | bellard | #define IER_SET 0x80 /* set bits in IER */ |
41 | 267002cd | bellard | #define IER_CLR 0 /* clear bits in IER */ |
42 | 267002cd | bellard | #define SR_INT 0x04 /* Shift register full/empty */ |
43 | 267002cd | bellard | #define T1_INT 0x40 /* Timer 1 interrupt */ |
44 | 267002cd | bellard | |
45 | 267002cd | bellard | /* Bits in ACR */
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46 | 267002cd | bellard | #define T1MODE 0xc0 /* Timer 1 mode */ |
47 | 267002cd | bellard | #define T1MODE_CONT 0x40 /* continuous interrupts */ |
48 | 267002cd | bellard | |
49 | 267002cd | bellard | /* commands (1st byte) */
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50 | 267002cd | bellard | #define ADB_PACKET 0 |
51 | 267002cd | bellard | #define CUDA_PACKET 1 |
52 | 267002cd | bellard | #define ERROR_PACKET 2 |
53 | 267002cd | bellard | #define TIMER_PACKET 3 |
54 | 267002cd | bellard | #define POWER_PACKET 4 |
55 | 267002cd | bellard | #define MACIIC_PACKET 5 |
56 | 267002cd | bellard | #define PMU_PACKET 6 |
57 | 267002cd | bellard | |
58 | 267002cd | bellard | |
59 | 267002cd | bellard | /* CUDA commands (2nd byte) */
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60 | 267002cd | bellard | #define CUDA_WARM_START 0x0 |
61 | 267002cd | bellard | #define CUDA_AUTOPOLL 0x1 |
62 | 267002cd | bellard | #define CUDA_GET_6805_ADDR 0x2 |
63 | 267002cd | bellard | #define CUDA_GET_TIME 0x3 |
64 | 267002cd | bellard | #define CUDA_GET_PRAM 0x7 |
65 | 267002cd | bellard | #define CUDA_SET_6805_ADDR 0x8 |
66 | 267002cd | bellard | #define CUDA_SET_TIME 0x9 |
67 | 267002cd | bellard | #define CUDA_POWERDOWN 0xa |
68 | 267002cd | bellard | #define CUDA_POWERUP_TIME 0xb |
69 | 267002cd | bellard | #define CUDA_SET_PRAM 0xc |
70 | 267002cd | bellard | #define CUDA_MS_RESET 0xd |
71 | 267002cd | bellard | #define CUDA_SEND_DFAC 0xe |
72 | 267002cd | bellard | #define CUDA_BATTERY_SWAP_SENSE 0x10 |
73 | 267002cd | bellard | #define CUDA_RESET_SYSTEM 0x11 |
74 | 267002cd | bellard | #define CUDA_SET_IPL 0x12 |
75 | 267002cd | bellard | #define CUDA_FILE_SERVER_FLAG 0x13 |
76 | 267002cd | bellard | #define CUDA_SET_AUTO_RATE 0x14 |
77 | 267002cd | bellard | #define CUDA_GET_AUTO_RATE 0x16 |
78 | 267002cd | bellard | #define CUDA_SET_DEVICE_LIST 0x19 |
79 | 267002cd | bellard | #define CUDA_GET_DEVICE_LIST 0x1a |
80 | 267002cd | bellard | #define CUDA_SET_ONE_SECOND_MODE 0x1b |
81 | 267002cd | bellard | #define CUDA_SET_POWER_MESSAGES 0x21 |
82 | 267002cd | bellard | #define CUDA_GET_SET_IIC 0x22 |
83 | 267002cd | bellard | #define CUDA_WAKEUP 0x23 |
84 | 267002cd | bellard | #define CUDA_TIMER_TICKLE 0x24 |
85 | 267002cd | bellard | #define CUDA_COMBINED_FORMAT_IIC 0x25 |
86 | 267002cd | bellard | |
87 | 267002cd | bellard | #define CUDA_TIMER_FREQ (4700000 / 6) |
88 | e2733d20 | bellard | #define CUDA_ADB_POLL_FREQ 50 |
89 | 267002cd | bellard | |
90 | d7ce296f | bellard | /* CUDA returns time_t's offset from Jan 1, 1904, not 1970 */
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91 | d7ce296f | bellard | #define RTC_OFFSET 2082844800 |
92 | d7ce296f | bellard | |
93 | 267002cd | bellard | typedef struct CUDATimer { |
94 | 267002cd | bellard | unsigned int latch; |
95 | 267002cd | bellard | uint16_t counter_value; /* counter value at load time */
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96 | 267002cd | bellard | int64_t load_time; |
97 | 267002cd | bellard | int64_t next_irq_time; |
98 | 267002cd | bellard | QEMUTimer *timer; |
99 | 267002cd | bellard | } CUDATimer; |
100 | 267002cd | bellard | |
101 | 267002cd | bellard | typedef struct CUDAState { |
102 | 267002cd | bellard | /* cuda registers */
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103 | 267002cd | bellard | uint8_t b; /* B-side data */
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104 | 267002cd | bellard | uint8_t a; /* A-side data */
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105 | 267002cd | bellard | uint8_t dirb; /* B-side direction (1=output) */
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106 | 267002cd | bellard | uint8_t dira; /* A-side direction (1=output) */
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107 | 267002cd | bellard | uint8_t sr; /* Shift register */
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108 | 267002cd | bellard | uint8_t acr; /* Auxiliary control register */
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109 | 267002cd | bellard | uint8_t pcr; /* Peripheral control register */
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110 | 267002cd | bellard | uint8_t ifr; /* Interrupt flag register */
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111 | 267002cd | bellard | uint8_t ier; /* Interrupt enable register */
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112 | 267002cd | bellard | uint8_t anh; /* A-side data, no handshake */
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113 | 267002cd | bellard | |
114 | 267002cd | bellard | CUDATimer timers[2];
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115 | 267002cd | bellard | |
116 | 267002cd | bellard | uint8_t last_b; /* last value of B register */
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117 | 267002cd | bellard | uint8_t last_acr; /* last value of B register */
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118 | 267002cd | bellard | |
119 | 267002cd | bellard | int data_in_size;
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120 | 267002cd | bellard | int data_in_index;
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121 | 267002cd | bellard | int data_out_index;
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122 | 267002cd | bellard | |
123 | 267002cd | bellard | int irq;
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124 | 819e712b | bellard | openpic_t *openpic; |
125 | 267002cd | bellard | uint8_t autopoll; |
126 | 267002cd | bellard | uint8_t data_in[128];
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127 | 267002cd | bellard | uint8_t data_out[16];
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128 | e2733d20 | bellard | QEMUTimer *adb_poll_timer; |
129 | 267002cd | bellard | } CUDAState; |
130 | 267002cd | bellard | |
131 | 267002cd | bellard | static CUDAState cuda_state;
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132 | 267002cd | bellard | ADBBusState adb_bus; |
133 | 267002cd | bellard | |
134 | 267002cd | bellard | static void cuda_update(CUDAState *s); |
135 | 267002cd | bellard | static void cuda_receive_packet_from_host(CUDAState *s, |
136 | 267002cd | bellard | const uint8_t *data, int len); |
137 | 819e712b | bellard | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
138 | 819e712b | bellard | int64_t current_time); |
139 | 267002cd | bellard | |
140 | 267002cd | bellard | static void cuda_update_irq(CUDAState *s) |
141 | 267002cd | bellard | { |
142 | 819e712b | bellard | if (s->ifr & s->ier & (SR_INT | T1_INT)) {
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143 | 819e712b | bellard | openpic_set_irq(s->openpic, s->irq, 1);
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144 | 267002cd | bellard | } else {
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145 | 819e712b | bellard | openpic_set_irq(s->openpic, s->irq, 0);
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146 | 267002cd | bellard | } |
147 | 267002cd | bellard | } |
148 | 267002cd | bellard | |
149 | 267002cd | bellard | static unsigned int get_counter(CUDATimer *s) |
150 | 267002cd | bellard | { |
151 | 267002cd | bellard | int64_t d; |
152 | 267002cd | bellard | unsigned int counter; |
153 | 267002cd | bellard | |
154 | 267002cd | bellard | d = muldiv64(qemu_get_clock(vm_clock) - s->load_time, |
155 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
156 | 267002cd | bellard | if (d <= s->counter_value) {
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157 | 267002cd | bellard | counter = d; |
158 | 267002cd | bellard | } else {
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159 | 267002cd | bellard | counter = s->latch - 1 - ((d - s->counter_value) % s->latch);
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160 | 267002cd | bellard | } |
161 | 267002cd | bellard | return counter;
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162 | 267002cd | bellard | } |
163 | 267002cd | bellard | |
164 | 819e712b | bellard | static void set_counter(CUDAState *s, CUDATimer *ti, unsigned int val) |
165 | 267002cd | bellard | { |
166 | 819e712b | bellard | #ifdef DEBUG_CUDA
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167 | 819e712b | bellard | printf("cuda: T%d.counter=%d\n",
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168 | 819e712b | bellard | 1 + (ti->timer == NULL), val); |
169 | 819e712b | bellard | #endif
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170 | 819e712b | bellard | ti->load_time = qemu_get_clock(vm_clock); |
171 | 819e712b | bellard | ti->counter_value = val; |
172 | 819e712b | bellard | cuda_timer_update(s, ti, ti->load_time); |
173 | 267002cd | bellard | } |
174 | 267002cd | bellard | |
175 | 267002cd | bellard | static int64_t get_next_irq_time(CUDATimer *s, int64_t current_time)
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176 | 267002cd | bellard | { |
177 | 267002cd | bellard | int64_t d, next_time, base; |
178 | 267002cd | bellard | /* current counter value */
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179 | 267002cd | bellard | d = muldiv64(current_time - s->load_time, |
180 | 267002cd | bellard | CUDA_TIMER_FREQ, ticks_per_sec); |
181 | dccfafc4 | bellard | if (d < s->counter_value) {
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182 | 267002cd | bellard | next_time = s->counter_value + 1;
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183 | dccfafc4 | bellard | } else
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184 | dccfafc4 | bellard | { |
185 | dccfafc4 | bellard | base = ((d - s->counter_value + 1) / s->latch);
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186 | 267002cd | bellard | base = (base * s->latch) + s->counter_value; |
187 | 267002cd | bellard | next_time = base + s->latch; |
188 | 267002cd | bellard | } |
189 | dccfafc4 | bellard | #if 0
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190 | 819e712b | bellard | #ifdef DEBUG_CUDA
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191 | 819e712b | bellard | printf("latch=%d counter=%lld delta_next=%lld\n",
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192 | 819e712b | bellard | s->latch, d, next_time - d);
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193 | 819e712b | bellard | #endif
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194 | dccfafc4 | bellard | #endif
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195 | 267002cd | bellard | next_time = muldiv64(next_time, ticks_per_sec, CUDA_TIMER_FREQ) + |
196 | 267002cd | bellard | s->load_time; |
197 | 267002cd | bellard | if (next_time <= current_time)
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198 | 267002cd | bellard | next_time = current_time + 1;
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199 | 267002cd | bellard | return next_time;
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200 | 267002cd | bellard | } |
201 | 267002cd | bellard | |
202 | 819e712b | bellard | static void cuda_timer_update(CUDAState *s, CUDATimer *ti, |
203 | 819e712b | bellard | int64_t current_time) |
204 | 819e712b | bellard | { |
205 | 819e712b | bellard | if (!ti->timer)
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206 | 819e712b | bellard | return;
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207 | 819e712b | bellard | if ((s->acr & T1MODE) != T1MODE_CONT) {
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208 | 819e712b | bellard | qemu_del_timer(ti->timer); |
209 | 819e712b | bellard | } else {
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210 | 819e712b | bellard | ti->next_irq_time = get_next_irq_time(ti, current_time); |
211 | 819e712b | bellard | qemu_mod_timer(ti->timer, ti->next_irq_time); |
212 | 819e712b | bellard | } |
213 | 819e712b | bellard | } |
214 | 819e712b | bellard | |
215 | 267002cd | bellard | static void cuda_timer1(void *opaque) |
216 | 267002cd | bellard | { |
217 | 267002cd | bellard | CUDAState *s = opaque; |
218 | 267002cd | bellard | CUDATimer *ti = &s->timers[0];
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219 | 267002cd | bellard | |
220 | 819e712b | bellard | cuda_timer_update(s, ti, ti->next_irq_time); |
221 | 267002cd | bellard | s->ifr |= T1_INT; |
222 | 267002cd | bellard | cuda_update_irq(s); |
223 | 267002cd | bellard | } |
224 | 267002cd | bellard | |
225 | 267002cd | bellard | static uint32_t cuda_readb(void *opaque, target_phys_addr_t addr) |
226 | 267002cd | bellard | { |
227 | 267002cd | bellard | CUDAState *s = opaque; |
228 | 267002cd | bellard | uint32_t val; |
229 | 267002cd | bellard | |
230 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
231 | 267002cd | bellard | switch(addr) {
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232 | 267002cd | bellard | case 0: |
233 | 267002cd | bellard | val = s->b; |
234 | 267002cd | bellard | break;
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235 | 267002cd | bellard | case 1: |
236 | 267002cd | bellard | val = s->a; |
237 | 267002cd | bellard | break;
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238 | 267002cd | bellard | case 2: |
239 | 267002cd | bellard | val = s->dirb; |
240 | 267002cd | bellard | break;
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241 | 267002cd | bellard | case 3: |
242 | 267002cd | bellard | val = s->dira; |
243 | 267002cd | bellard | break;
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244 | 267002cd | bellard | case 4: |
245 | 267002cd | bellard | val = get_counter(&s->timers[0]) & 0xff; |
246 | 267002cd | bellard | s->ifr &= ~T1_INT; |
247 | 267002cd | bellard | cuda_update_irq(s); |
248 | 267002cd | bellard | break;
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249 | 267002cd | bellard | case 5: |
250 | 267002cd | bellard | val = get_counter(&s->timers[0]) >> 8; |
251 | 267002cd | bellard | s->ifr &= ~T1_INT; |
252 | 267002cd | bellard | cuda_update_irq(s); |
253 | 267002cd | bellard | break;
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254 | 267002cd | bellard | case 6: |
255 | 267002cd | bellard | val = s->timers[0].latch & 0xff; |
256 | 267002cd | bellard | break;
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257 | 267002cd | bellard | case 7: |
258 | 267002cd | bellard | val = (s->timers[0].latch >> 8) & 0xff; |
259 | 267002cd | bellard | break;
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260 | 267002cd | bellard | case 8: |
261 | 267002cd | bellard | val = get_counter(&s->timers[1]) & 0xff; |
262 | 267002cd | bellard | break;
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263 | 267002cd | bellard | case 9: |
264 | 267002cd | bellard | val = get_counter(&s->timers[1]) >> 8; |
265 | 267002cd | bellard | break;
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266 | 267002cd | bellard | case 10: |
267 | 819e712b | bellard | val = s->sr; |
268 | 819e712b | bellard | s->ifr &= ~SR_INT; |
269 | 819e712b | bellard | cuda_update_irq(s); |
270 | 267002cd | bellard | break;
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271 | 267002cd | bellard | case 11: |
272 | 267002cd | bellard | val = s->acr; |
273 | 267002cd | bellard | break;
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274 | 267002cd | bellard | case 12: |
275 | 267002cd | bellard | val = s->pcr; |
276 | 267002cd | bellard | break;
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277 | 267002cd | bellard | case 13: |
278 | 267002cd | bellard | val = s->ifr; |
279 | 267002cd | bellard | break;
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280 | 267002cd | bellard | case 14: |
281 | 267002cd | bellard | val = s->ier; |
282 | 267002cd | bellard | break;
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283 | 267002cd | bellard | default:
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284 | 267002cd | bellard | case 15: |
285 | 267002cd | bellard | val = s->anh; |
286 | 267002cd | bellard | break;
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287 | 267002cd | bellard | } |
288 | 267002cd | bellard | #ifdef DEBUG_CUDA
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289 | 819e712b | bellard | if (addr != 13 || val != 0) |
290 | 819e712b | bellard | printf("cuda: read: reg=0x%x val=%02x\n", addr, val);
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291 | 267002cd | bellard | #endif
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292 | 267002cd | bellard | return val;
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293 | 267002cd | bellard | } |
294 | 267002cd | bellard | |
295 | 267002cd | bellard | static void cuda_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
296 | 267002cd | bellard | { |
297 | 267002cd | bellard | CUDAState *s = opaque; |
298 | 267002cd | bellard | |
299 | 267002cd | bellard | addr = (addr >> 9) & 0xf; |
300 | 267002cd | bellard | #ifdef DEBUG_CUDA
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301 | 267002cd | bellard | printf("cuda: write: reg=0x%x val=%02x\n", addr, val);
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302 | 267002cd | bellard | #endif
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303 | 267002cd | bellard | |
304 | 267002cd | bellard | switch(addr) {
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305 | 267002cd | bellard | case 0: |
306 | 267002cd | bellard | s->b = val; |
307 | 267002cd | bellard | cuda_update(s); |
308 | 267002cd | bellard | break;
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309 | 267002cd | bellard | case 1: |
310 | 267002cd | bellard | s->a = val; |
311 | 267002cd | bellard | break;
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312 | 267002cd | bellard | case 2: |
313 | 267002cd | bellard | s->dirb = val; |
314 | 267002cd | bellard | break;
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315 | 267002cd | bellard | case 3: |
316 | 267002cd | bellard | s->dira = val; |
317 | 267002cd | bellard | break;
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318 | 267002cd | bellard | case 4: |
319 | 267002cd | bellard | val = val | (get_counter(&s->timers[0]) & 0xff00); |
320 | 819e712b | bellard | set_counter(s, &s->timers[0], val);
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321 | 267002cd | bellard | break;
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322 | 267002cd | bellard | case 5: |
323 | 267002cd | bellard | val = (val << 8) | (get_counter(&s->timers[0]) & 0xff); |
324 | 819e712b | bellard | set_counter(s, &s->timers[0], val);
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325 | 267002cd | bellard | break;
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326 | 267002cd | bellard | case 6: |
327 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff00) | val; |
328 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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329 | 267002cd | bellard | break;
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330 | 267002cd | bellard | case 7: |
331 | 267002cd | bellard | s->timers[0].latch = (s->timers[0].latch & 0xff) | (val << 8); |
332 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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333 | 267002cd | bellard | break;
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334 | 267002cd | bellard | case 8: |
335 | 267002cd | bellard | val = val | (get_counter(&s->timers[1]) & 0xff00); |
336 | 819e712b | bellard | set_counter(s, &s->timers[1], val);
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337 | 267002cd | bellard | break;
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338 | 267002cd | bellard | case 9: |
339 | 267002cd | bellard | val = (val << 8) | (get_counter(&s->timers[1]) & 0xff); |
340 | 819e712b | bellard | set_counter(s, &s->timers[1], val);
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341 | 267002cd | bellard | break;
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342 | 267002cd | bellard | case 10: |
343 | 267002cd | bellard | s->sr = val; |
344 | 267002cd | bellard | break;
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345 | 267002cd | bellard | case 11: |
346 | 267002cd | bellard | s->acr = val; |
347 | 819e712b | bellard | cuda_timer_update(s, &s->timers[0], qemu_get_clock(vm_clock));
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348 | 267002cd | bellard | cuda_update(s); |
349 | 267002cd | bellard | break;
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350 | 267002cd | bellard | case 12: |
351 | 267002cd | bellard | s->pcr = val; |
352 | 267002cd | bellard | break;
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353 | 267002cd | bellard | case 13: |
354 | 267002cd | bellard | /* reset bits */
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355 | 267002cd | bellard | s->ifr &= ~val; |
356 | 267002cd | bellard | cuda_update_irq(s); |
357 | 267002cd | bellard | break;
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358 | 267002cd | bellard | case 14: |
359 | 267002cd | bellard | if (val & IER_SET) {
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360 | 267002cd | bellard | /* set bits */
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361 | 267002cd | bellard | s->ier |= val & 0x7f;
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362 | 267002cd | bellard | } else {
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363 | 267002cd | bellard | /* reset bits */
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364 | 267002cd | bellard | s->ier &= ~val; |
365 | 267002cd | bellard | } |
366 | 267002cd | bellard | cuda_update_irq(s); |
367 | 267002cd | bellard | break;
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368 | 267002cd | bellard | default:
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369 | 267002cd | bellard | case 15: |
370 | 267002cd | bellard | s->anh = val; |
371 | 267002cd | bellard | break;
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372 | 267002cd | bellard | } |
373 | 267002cd | bellard | } |
374 | 267002cd | bellard | |
375 | 267002cd | bellard | /* NOTE: TIP and TREQ are negated */
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376 | 267002cd | bellard | static void cuda_update(CUDAState *s) |
377 | 267002cd | bellard | { |
378 | 819e712b | bellard | int packet_received, len;
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379 | 819e712b | bellard | |
380 | 819e712b | bellard | packet_received = 0;
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381 | 819e712b | bellard | if (!(s->b & TIP)) {
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382 | 819e712b | bellard | /* transfer requested from host */
|
383 | 267002cd | bellard | |
384 | 819e712b | bellard | if (s->acr & SR_OUT) {
|
385 | 819e712b | bellard | /* data output */
|
386 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
387 | 819e712b | bellard | if (s->data_out_index < sizeof(s->data_out)) { |
388 | 819e712b | bellard | #ifdef DEBUG_CUDA
|
389 | 819e712b | bellard | printf("cuda: send: %02x\n", s->sr);
|
390 | 819e712b | bellard | #endif
|
391 | 819e712b | bellard | s->data_out[s->data_out_index++] = s->sr; |
392 | 819e712b | bellard | s->ifr |= SR_INT; |
393 | 819e712b | bellard | cuda_update_irq(s); |
394 | 819e712b | bellard | } |
395 | 819e712b | bellard | } |
396 | 819e712b | bellard | } else {
|
397 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
398 | 819e712b | bellard | /* data input */
|
399 | 819e712b | bellard | if ((s->b & (TACK | TIP)) != (s->last_b & (TACK | TIP))) {
|
400 | 819e712b | bellard | s->sr = s->data_in[s->data_in_index++]; |
401 | 819e712b | bellard | #ifdef DEBUG_CUDA
|
402 | 819e712b | bellard | printf("cuda: recv: %02x\n", s->sr);
|
403 | 819e712b | bellard | #endif
|
404 | 819e712b | bellard | /* indicate end of transfer */
|
405 | 819e712b | bellard | if (s->data_in_index >= s->data_in_size) {
|
406 | 819e712b | bellard | s->b = (s->b | TREQ); |
407 | 819e712b | bellard | } |
408 | 819e712b | bellard | s->ifr |= SR_INT; |
409 | 819e712b | bellard | cuda_update_irq(s); |
410 | 819e712b | bellard | } |
411 | 267002cd | bellard | } |
412 | 819e712b | bellard | } |
413 | 819e712b | bellard | } else {
|
414 | 819e712b | bellard | /* no transfer requested: handle sync case */
|
415 | 819e712b | bellard | if ((s->last_b & TIP) && (s->b & TACK) != (s->last_b & TACK)) {
|
416 | 819e712b | bellard | /* update TREQ state each time TACK change state */
|
417 | 819e712b | bellard | if (s->b & TACK)
|
418 | 819e712b | bellard | s->b = (s->b | TREQ); |
419 | 819e712b | bellard | else
|
420 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
421 | 267002cd | bellard | s->ifr |= SR_INT; |
422 | 267002cd | bellard | cuda_update_irq(s); |
423 | 819e712b | bellard | } else {
|
424 | 819e712b | bellard | if (!(s->last_b & TIP)) {
|
425 | 819e712b | bellard | /* handle end of host to cuda transfert */
|
426 | 819e712b | bellard | packet_received = (s->data_out_index > 0);
|
427 | 819e712b | bellard | /* always an IRQ at the end of transfert */
|
428 | 819e712b | bellard | s->ifr |= SR_INT; |
429 | 819e712b | bellard | cuda_update_irq(s); |
430 | 819e712b | bellard | } |
431 | 819e712b | bellard | /* signal if there is data to read */
|
432 | 819e712b | bellard | if (s->data_in_index < s->data_in_size) {
|
433 | 819e712b | bellard | s->b = (s->b & ~TREQ); |
434 | 819e712b | bellard | } |
435 | 267002cd | bellard | } |
436 | 267002cd | bellard | } |
437 | 267002cd | bellard | |
438 | 267002cd | bellard | s->last_acr = s->acr; |
439 | 267002cd | bellard | s->last_b = s->b; |
440 | 819e712b | bellard | |
441 | 819e712b | bellard | /* NOTE: cuda_receive_packet_from_host() can call cuda_update()
|
442 | 819e712b | bellard | recursively */
|
443 | 819e712b | bellard | if (packet_received) {
|
444 | 819e712b | bellard | len = s->data_out_index; |
445 | 819e712b | bellard | s->data_out_index = 0;
|
446 | 819e712b | bellard | cuda_receive_packet_from_host(s, s->data_out, len); |
447 | 819e712b | bellard | } |
448 | 267002cd | bellard | } |
449 | 267002cd | bellard | |
450 | 267002cd | bellard | static void cuda_send_packet_to_host(CUDAState *s, |
451 | 267002cd | bellard | const uint8_t *data, int len) |
452 | 267002cd | bellard | { |
453 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
454 | 819e712b | bellard | { |
455 | 819e712b | bellard | int i;
|
456 | 819e712b | bellard | printf("cuda_send_packet_to_host:\n");
|
457 | 819e712b | bellard | for(i = 0; i < len; i++) |
458 | 819e712b | bellard | printf(" %02x", data[i]);
|
459 | 819e712b | bellard | printf("\n");
|
460 | 819e712b | bellard | } |
461 | 819e712b | bellard | #endif
|
462 | 267002cd | bellard | memcpy(s->data_in, data, len); |
463 | 267002cd | bellard | s->data_in_size = len; |
464 | 267002cd | bellard | s->data_in_index = 0;
|
465 | 267002cd | bellard | cuda_update(s); |
466 | 267002cd | bellard | s->ifr |= SR_INT; |
467 | 267002cd | bellard | cuda_update_irq(s); |
468 | 267002cd | bellard | } |
469 | 267002cd | bellard | |
470 | 7db4eea6 | bellard | static void cuda_adb_poll(void *opaque) |
471 | e2733d20 | bellard | { |
472 | e2733d20 | bellard | CUDAState *s = opaque; |
473 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
474 | e2733d20 | bellard | int olen;
|
475 | e2733d20 | bellard | |
476 | e2733d20 | bellard | olen = adb_poll(&adb_bus, obuf + 2);
|
477 | e2733d20 | bellard | if (olen > 0) { |
478 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
479 | e2733d20 | bellard | obuf[1] = 0x40; /* polled data */ |
480 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
481 | e2733d20 | bellard | } |
482 | e2733d20 | bellard | qemu_mod_timer(s->adb_poll_timer, |
483 | e2733d20 | bellard | qemu_get_clock(vm_clock) + |
484 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
485 | e2733d20 | bellard | } |
486 | e2733d20 | bellard | |
487 | 267002cd | bellard | static void cuda_receive_packet(CUDAState *s, |
488 | 267002cd | bellard | const uint8_t *data, int len) |
489 | 267002cd | bellard | { |
490 | 267002cd | bellard | uint8_t obuf[16];
|
491 | e2733d20 | bellard | int ti, autopoll;
|
492 | 267002cd | bellard | |
493 | 267002cd | bellard | switch(data[0]) { |
494 | 267002cd | bellard | case CUDA_AUTOPOLL:
|
495 | e2733d20 | bellard | autopoll = (data[1] != 0); |
496 | e2733d20 | bellard | if (autopoll != s->autopoll) {
|
497 | e2733d20 | bellard | s->autopoll = autopoll; |
498 | e2733d20 | bellard | if (autopoll) {
|
499 | e2733d20 | bellard | qemu_mod_timer(s->adb_poll_timer, |
500 | e2733d20 | bellard | qemu_get_clock(vm_clock) + |
501 | e2733d20 | bellard | (ticks_per_sec / CUDA_ADB_POLL_FREQ)); |
502 | e2733d20 | bellard | } else {
|
503 | e2733d20 | bellard | qemu_del_timer(s->adb_poll_timer); |
504 | e2733d20 | bellard | } |
505 | e2733d20 | bellard | } |
506 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
507 | 267002cd | bellard | obuf[1] = data[1]; |
508 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
509 | 267002cd | bellard | break;
|
510 | 267002cd | bellard | case CUDA_GET_TIME:
|
511 | dccfafc4 | bellard | case CUDA_SET_TIME:
|
512 | 267002cd | bellard | /* XXX: add time support ? */
|
513 | d7ce296f | bellard | ti = time(NULL) + RTC_OFFSET;
|
514 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
515 | 267002cd | bellard | obuf[1] = 0; |
516 | 267002cd | bellard | obuf[2] = 0; |
517 | 267002cd | bellard | obuf[3] = ti >> 24; |
518 | 267002cd | bellard | obuf[4] = ti >> 16; |
519 | 267002cd | bellard | obuf[5] = ti >> 8; |
520 | 267002cd | bellard | obuf[6] = ti;
|
521 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 7);
|
522 | 267002cd | bellard | break;
|
523 | 267002cd | bellard | case CUDA_FILE_SERVER_FLAG:
|
524 | 267002cd | bellard | case CUDA_SET_DEVICE_LIST:
|
525 | 267002cd | bellard | case CUDA_SET_AUTO_RATE:
|
526 | 267002cd | bellard | case CUDA_SET_POWER_MESSAGES:
|
527 | 267002cd | bellard | obuf[0] = CUDA_PACKET;
|
528 | 267002cd | bellard | obuf[1] = 0; |
529 | 267002cd | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
530 | 267002cd | bellard | break;
|
531 | d7ce296f | bellard | case CUDA_POWERDOWN:
|
532 | d7ce296f | bellard | obuf[0] = CUDA_PACKET;
|
533 | d7ce296f | bellard | obuf[1] = 0; |
534 | d7ce296f | bellard | cuda_send_packet_to_host(s, obuf, 2);
|
535 | d7ce296f | bellard | qemu_system_shutdown_request(); |
536 | d7ce296f | bellard | break;
|
537 | 267002cd | bellard | default:
|
538 | 267002cd | bellard | break;
|
539 | 267002cd | bellard | } |
540 | 267002cd | bellard | } |
541 | 267002cd | bellard | |
542 | 267002cd | bellard | static void cuda_receive_packet_from_host(CUDAState *s, |
543 | 267002cd | bellard | const uint8_t *data, int len) |
544 | 267002cd | bellard | { |
545 | 819e712b | bellard | #ifdef DEBUG_CUDA_PACKET
|
546 | 819e712b | bellard | { |
547 | 819e712b | bellard | int i;
|
548 | 819e712b | bellard | printf("cuda_receive_packet_to_host:\n");
|
549 | 819e712b | bellard | for(i = 0; i < len; i++) |
550 | 819e712b | bellard | printf(" %02x", data[i]);
|
551 | 819e712b | bellard | printf("\n");
|
552 | 819e712b | bellard | } |
553 | 819e712b | bellard | #endif
|
554 | 267002cd | bellard | switch(data[0]) { |
555 | 267002cd | bellard | case ADB_PACKET:
|
556 | e2733d20 | bellard | { |
557 | e2733d20 | bellard | uint8_t obuf[ADB_MAX_OUT_LEN + 2];
|
558 | e2733d20 | bellard | int olen;
|
559 | e2733d20 | bellard | olen = adb_request(&adb_bus, obuf + 2, data + 1, len - 1); |
560 | 38f0b147 | bellard | if (olen > 0) { |
561 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
562 | e2733d20 | bellard | obuf[1] = 0x00; |
563 | e2733d20 | bellard | } else {
|
564 | 38f0b147 | bellard | /* error */
|
565 | e2733d20 | bellard | obuf[0] = ADB_PACKET;
|
566 | 38f0b147 | bellard | obuf[1] = -olen;
|
567 | 38f0b147 | bellard | olen = 0;
|
568 | e2733d20 | bellard | } |
569 | e2733d20 | bellard | cuda_send_packet_to_host(s, obuf, olen + 2);
|
570 | e2733d20 | bellard | } |
571 | 267002cd | bellard | break;
|
572 | 267002cd | bellard | case CUDA_PACKET:
|
573 | 267002cd | bellard | cuda_receive_packet(s, data + 1, len - 1); |
574 | 267002cd | bellard | break;
|
575 | 267002cd | bellard | } |
576 | 267002cd | bellard | } |
577 | 267002cd | bellard | |
578 | 267002cd | bellard | static void cuda_writew (void *opaque, target_phys_addr_t addr, uint32_t value) |
579 | 267002cd | bellard | { |
580 | 267002cd | bellard | } |
581 | 267002cd | bellard | |
582 | 267002cd | bellard | static void cuda_writel (void *opaque, target_phys_addr_t addr, uint32_t value) |
583 | 267002cd | bellard | { |
584 | 267002cd | bellard | } |
585 | 267002cd | bellard | |
586 | 267002cd | bellard | static uint32_t cuda_readw (void *opaque, target_phys_addr_t addr) |
587 | 267002cd | bellard | { |
588 | 267002cd | bellard | return 0; |
589 | 267002cd | bellard | } |
590 | 267002cd | bellard | |
591 | 267002cd | bellard | static uint32_t cuda_readl (void *opaque, target_phys_addr_t addr) |
592 | 267002cd | bellard | { |
593 | 267002cd | bellard | return 0; |
594 | 267002cd | bellard | } |
595 | 267002cd | bellard | |
596 | 267002cd | bellard | static CPUWriteMemoryFunc *cuda_write[] = {
|
597 | 267002cd | bellard | &cuda_writeb, |
598 | 267002cd | bellard | &cuda_writew, |
599 | 267002cd | bellard | &cuda_writel, |
600 | 267002cd | bellard | }; |
601 | 267002cd | bellard | |
602 | 267002cd | bellard | static CPUReadMemoryFunc *cuda_read[] = {
|
603 | 267002cd | bellard | &cuda_readb, |
604 | 267002cd | bellard | &cuda_readw, |
605 | 267002cd | bellard | &cuda_readl, |
606 | 267002cd | bellard | }; |
607 | 267002cd | bellard | |
608 | 819e712b | bellard | int cuda_init(openpic_t *openpic, int irq) |
609 | 267002cd | bellard | { |
610 | 267002cd | bellard | CUDAState *s = &cuda_state; |
611 | 267002cd | bellard | int cuda_mem_index;
|
612 | 267002cd | bellard | |
613 | 819e712b | bellard | s->openpic = openpic; |
614 | 819e712b | bellard | s->irq = irq; |
615 | 819e712b | bellard | |
616 | 267002cd | bellard | s->timers[0].timer = qemu_new_timer(vm_clock, cuda_timer1, s);
|
617 | 819e712b | bellard | s->timers[0].latch = 0x10000; |
618 | 819e712b | bellard | set_counter(s, &s->timers[0], 0xffff); |
619 | 267002cd | bellard | s->timers[1].latch = 0x10000; |
620 | 819e712b | bellard | s->ier = T1_INT | SR_INT; |
621 | 819e712b | bellard | set_counter(s, &s->timers[1], 0xffff); |
622 | e2733d20 | bellard | |
623 | e2733d20 | bellard | s->adb_poll_timer = qemu_new_timer(vm_clock, cuda_adb_poll, s); |
624 | 267002cd | bellard | cuda_mem_index = cpu_register_io_memory(0, cuda_read, cuda_write, s);
|
625 | 267002cd | bellard | return cuda_mem_index;
|
626 | 267002cd | bellard | } |