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Name Size
Makefile.objs 465 Bytes
arm-semi.c 17.2 kB
cpu-qom.h 5.9 kB
cpu.c 32.5 kB
cpu.h 38.6 kB
cpu64.c 3.5 kB
crypto_helper.c 13 kB
gdbstub.c 2.8 kB
gdbstub64.c 1.9 kB
helper-a64.c 4.3 kB
helper-a64.h 1.4 kB
helper.c 143.4 kB
helper.h 18.8 kB
iwmmxt_helper.c 24.8 kB
kvm-consts.h 3.8 kB
kvm-stub.c 437 Bytes
kvm.c 9.4 kB
kvm32.c 15.7 kB
kvm64.c 5.2 kB
kvm_arm.h 3.8 kB
machine.c 7.9 kB
neon_helper.c 52.4 kB
op_addsub.h 1.8 kB
op_helper.c 8.9 kB
translate-a64.c 213.1 kB
translate.c 375.8 kB
translate.h 1.9 kB

Latest revisions

# Date Author Comment
e1cea114 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add top level decode for SIMD 3-same group

Add top level decode for the A64 SIMD three regs same group
(C3.6.16), splitting it into the pairwise, logical, float and
integer subgroups.

Signed-off-by: Peter Maydell <>...
956d272e 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add logic ops from SIMD 3 same group

Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,
BIT and BIF) from the SIMD 3 register same group (C3.6.16).

Signed-off-by: Alex Bennée <>
Signed-off-by: Peter Maydell <>...
1f8a73af 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add integer ops from SIMD 3-same group

Add some of the integer operations in the SIMD 3-same group:
specifically, the comparisons, addition and subtraction.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
845ea09a 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add simple SIMD 3-same floating point ops

Implement a simple subset of the SIMD 3-same floating point
operations. This includes a common helper function used for both
scalar and vector ops; FABD is the only currently implemented
shared op....
4d1cef84 01/31/2014 04:47 pm Alex Bennée

target-arm: A64: Add SIMD shift by immediate

This implements a subset of the AdvSIMD shift operations (namely all the
none saturating or narrowing ones). The actual shift generation code
itself is common for both the scalar and vector cases but wrapped with...
a08582f4 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD three-different multiply accumulate insns

Add support for the multiply-accumulate instructions from the
SIMD three-different instructions group (C3.6.15): * skeleton decode of unallocated encodings and split of
the group into its three sub-parts...
0ae39320 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD three-different ABDL instructions

Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.

Signed-off-by: Peter Maydell <>...
b305dba6 01/31/2014 04:47 pm Peter Maydell

target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops

Implement the add, sub and compare ops from the SIMD "scalar three same"
group.

Signed-off-by: Peter Maydell <>
Reviewed-by: Richard Henderson <>
c9975a83 01/31/2014 04:47 pm Will Newton

target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <>
Signed-off-by: Peter Maydell <>
901ad525 01/31/2014 04:47 pm Will Newton

target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <>
Signed-off-by: Peter Maydell <>

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