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target-i386: Tidy ljmp
Remove an unnecessary move opcode.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>Signed-off-by: Richard Henderson <rth@twiddle.net>
target-i386: Rename gen_op_jmp_T0 to gen_op_jmp_v
And make the destination argument explicit.
target-i386: Tidy some size computation
Clean up relics of multiple size domains: - MO_16 + 1 => - 1 + 1 => 0.
target-i386: Remove gen_op_mov_reg_A0
Replace with its definition.
target-i386: Remove gen_op_mov_TN_reg
target-i386: Remove gen_op_addl_T0_T1
target-i386: Remove gen_op_mov_reg_T1
target-i386: Remove gen_op_mov_reg_T0
target-i386: Tidy cpu_regs initialization
target-i386: Tidy addr16 code in gen_lea_modrm
Unlike the addr32, there was no bug. But we can use the sametechnique to reduce the number of TCG ops.
target-i386: Combine gen_push_T* into gen_push_v
Reduce ifdefs, share more code between paths, reduce the number of TCGops generated.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>...
target_i386: Clean up gen_pop_T0
Reduce ifdefs, share more code between paths, reduce the number of TCGops generated. Avoid re-computing the size of the operation acrossgen_pop_T0 and gen_pop_update.
Add forgotten zero-extension in the TARGET_X86_64, !CODE64, ss32 case....
target-i386: Change dflag to TCGMemOp
Changing the domain to TCGMemOp makes it easier to interoperatewith other portions of the rest of the translator.
We now only have one domain for size operands inside the translator,which makes things less confusing all the way around. There are...
target-i386: Change gen_op_mov_reg_A0 size parameter to TCGMemOp
Change the domain of the parameter and update all callers.Which lets us defer completely to gen_op_mov_reg_v.
target-i386: Change aflag to TCGMemOp
target-i386: Change gen_op_add_reg_* size parameter to TCGMemOp
These functions used the aflags/dflags domain, which is log2-1of the byte size. Confusingly, they used enumeration valuesfrom the log2 domain.
Change the domain of the parameter and update all callers....
target-i386: Change gen_op_j*z_ecx size parameter to TCGMemOp
Change the domain of the parameter and update all callers.
target-i386: Use TCGMemOp for 'ot' variables
The 'ot' variables (operand type?) hold the log2(byte size) ofthe operand being manipulated. This is the same as the MO_SIZEsubset of the TCGMemOp. Indeed, we often pass 'ot' to thetcg_gen_qemu_ld/st functions....
target-i386: Remove gen_op_movl_T0_T1
Replace it with its definition.
target-i386: Remove gen_op_andl_A0_ffff
Replace it with tcg_gen_ext16u_tl, and in two cases merge with aprevious move from cpu_regs.
target-i386: Tidy extend + store
We can now use tcg_gen_qemu_st_i32 directly to avoid the extension.
target-i386: Tidy extend + move
For the known MO_32/MO_64 cases, we don't need to extend a 32-bit tempinto a 64-bit temp before storing into the hardware register.
We do need the extension for the MO_8/MO_16 cases, in order for thedeposit_tl operation to work, so leave those alone....
target-i386: Remove gen_op_movl_T0_0
Propagate its definition into all users.
target-i386: Remove gen_op_movl_T0_im*
Propagate the definition of gen_op_movl_T0_im to all users.The function gen_op_movl_T0_imu was unused.
Propagate the definitions into all users. The only time thatgen_op_movl_T1_imu was used, the input was type 'unsigned',so the replacement works identically.
target-i386: Remove gen_op_mov*_A0_im
Propagate the definitions into all users. In two cases, this allowsus to share code between the 32-bit and 64-bit immediate moves.
target-i386: Remove gen_movtl_T*_im
Propagate the definitions into all users.
target-i386: Remove gen_op_andl_T0_ffff
Replace it with tcg_gen_ext16u_tl. In four places we can combine thatwith a previous move into cpu_T0, and in one place we can infer thatthe zero-extension has already happened via the previous load.
target-i386: Remove gen_op_andl_T0_im
target-i386: Remove gen_op_st_T0_A0
target-i386: Remove gen_op_st_T1_A0
target-i386: Fix typo in gen_push_T1
By inspection, obviously we should be storing T1 not T0.This could only happen for x86_64 in 64-bit mode with 0x66prefix to call insn -- i.e. never.
target-i386: Tidy mov[sz][bw]
We can use the MO_SIGN bit to tidy the reg-reg switch statementas well as pass it on to gen_op_ld_v, eliminating one call.
target-i386: Tidy movsl
Always perform a sign-extending load. In the extremely unlikelycase that we've used an 0x66 prefix, the extension to 64-bits isunnecessary but not wrong; the store will still examine only 16 bits.
target-i386: Remove unused arguments to gen_lea_modrm
The reg_ptr and offset_ptr outputs are universally unused.
target-i386: Use MO_BE for movbe
Fold the bswap into the memory operation.
target-i386: Tidy gen_op_mov_TN_reg+tcg_gen_trunc_tl_i32
For the 16 and 32-bit cases, we don't need to truncate viaa temporary register.
target-i386: Tidy load + truncate
We can now use tcg_gen_qemu_ld_i32 directly to avoid the truncation.
target-i386: Remove gen_op_ld_T0_A0
target-i386: Remove gen_op_ldu_T0_A0
target-i386: Remove gen_op_ld_T1_A0
target-i386: Remove gen_op_lds_T0_A0
Replace its users by gen_op_ld_v with the MO_SIGN bit set.
target-i386: Introduce gen_op_st_rm_T0_A0
Too many places have the same test vs OR_TMP0 to indicatea write back to memory. Hoist that to a subroutine.
target-i386: Replace OT_* constants with MO_* constants
The MO_8/16/32/64 constants have the same encoding and meaningas the OT_BYTE/WORD/LONG/QUAD. Since we rely on them being thesame, for the qemu_ld/st helpers, standardize on the common names.
target-i386: Use new tcg_gen_qemu_st_* helpers
In preference to the older helpers. Stores only in this patch.
target-i386: Use new tcg_gen_qemu_ld_* helpers
In preference to the older helpers. Loads only in this patch.
target-i386: Stop encoding DisasContext.mem_index
Now that we don't combine mem_index with operand size info,we don't need to encode it. Which tidies many places thataccess it.
target-i386: Push DisasContext into load/store helpers
Rather than add s->mem_index into a combined size+mem_indexargument, pass the context down. This will allow cleaningup s->mem_index later.
target-i386: Fix addr32 prefix in gen_lea_modrm
Fix the following run-test-x86_64 testsuite failures:
-lea (%eax) = 0000000000000001-lea (%ebx) = 0000000000000002-lea (%ecx) = 0000000000000004-lea (%edx) = 0000000000000008-lea (%%esi) = 0000000000000010...
target-i386: yield to another VCPU on PAUSE
After commit b1bbfe7 (aio / timers: On timer modification, qemu_notifyor aio_notify, 2013-08-21) FreeBSD guests report a huge slowdown.
The problem shows up as soon as FreeBSD turns out its periodic (~1 ms)tick, but the timers are only the trigger for a pre-existing problem....
tcg: Move helper registration into tcg_context_init
No longer needs to be done on a per-target basis.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-i386: Only provide CMOV and friends if feature bit set
The instructions CMOVcc, FCMOVcc and F[U]COMI[P] should only bepresent if the CMOV feature bit is set. Add missing feature bitchecks so we correctly fault if emulating a 486 or 586.This fixes bug LP:1201446....
tcg: Change tcg_gen_exit_tb argument to uintptr_t
And update all users.
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>Signed-off-by: Richard Henderson <rth@twiddle.net>
cpu: Move singlestep_enabled field from CPU_COMMON to CPUState
Prepares for changing cpu_single_step() argument to CPUState.
Acked-by: Michael Walle <michael@walle.cc> (for lm32)Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Change gen_intermediate_code_internal() argument to X86CPU
Also use bool type while at it.
Prepares for moving singlestep_enabled field to CPUState.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Andreas Färber <afaerber@suse.de>
target-i386: Fix aflag logic for CODE64 and the 0x67 prefix
The code reorganization in commit 4a6fd938 broke handling of PREFIX_ADR.While fixing this, tidy and comment the code so that it's more obviouswhat's going on in setting both aflag and dflag.
The TARGET_X86_64 ifdef can be eliminated because CODE64 expands to the...
target-i386: ROR r8/r16 imm instruction fix
Fix EFLAGS corruption by ROR r8/r16 imm instruction located at the endof the TB, similarly to commit 089305ac for the non-immediate case.
Reported-by: Hervé Poussineau <hpoussin@reactos.org>Reviewed-by: Richard Henderson <rth@twiddle.net>...
target-i386: Replace cpuid_*features fields with a feature word array
This replaces the feature-bit fields on both X86CPU and x86_def_tstructs with an array.
With this, we will be able to simplify code that simply does the sameoperation on all feature words (e.g. kvm_check_features_against_host(),...
i386 ROR r8/r16 instruction fix
Fixed EFLAGS corruption by ROR r8/r16 instruction located at the end of the TB.
Signed-off-by: Pavel Dovgalyuk <pavel.dovgaluk@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: add AES-NI instructions
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: add pclmulqdq instruction
Reviewed-by: Richard Henderson <rth@twiddle.net>Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: SSE4.1: fix pinsrb instruction
gen_op_mov_TN_reg() loads the value in cpu_T0, so this temporary shouldbe used instead of cpu_tmp0.
Reviewed-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-i386: Fix flags computation for ADOX
When starting from CC_OP_DYNAMIC, and issuing adox before adcx,a typo used the wrong value for the resulting CC_OP.
Cc: Blue Swirl <blauwirbel@gmail.com>Reported-by: Torbjorn Granlund <tg@gmplib.org>Signed-off-by: Richard Henderson <rth@twiddle.net>...
Fix typos and misspellings
Fix various typos and misspellings. The bulk of these were found withcodespell.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>Reviewed-by: Stefan Weil <sw@weilnetz.de>Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
gen-icount.h: Rename gen_icount_start/end to gen_tb_start/end
The gen_icount_start/end functions are now somewhat misnamed since theyare useful for generic "start/end of TB" code, used for more than justicount. Rename them to gen_tb_start/end.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>...
target-i386: Use mulu2 and muls2
These correspond very closely to the insns that we're emulating.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-i386: Use add2 to implement the ADX extension
target-i386: Use movcond to implement shift flags.
With this being all straight-line code, it can get deletedwhen the cc variables die.
target-i386: Use movcond to implement rotate flags.
target-i386: Discard CC_OP computation in set_cc_op also
The shift and rotate insns use movcond to set CC_OP, and thusachieve a conditional EFLAGS setting. By discarding CC_OP ina later flags setting insn, we can discard that movcond.
target-i386: Use movcond to implement shiftd.
target-i386: Implement ADX extension
target-i386: Implement tzcnt and fix lzcnt
We weren't computing flags for lzcnt at all. At the same time,adjust the implementation of bsf/bsr to avoid the local branch,using movcond instead.
target-i386: Add CC_OP_CLR
Special case xor with self. We need not even store the knownzero into cc_src.
target-i386: Implement BZHI
target-i386: Implement MULX
target-i386: Implement PDEP, PEXT
target-i386: Implement SHLX, SARX, SHRX
target-i386: Implement RORX
target-i386: Implement BLSR, BLSMSK, BLSI
Do all of group 17 at one time for ease.
target-i386: Decode the VEX prefixes
No actual required uses of these encodings yet.
target-i386: Implement MOVBE
target-i386: Implement ANDN
As this is the first of the BMI insns to be implemented,this carries quite a bit more baggage than normal.
target-i386: Implement BEXTR
target-i386: Tidy prefix parsing
Avoid duplicating switch statement between 32 and 64-bit modes.
target-i386: Use CC_SRC2 for ADC and SBB
Add another slot in ENV and store two of the three inputs. This lets usdo less work when carry-out is not needed, and avoids the unpredictableCC_OP after translating these insns.
target-i386: Make helper_cc_compute_{all,c} const
Pass the data in explicitly, rather than indirectly via env.This avoids all sorts of unnecessary register spillage.
target-i386: use gen_op for cmps/scas
Replace low-level ops with a higher-level "cmp %al, (A0)" in the caseof scas, and "cmp T0, (A0)" in the case of cmps.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>Signed-off-by: Richard Henderson <rth@twiddle.net>
target-i386: introduce gen_jcc1_noeob
A jump that ends a basic block or otherwise falls back to CC_OP_DYNAMICwill always have to call gen_op_set_cc_op. However, not all jumps enda basic block, so introduce a variant that does not do this.
This was partially undone earlier (i386: drop cc_op argument of gen_jcc1),...
target-i386: Update cc_op before TCG branches
Placing the CC_OP_DYNAMIC at the join is less effective thanbefore the branch, as the branch will have forced global registersto their home locations. This way we have a chance to discardCC_SRC2 before it gets stored....
target-i386: optimize flags checking after sub using CC_SRCT
After a comparison or subtraction, the original value of the LHS willcurrently be reconstructed using an addition. However, in most casesit is already available: store it in a temp-local variable and save 1...
target-i386: optimize setcc instructions
Reconstruct the arguments for complex conditions involving CC_OP_SUBx (BE,L, LE). In the others do it via setcond and gen_setcc_slow (which isnot that slow in many cases).
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>...
target-i386: introduce CCPrepare
Introduce a struct that describes how to build a cond operationthat checks for a given x86 condition code. For now, just changegen_compute_eflags_ to return the new struct, generate code forthe CCPrepare struct, and go on as before....
target-i386: introduce gen_prepare_cc
This makes the i386 front-end able to create CCPrepare structs for allcondition, not just those that come from a single flag. In particular,JCC_L and JCC_LE can be optimized because gen_prepare_cc is not forcedto return a result in bit 0 (unlike gen_setcc_slow)....
target-i386: use CCPrepare to generate conditional jumps
This simplifies all the jump generation code. CCPrepare allows thecode to create an efficient brcond always, so there is no need toduplicate the setcc and jcc code.
target-i386: inline gen_prepare_cc_slow
target-i386: cleanup temporary macros for CCPrepare
target-i386: introduce gen_cmovcc1
target-i386: expand cmov via movcond
target-i386: kill cpu_T3
It is almost unused, and it is simpler to pass a TCG value directlyto gen_shiftd_rm_T1_T3. This value is then written to t2 withoutgoing through a temporary register.